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Merge pull request #1217 from jordancarlin/riscv-arch-test-updates

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riscv-arch-test updates
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David Harris 2024-12-31 12:13:56 -08:00 • committed by GitHub
commit 08cf6cc137
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3 changed files with 112 additions and 8 deletions
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2
addins/riscv-arch-test

@ -1 +1 @@
Subproject commit a079bb263b04dde4028efee134f3a4e42799a5ca
Subproject commit 832ab11c093f332ef83ca9c0ef55845071a7cb3d

18
testbench/testbench.sv
View file

@ -145,7 +145,9 @@ module testbench;
"arch64i": tests = arch64i;
"arch64priv": tests = arch64priv;
"arch64c": if (P.ZCA_SUPPORTED)
if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
if (P.ZICSR_SUPPORTED)
if (P.ZCD_SUPPORTED) tests = {arch64c, arch64cpriv, arch64zcd};
else tests = {arch64c, arch64cpriv};
else tests = {arch64c};
"arch64m": if (P.M_SUPPORTED) tests = arch64m;
"arch64a_amo": if (P.ZAAMO_SUPPORTED) tests = arch64a_amo;
@ -172,7 +174,9 @@ module testbench;
"arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs;
"arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz;
"arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb;
"arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh;
"arch64zfh": if (P.ZFH_SUPPORTED)
if (P.D_SUPPORTED) tests = {arch64zfh, arch64zfh_d};
else tests = arch64zfh;
"arch64zfh_fma": if (P.ZFH_SUPPORTED) tests = arch64zfh_fma;
"arch64zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch64zfh_divsqrt;
"arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf;
@ -192,7 +196,11 @@ module testbench;
"arch32i": tests = arch32i;
"arch32priv": tests = arch32priv;
"arch32c": if (P.C_SUPPORTED)
if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
if (P.ZICSR_SUPPORTED)
if (P.ZCF_SUPPORTED)
if (P.ZCD_SUPPORTED) tests = {arch32c, arch32cpriv, arch32zcf, arch32zcd};
else tests = {arch32c, arch32cpriv, arch32zcf};
else tests = {arch32c, arch32cpriv};
else tests = {arch32c};
"arch32m": if (P.M_SUPPORTED) tests = arch32m;
"arch32a_amo": if (P.ZAAMO_SUPPORTED) tests = arch32a_amo;
@ -216,7 +224,9 @@ module testbench;
"arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs;
"arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz;
"arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb;
"arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh;
"arch32zfh": if (P.ZFH_SUPPORTED)
if (P.D_SUPPORTED) tests = {arch32zfh, arch32zfh_d};
else tests = arch32zfh;
"arch32zfh_fma": if (P.ZFH_SUPPORTED) tests = arch32zfh_fma;
"arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt;
"arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf;

100
testbench/tests.vh
View file

@ -241,22 +241,30 @@ string arch64pmp[] = '{
string arch32vm_sv32[] = '{
`RISCVARCHTEST,
"rv32i_m/vm_sv32/src/mstatus_tvm_test.S",
"rv32i_m/vm_sv32/src/pmp_check_on_pa_S_mode.S",
"rv32i_m/vm_sv32/src/pmp_check_on_pa_U_mode.S",
"rv32i_m/vm_sv32/src/pmp_check_on_pte_S_mode.S",
"rv32i_m/vm_sv32/src/pmp_check_on_pte_U_mode.S",
"rv32i_m/vm_sv32/src/satp_access_tests.S",
"rv32i_m/vm_sv32/src/vm_A_and_D_S_mode.S",
"rv32i_m/vm_sv32/src/vm_A_and_D_U_mode.S",
"rv32i_m/vm_sv32/src/vm_invalid_pte_S_mode.S",
"rv32i_m/vm_sv32/src/vm_invalid_pte_U_mode.S",
"rv32i_m/vm_sv32/src/vm_misaligned_S_mode.S",
"rv32i_m/vm_sv32/src/vm_misaligned_U_mode.S",
"rv32i_m/vm_sv32/src/vm_mprv_S_mode.S",
"rv32i_m/vm_sv32/src/vm_mprv_U_mode.S",
"rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_set_S_mode.S",
"rv32i_m/vm_sv32/src/vm_mprv_U_set_sum_unset_S_mode.S",
"rv32i_m/vm_sv32/src/vm_mxr_S_mode.S",
"rv32i_m/vm_sv32/src/vm_mxr_U_mode.S",
"rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_S_mode.S",
"rv32i_m/vm_sv32/src/vm_nleaf_pte_level0_U_mode.S",
"rv32i_m/vm_sv32/src/vm_reserved_pte_S_mode.S",
"rv32i_m/vm_sv32/src/vm_reserved_pte_U_mode.S",
"rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_S_mode.S",
"rv32i_m/vm_sv32/src/vm_reserved_rsw_pte_U_mode.S",
"rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_S_mode.S",
"rv32i_m/vm_sv32/src/vm_reserved_rwx_pte_U_mode.S",
"rv32i_m/vm_sv32/src/vm_sum_set_S_mode.S",
"rv32i_m/vm_sv32/src/vm_sum_unset_S_mode.S",
"rv32i_m/vm_sv32/src/vm_U_Bit_set_U_mode.S",
@ -528,6 +536,15 @@ string arch64cpriv[] = '{
"rv64i_m/C/src/cebreak-01.S"
};
// Tests commented out pending riscv-arch-test issue #590
string arch64zcd[] = '{
// `RISCVARCHTEST,
"rv64i_m/D_Zcd/src/c.fld-01.S",
"rv64i_m/D_Zcd/src/c.fldsp-01.S",
"rv64i_m/D_Zcd/src/c.fsd-01.S",
"rv64i_m/D_Zcd/src/c.fsdsp-01.S"
};
string arch64i[] = '{
`RISCVARCHTEST,
"rv64i_m/I/src/add-01.S",
@ -1000,10 +1017,23 @@ string arch64zfh[] = '{
"rv64i_m/Zfh/src/fadd_b7-01.S",
"rv64i_m/Zfh/src/fadd_b8-01.S",
"rv64i_m/Zfh/src/fclass_b1-01.S",
"rv64i_m/Zfh/src/fcvt.h.s_b1-01.S",
"rv64i_m/Zfh/src/fcvt.h.s_b22-01.S",
"rv64i_m/Zfh/src/fcvt.h.s_b23-01.S",
"rv64i_m/Zfh/src/fcvt.h.s_b24-01.S",
"rv64i_m/Zfh/src/fcvt.h.s_b27-01.S",
"rv64i_m/Zfh/src/fcvt.h.s_b28-01.S",
"rv64i_m/Zfh/src/fcvt.h.s_b29-01.S",
"rv64i_m/Zfh/src/fcvt.h.w_b25-01.S",
"rv64i_m/Zfh/src/fcvt.h.w_b26-01.S",
"rv64i_m/Zfh/src/fcvt.h.wu_b25-01.S",
"rv64i_m/Zfh/src/fcvt.h.wu_b26-01.S",
"rv64i_m/Zfh/src/fcvt.s.h_b22-01.S",
"rv64i_m/Zfh/src/fcvt.s.h_b23-01.S",
"rv64i_m/Zfh/src/fcvt.s.h_b24-01.S",
"rv64i_m/Zfh/src/fcvt.s.h_b27-01.S",
"rv64i_m/Zfh/src/fcvt.s.h_b28-01.S",
"rv64i_m/Zfh/src/fcvt.s.h_b29-01.S",
"rv64i_m/Zfh/src/fcvt.w.h_b1-01.S",
"rv64i_m/Zfh/src/fcvt.w.h_b22-01.S",
"rv64i_m/Zfh/src/fcvt.w.h_b23-01.S",
@ -1130,7 +1160,23 @@ string arch64zfh[] = '{
"rv64i_m/Zfh/src/fnmsub_b8-01.S"
};
string arch64zfh_d[] = '{
// `RISCVARCHTEST,
"rv64i_m/Zfh/src/fcvt.d.h_b1-01.S",
"rv64i_m/Zfh/src/fcvt.d.h_b22-01.S",
"rv64i_m/Zfh/src/fcvt.d.h_b23-01.S",
"rv64i_m/Zfh/src/fcvt.d.h_b24-01.S",
"rv64i_m/Zfh/src/fcvt.d.h_b27-01.S",
"rv64i_m/Zfh/src/fcvt.d.h_b28-01.S",
"rv64i_m/Zfh/src/fcvt.d.h_b29-01.S",
"rv64i_m/Zfh/src/fcvt.h.d_b1-01.S",
"rv64i_m/Zfh/src/fcvt.h.d_b22-01.S",
"rv64i_m/Zfh/src/fcvt.h.d_b23-01.S",
"rv64i_m/Zfh/src/fcvt.h.d_b24-01.S",
"rv64i_m/Zfh/src/fcvt.h.d_b27-01.S",
"rv64i_m/Zfh/src/fcvt.h.d_b28-01.S",
"rv64i_m/Zfh/src/fcvt.h.d_b29-01.S"
};
string arch64d_fma[] = '{
`RISCVARCHTEST,
@ -2413,10 +2459,23 @@ string arch32zfh[] = '{
"rv32i_m/Zfh/src/fadd_b7-01.S",
"rv32i_m/Zfh/src/fadd_b8-01.S",
"rv32i_m/Zfh/src/fclass_b1-01.S",
"rv32i_m/Zfh/src/fcvt.h.s_b1-01.S",
"rv32i_m/Zfh/src/fcvt.h.s_b22-01.S",
"rv32i_m/Zfh/src/fcvt.h.s_b23-01.S",
"rv32i_m/Zfh/src/fcvt.h.s_b24-01.S",
"rv32i_m/Zfh/src/fcvt.h.s_b27-01.S",
"rv32i_m/Zfh/src/fcvt.h.s_b28-01.S",
"rv32i_m/Zfh/src/fcvt.h.s_b29-01.S",
"rv32i_m/Zfh/src/fcvt.h.w_b25-01.S",
"rv32i_m/Zfh/src/fcvt.h.w_b26-01.S",
"rv32i_m/Zfh/src/fcvt.h.wu_b25-01.S",
"rv32i_m/Zfh/src/fcvt.h.wu_b26-01.S",
"rv32i_m/Zfh/src/fcvt.s.h_b22-01.S",
"rv32i_m/Zfh/src/fcvt.s.h_b23-01.S",
"rv32i_m/Zfh/src/fcvt.s.h_b24-01.S",
"rv32i_m/Zfh/src/fcvt.s.h_b27-01.S",
"rv32i_m/Zfh/src/fcvt.s.h_b28-01.S",
"rv32i_m/Zfh/src/fcvt.s.h_b29-01.S",
"rv32i_m/Zfh/src/fcvt.w.h_b1-01.S",
"rv32i_m/Zfh/src/fcvt.w.h_b22-01.S",
"rv32i_m/Zfh/src/fcvt.w.h_b23-01.S",
@ -2525,6 +2584,24 @@ string arch32zfh[] = '{
"rv32i_m/Zfh/src/fnmsub_b8-01.S"
};
string arch32zfh_d[] = '{
// `RISCVARCHTEST,
"rv32i_m/Zfh/src/fcvt.d.h_b1-01.S",
"rv32i_m/Zfh/src/fcvt.d.h_b22-01.S",
"rv32i_m/Zfh/src/fcvt.d.h_b23-01.S",
"rv32i_m/Zfh/src/fcvt.d.h_b24-01.S",
"rv32i_m/Zfh/src/fcvt.d.h_b27-01.S",
"rv32i_m/Zfh/src/fcvt.d.h_b28-01.S",
"rv32i_m/Zfh/src/fcvt.d.h_b29-01.S",
"rv32i_m/Zfh/src/fcvt.h.d_b1-01.S",
"rv32i_m/Zfh/src/fcvt.h.d_b22-01.S",
"rv32i_m/Zfh/src/fcvt.h.d_b23-01.S",
"rv32i_m/Zfh/src/fcvt.h.d_b24-01.S",
"rv32i_m/Zfh/src/fcvt.h.d_b27-01.S",
"rv32i_m/Zfh/src/fcvt.h.d_b28-01.S",
"rv32i_m/Zfh/src/fcvt.h.d_b29-01.S"
};
string arch32zfaf[] = '{
`RISCVARCHTEST,
"rv32i_m/F_Zfa/src/fround_b1-01.S",
@ -3353,6 +3430,23 @@ string arch32cpriv[] = '{
"rv32i_m/C/src/cebreak-01.S"
};
// Tests commented out pending riscv-arch-test issue #590
string arch32zcf[] = '{
// `RISCVARCHTEST,
// "rv32i_m/F_Zcf/src/c.flw-01.S",
// "rv32i_m/F_Zcf/src/c.flwsp-01.S",
// "rv32i_m/F_Zcf/src/c.fsw-01.S",
"rv32i_m/F_Zcf/src/c.fswsp-01.S"
};
// Tests commented out pending riscv-arch-test issue #590
string arch32zcd[] = '{
// `RISCVARCHTEST,
"rv32i_m/D_Zcd/src/c.fld-01.S",
// "rv32i_m/D_Zcd/src/c.fldsp-01.S",
"rv32i_m/D_Zcd/src/c.fsd-01.S",
"rv32i_m/D_Zcd/src/c.fsdsp-01.S"
};
string arch32i[] = '{
`RISCVARCHTEST,