Added performance and distribution to sim and wrapper. Added colors too!

bin/CacheSim.py

@@ -36,6 +36,8 @@
 # This helps avoid unexpected logger behavior.
 # With verbose mode off, the simulator only reports mismatches between its and Wally's behavior.
 # With verbose mode on, the simulator logs each access into the cache.
+# Add -p or --perf to report the hit/miss ratio. 
+# Add -d or --dist to report the distribution of loads, stores, and atomic ops.
 
 import sys
 import math
@@ -197,12 +199,24 @@ if __name__ == "__main__":
     parser.add_argument('taglen', type=int, help="Length of the tag in bits", metavar="T")
     parser.add_argument('-f', "--file", required=True, help="Log file to simulate from")
     parser.add_argument('-v', "--verbose", action='store_true', help="verbose/full-trace mode")
+    parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
+    parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
 
     args = parser.parse_args()
     cache = Cache(args.numlines, args.numways, args.addrlen, args.taglen)
     extfile = os.path.expanduser(args.file)
     nofails = True
 
+    if args.perf:
+        hits = 0
+        misses = 0
+
+    if args.dist:
+        loads = 0
+        stores = 0
+        atoms = 0
+        totalops = 0
+
     with open(extfile, "r") as f:
         for ln in f:
             ln = ln.strip()
@@ -217,6 +231,9 @@ if __name__ == "__main__":
                         print("New Test")
                         
             else:
+                if args.dist:
+                    totalops += 1
+                
                 if lninfo[1] == 'F':
                     cache.flush()
                     if args.verbose:
@@ -229,11 +246,37 @@ if __name__ == "__main__":
                     addr = int(lninfo[0], 16)
                     iswrite = lninfo[1] == 'W' or lninfo[1] == 'A'
                     result = cache.cacheaccess(addr, iswrite)
+                    
                     if args.verbose:
                         tag, setnum, offset = cache.splitaddr(addr)
                         print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result)
+                    
+                    if args.perf:
+                        if result == 'H':
+                            hits += 1
+                        else:
+                            misses += 1
+                    
+                    if args.dist:
+                        if lninfo[1] == 'R':
+                            loads += 1
+                        elif lninfo[1] == 'W':
+                            stores += 1
+                        elif lninfo[1] == 'A':
+                            atoms += 1
+                    
                     if not result == lninfo[2]:
                         print("Result mismatch at address", lninfo[0]+ ". Wally:", lninfo[2]+", Sim:", result)
                         nofails = False
+    if args.dist:
+        percent_loads = str(round(100*loads/totalops))
+        percent_stores = str(round(100*stores/totalops))
+        percent_atoms = str(round(100*atoms/totalops))
+        print("This log had", percent_loads+"% loads,", percent_stores+"% stores, and", percent_atoms+"% atomic operations.")
+    
+    if args.perf:
+        ratio = round(hits/misses,3)
+        print("There were", hits, "hits and", misses, "misses. The hit/miss ratio was", str(ratio)+".")
+    
     if nofails:
         print("SUCCESS! There were no mismatches between Wally and the sim.")

sim/rv64gc_CacheSim.py

@@ -4,8 +4,8 @@
 ## CacheSimTest.py
 ##
 ## Written: lserafini@hmc.edu
-## Created: 4 April 2023
-## Modified: 5 April 2023
+## Created: 11 April 2023
+## Modified: 12 April 2023
 ##
 ## Purpose: Run the cache simulator on each rv64gc test suite in turn. 
 ##
@@ -28,12 +28,24 @@
 ################################################################################################
 import sys
 import os
+import argparse
 
 # NOTE: make sure testbench.sv has the ICache and DCache loggers enabled!
 # This does not check the test output for correctness, run regression for that.
 
+class bcolors:
+    HEADER = '\033[95m'
+    OKBLUE = '\033[94m'
+    OKCYAN = '\033[96m'
+    OKGREEN = '\033[92m'
+    WARNING = '\033[93m'
+    FAIL = '\033[91m'
+    ENDC = '\033[0m'
+    BOLD = '\033[1m'
+    UNDERLINE = '\033[4m'
 
-tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
+# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
+tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m",             
              "arch64zi", "wally64a", "wally64periph", "wally64priv", 
              "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
              "imperas64f", "imperas64d", "imperas64c", "imperas64i"]
@@ -42,12 +54,24 @@ cachetypes = ["ICache", "DCache"]
 simdir = os.path.expanduser("~/cvw/sim")
 
 if __name__ == '__main__':
+    parser = argparse.ArgumentParser(description="Runs the cache simulator on all rv64gc test suites")
+    parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
+    parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
+
+    args = parser.parse_args()
+
     testcmd = "vsim -do \"do wally-batch.do rv64gc {}\" -c > /dev/null"
     cachecmd = "CacheSim.py 64 4 56 44 -f {}"
+    
+    if args.perf:
+        cachecmd += " -p"
+    if args.dist:
+        cachecmd += " -d"
+    
     for test in tests64gc:
-        # print(testcmd.format(test))
-        print("Commencing test", test)
+        print(f"{bcolors.HEADER}Commencing test", test+f":{bcolors.ENDC}")
         os.system(testcmd.format(test))
         for cache in cachetypes:
-            print("Running the", cache, "simulator.")
+            print(f"{bcolors.OKCYAN}Running the", cache, f"simulator.{bcolors.ENDC}")
             os.system(cachecmd.format(cache+".log"))
+        print()