github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-06-27 17:01:20 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Merge branch 'main' of https://github.com/openhwgroup/cvw into ccov

Browse source
This commit is contained in:
Corey Hickson 2025-04-02 00:29:24 -07:00
commit 0995c85452
29 changed files with 276 additions and 439 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/ifu/ifu.sv
View file

@ -379,7 +379,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
assign InstrD = InstrRawD;
assign IllegalIEUInstrD = IllegalBaseInstrD;
end
assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD;
assign IllegalIEUFPUInstrD = IllegalIEUInstrD & (IllegalFPUInstrD | !P.F_SUPPORTED);
// Misaligned PC logic
// Instruction address misalignment only from br/jal(r) instructions.

4
src/privileged/csrsr.sv
View file

@ -106,8 +106,8 @@ module csrsr import cvw::*; #(parameter cvw_t P) (
always_comb
if (CSRWriteValM[12:11] == P.U_MODE & P.U_SUPPORTED) STATUS_MPP_NEXT = P.U_MODE;
else if (CSRWriteValM[12:11] == P.S_MODE & P.S_SUPPORTED) STATUS_MPP_NEXT = P.S_MODE;
else if (CSRWriteValM[12:11] == 2'b10) STATUS_MPP_NEXT = STATUS_MPP; // do not change MPP when trying to write reserved 10
else STATUS_MPP_NEXT = P.M_MODE;
else if (CSRWriteValM[12:11] == P.M_MODE) STATUS_MPP_NEXT = P.M_MODE;
else STATUS_MPP_NEXT = STATUS_MPP; // do not change MPP when trying to write reserved 10 or unsupported mode
///////////////////////////////////////////
// Endianness logic Privileged Spec 3.1.6.4