Merge branch 'main' into Zicclsm

.gitattributes

@@ -1 +0,0 @@
-pipelined/busybear_boot/* filter=lfs diff=lfs merge=lfs -text

.gitignore

@@ -62,6 +62,7 @@ examples/fp/fpcalc/fpcalc
 examples/C/inline/inline
 examples/C/sum_mixed/sum_mixed
 examples/asm/trap/trap
+examples/asm/etc/pause
 src/fma/fma16_testgen
 linux/devicetree/debug/*
 !linux/devicetree/debug/dump-dts.sh
@@ -82,7 +83,6 @@ synthDC/ppa/plots
 synthDC/wallyplots/
 synthDC/runArchive
 synthDC/hdl
-synthDC/wrappers
 sim/power.saif
 tests/fp/vectors/*.tv
 synthDC/Summary.csv

config/shared/config-shared.vh

@@ -24,6 +24,7 @@ localparam SV48 = 4'd9;
 localparam A_SUPPORTED = ((MISA >> 0) % 2 == 1);
 localparam B_SUPPORTED = ((ZBA_SUPPORTED | ZBB_SUPPORTED | ZBC_SUPPORTED | ZBS_SUPPORTED));// not based on MISA
 localparam C_SUPPORTED = ((MISA >> 2) % 2 == 1);
+localparam COMPRESSED_SUPPORTED = C_SUPPORTED | ZCA_SUPPORTED;
 localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1);
 localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1);
 localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1);

config/shared/parameter-defs.vh

@@ -119,6 +119,7 @@ localparam cvw_t P = '{
   A_SUPPORTED : A_SUPPORTED,
   B_SUPPORTED : B_SUPPORTED,
   C_SUPPORTED : C_SUPPORTED,
+  COMPRESSED_SUPPORTED : COMPRESSED_SUPPORTED,
   D_SUPPORTED : D_SUPPORTED,
   E_SUPPORTED : E_SUPPORTED,
   F_SUPPORTED : F_SUPPORTED,

examples/asm/etc/Makefile

@@ -0,0 +1,11 @@
+TARGET = pause
+
+$(TARGET).objdump: $(TARGET)
+	riscv64-unknown-elf-objdump -D $(TARGET) > $(TARGET).objdump
+    
+pause: pause.S Makefile
+	riscv64-unknown-elf-gcc -o pause -march=rv32ia_zihintpause -mabi=ilp32 -mcmodel=medany \
+	    -nostartfiles -T../../link/link.ld  pause.S
+
+clean:
+	rm -f $(TARGET) $(TARGET).objdump

examples/asm/etc/pause.S

@@ -0,0 +1,25 @@
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+
+
+la a0, lock
+
+spinlock:				# address of lock is in a0
+	lr.w t0, (a0)		# read the lock
+	bnez t0, retry	    # spin until free
+	li   t1, 1          
+	sc.w t0, t1, (a0)	# try to write a 1 to take lock
+	bnez t0, retry	    # spin until successful
+	ret				    # got the lock!
+retry:				    # no lock yet
+	pause				# pause hint to reduce spin power
+	j spinlock			# try again
+
+
+self_loop:
+    j self_loop
+
+.data
+lock:   
+    .word 1

src/cvw.sv

@@ -197,6 +197,7 @@ typedef struct packed {
   logic A_SUPPORTED;
   logic B_SUPPORTED;
   logic C_SUPPORTED;
+  logic COMPRESSED_SUPPORTED;  // C or ZCA
   logic D_SUPPORTED;
   logic E_SUPPORTED;
   logic F_SUPPORTED;

src/ebu/ebufsmarb.sv

@@ -116,5 +116,5 @@ module ebufsmarb (
   //  11          16     15
   always_comb 
     if (HBURST[2:1] == 2'b00) Threshold = 4'b0000;
-    else                      Threshold = (2 << HBURST[2:1]) - 1;
+    else                      Threshold = ('d2 << HBURST[2:1]) - 'd1;
 endmodule

src/generic/mem/ram1p1rwbe.sv

@@ -90,12 +90,12 @@ module ram1p1rwbe import cvw::*; #(parameter cvw_t P, parameter DEPTH=64, WIDTH=
       end
     end
     
-    // Read
+    // Combinational read: register address and read after clock edge
     logic [$clog2(DEPTH)-1:0] addrd;
     flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
     assign dout = RAM[addrd];
 
-    /*      // Read
+    /*      // Alternate read logic reads the old contents of mem[addr].  Increases setup time and adds dout reg, but reduces clk to q
      always_ff @(posedge clk) 
      if(ce) dout <= #1 mem[addr]; */
 

src/generic/mem/ram1p1rwe.sv

@@ -71,12 +71,12 @@ module ram1p1rwe import cvw::* ; #(parameter cvw_t P,
     // The version with byte write enables it correctly infers block ram.
     integer i;
 
-    // Read
+    // Combinational read: register address and read after clock edge
     logic [$clog2(DEPTH)-1:0] addrd;
     flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
     assign dout = RAM[addrd];
 
-    /*      // Read
+    /*      // Alternate read logic reads the old contents of mem[addr].  Increases setup time and adds dout reg, but reduces clk to q
      always_ff @(posedge clk) 
      if(ce) dout <= #1 mem[addr]; */
 

src/generic/mem/rom1p1r.sv

@@ -36,6 +36,9 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
 
    // Core Memory
    logic [DATA_WIDTH-1:0]    ROM [(2**ADDR_WIDTH)-1:0];
+   
+   // dh 10/30/23 ROM macros are presently commented out
+   // because they don't point to a generated ROM
 /*   if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 64)) begin
       rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
 
@@ -43,9 +46,9 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
       rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));      
 
    end else begin */
-   always @ (posedge clk) begin
-   if(ce) dout <= ROM[addr];    
-   end
+   always @ (posedge clk) 
+      if(ce) dout <= ROM[addr];    
+   
    
    // for FPGA, initialize with zero-stage bootloader
    if(PRELOAD_ENABLED) begin

src/ifu/bpred/icpred.sv

@@ -54,7 +54,7 @@ module icpred import cvw::*;  #(parameter cvw_t P,
     logic     cjal, cj, cjr, cjalr, CJumpF, CBranchF;
     logic     NCJumpF, NCBranchF;
 
-    if(P.C_SUPPORTED) begin
+    if(P.COMPRESSED_SUPPORTED) begin
       logic [4:0] CompressedOpcF;
       assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
       assign cjal = CompressedOpcF == 5'h09 & P.XLEN == 32;
@@ -70,13 +70,13 @@ module icpred import cvw::*;  #(parameter cvw_t P,
     assign NCJumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F;
     assign NCBranchF = PostSpillInstrRawF[6:0] == 7'h63;
     
-    assign BPBranchF = NCBranchF | (P.C_SUPPORTED & CBranchF);
-    assign BPJumpF = NCJumpF | (P.C_SUPPORTED & (CJumpF));
+    assign BPBranchF = NCBranchF | (P.COMPRESSED_SUPPORTED & CBranchF);
+    assign BPJumpF = NCJumpF | (P.COMPRESSED_SUPPORTED & (CJumpF));
     assign BPReturnF = (NCJumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 & PostSpillInstrRawF[11:7] == 5'b0) | // return must return to ra or r5
-        (P.C_SUPPORTED & cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
+        (P.COMPRESSED_SUPPORTED & cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
     
     assign BPCallF = (NCJumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // call(r) must link to ra or x5
-        (P.C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
+        (P.COMPRESSED_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
 
   end else begin
     // This section connects the BTB's instruction class prediction.

src/ifu/ifu.sv

@@ -144,7 +144,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   // Spill Support
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  if(P.C_SUPPORTED) begin : Spill
+  if(P.COMPRESSED_SUPPORTED) begin : Spill
     spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF, 
       .IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
   end else begin : NoSpill
@@ -366,7 +366,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
    
   // expand 16-bit compressed instructions to 32 bits
-  if (P.C_SUPPORTED | P.ZCA_SUPPORTED) begin
+  if (P.COMPRESSED_SUPPORTED) begin
     logic IllegalCompInstrD;
     decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); 
     assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
@@ -386,27 +386,34 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   // only IALIGN=32, the two low bits (mepc[1:0]) are always zero.
   // Spec 3.1.14
   // Traps: Can’t happen.  The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4.  See 3.1.7 of the privileged spec.
-  assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.C_SUPPORTED) & PCSrcE;
+  assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.COMPRESSED_SUPPORTED) & PCSrcE;
   flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
 
-  // Instruction and PC/PCLink pipeline registers
+  // Instruction and PC pipeline registers
   // Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.
   mux2    #(32)     FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);
   mux2    #(32)     FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
   flopenr #(32)     InstrEReg(clk, reset, ~StallE, NextInstrD, InstrE);
-  flopenr #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
   flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
-  flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
-  //flopenr #(P.XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
-  //flopenr #(P.XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
+
+  // InstrM is only needed with CSRs or atomic operations
+  if (P.ZICSR_SUPPORTED | P.A_SUPPORTED)
+    flopenr #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
+  else assign InstrM = 0;
+  // PCM is only needed with CSRs or branch prediction
+  if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED) 
+    flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
+  else assign PCM = 0;
 
   flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
   flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
-  assign PCLinkE = PCE + (CompressedE ? 2 : 4);
+  assign PCLinkE = PCE + (CompressedE ? 'd2 : 'd4); // 'd4 means 4 but stops Design Compiler complaining about signed to unsigned conversion
 
   // pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
-  flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
-  flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
-  flopenrc #(1)  CompressedMReg(clk, reset, FlushM, ~StallM, CompressedE, CompressedM);
-  mux2     #(32) InstrOrigMux(InstrM, {16'b0, InstrRawM}, CompressedM, InstrOrigM); 
+  if (P.ZICSR_SUPPORTED) begin
+    flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
+    flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
+    flopenrc #(1)  CompressedMReg(clk, reset, FlushM, ~StallM, CompressedE, CompressedM);
+    mux2     #(32) InstrOrigMux(InstrM, {16'b0, InstrRawM}, CompressedM, InstrOrigM); 
+  end else assign InstrOrigM = 0;
 endmodule

src/ifu/irom.sv

@@ -37,17 +37,21 @@ module irom import cvw::*;  #(parameter cvw_t P) (
 
   logic [P.XLEN-1:0] IROMInstrFFull;
   logic [31:0]       RawIROMInstrF;
-  logic [1:0]        AdrD;
-  flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD);
+  logic [2:1]        AdrD;
 
   rom1p1r #(ADDR_WDITH, P.XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
   if (P.XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
   else              begin
   // IROM is aligned to XLEN words, but instructions are 32 bits.  Select between the two
   // haves.  Adr is the Next PCF not PCF so we delay 1 cycle.
-    assign RawIROMInstrF = AdrD[1] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
+    flopen #(1) AdrReg2(clk, ce, Adr[2], AdrD[2]);
+    assign RawIROMInstrF = AdrD[2] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
   end
   // If the memory addres is aligned to 2 bytes return the upper 2 bytes in the lower 2 bytes.
   // The spill logic will handle merging the two together.
-  assign IROMInstrF = AdrD[0] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
+  if (P.COMPRESSED_SUPPORTED) begin
+    flopen #(1) AdrReg1(clk, ce, Adr[1], AdrD[1]);
+    assign IROMInstrF = AdrD[1] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
+  end else
+    assign IROMInstrF = RawIROMInstrF;
 endmodule  

src/lsu/swbytemask.sv

@@ -35,11 +35,12 @@ module swbytemask #(parameter WORDLEN, EXTEND = 0)(
 );
   if(EXTEND) begin
     logic [WORDLEN*2/8-1:0]              ExtendedByteMask;
-    assign ExtendedByteMask = ((2**(2**Size))-1) << Adr;
+    // 'd2 means 2, but stops Design Compiler from complaining about signed to unsigned conversion    
+    assign ExtendedByteMask = (('d2**('d2**Size))-'d1) << Adr;
     assign ByteMask = ExtendedByteMask[WORDLEN/8-1:0];
     assign ByteMaskExtended = ExtendedByteMask[WORDLEN*2/8-1:WORDLEN/8];
   end else begin    
-    assign ByteMask = ((2**(2**Size))-1) << Adr;
+    assign ByteMask = (('d2**('d2**Size))-'d1) << Adr;
     assign ByteMaskExtended = '0;
   end
 

src/privileged/csr.sv

@@ -203,7 +203,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
 
   assign CSRAdrM = InstrM[31:20];
   assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM;
-  assign NextEPCM = P.C_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment
+  assign NextEPCM = P.COMPRESSED_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment
   assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[P.XLEN-1], CSRWriteValM[3:0]};
   assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
   assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == P.M_MODE);

src/privileged/csrm.sv

@@ -94,7 +94,8 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   localparam DSCRATCH1     = 12'h7B3;
   // Constants
   localparam ZERO = {(P.XLEN){1'b0}};
-  localparam MEDELEG_MASK  = 16'hB3FF;
+  // when compressed instructions are supported, there can't be misaligned instructions
+  localparam MEDELEG_MASK  = P.COMPRESSED_SUPPORTED ? 16'hB3FE : 16'hB3FF;
   localparam MIDELEG_MASK  = 12'h222; // we choose to not make machine interrupts delegable
 
  // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop

src/privileged/trap.sv

@@ -68,7 +68,8 @@ module trap import cvw::*;  #(parameter cvw_t P) (
   assign Committed     = CommittedM | CommittedF;
   assign EnabledIntsM  = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW);
   assign ValidIntsM    = {12{~Committed}} & EnabledIntsM;
-  assign InterruptM    = (|ValidIntsM) & InstrValidM & (~wfiM | wfiW); // suppress interrupt if the memory system has partially processed a request.
+  assign InterruptM    = (|ValidIntsM) & InstrValidM & (~wfiM | wfiW); // suppress interrupt if the memory system has partially processed a request. Delay interrupt until wfi is in the W stage. 
+  // wfiW is to support possible but unlikely back to back wfi instructions. wfiM would be high in the M stage, while also in the W stage.
   assign DelegateM     = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & 
                      (PrivilegeModeW == P.U_MODE | PrivilegeModeW == P.S_MODE);
 

synthDC/Makefile

@@ -147,4 +147,4 @@ clean:
 	rm -f power.saif
 	rm -f Synopsys_stack_trace_*.txt
 	rm -f crte_*.txt
-	rm $(WALLY)/synthDC/wrappers/*
+	

synthDC/extractArea.pl

@@ -96,10 +96,11 @@ sub processRun {
         foreach my $kw (@keywords) {
            # print "$kw $line\n";
             if ($line =~ /^${kw}\s+(\S*)/) {
-                #print "$line $kw $1\n";
+                $results{$kw} = int($1);
+            } elsif ($line =~ /^${kw}__\S*\s+(\S*)/) {
                 $results{$kw} = int($1);
             }
-        }
+         }
     }
     foreach my $kw (@keywords) {
         #print "$kw\t$results{$kw}\n";

synthDC/extractSummary.py

@@ -149,9 +149,10 @@ def areaDelay(tech, delays, areas, labels, fig, ax, norm=False):
     plt.ylim(ymin=0, ymax=1.1*ytop)
     
     ax.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}'))
-
-    texts = [plt.text(delays[i], areas[i], labels[i], ha='center', va='center') for i in range(len(labels))]
-    adjust_text(texts)
+    
+    if (len(labels) > 0):
+        texts = [plt.text(delays[i], areas[i], labels[i], ha='center', va='center') for i in range(len(labels))]
+        adjust_text(texts)
     return fig
 
 
@@ -166,7 +167,7 @@ def plotFeatures(tech, width, config):
                 labels += [oneSynth.mod]
 
     if (delays == []):
-        print("No delays found for freq ", freq, ". Did you set --skyfreq and --tsmcfreq?\n")
+        print("No delays found for tech ", tech, " freq ", freq, ". Did you set --sky130freq, --sky90freq and --tsmcfreq?\n")
 
     fig, (ax) = plt.subplots(1, 1)
 
@@ -244,13 +245,15 @@ def addFO4axis(fig, ax, tech):
 if __name__ == '__main__':
 
     parser = argparse.ArgumentParser()
-    parser.add_argument("-s", "--skyfreq", type=int, default=1500, help = "Target frequency used for sky90 syntheses")
+    parser.add_argument("-s130", "--sky130freq", type=int, default=500, help = "Target frequency used for sky130 syntheses")
+    parser.add_argument("-s90", "--sky90freq", type=int, default=1500, help = "Target frequency used for sky90 syntheses")
     parser.add_argument("-t", "--tsmcfreq", type=int, default=5000, help = "Target frequency used for tsmc28 syntheses")
     args = parser.parse_args()
 
     TechSpec = namedtuple("TechSpec", "color shape targfreq fo4 add32area add32lpower add32denergy")
     techdict = {}
-    techdict['sky90'] = TechSpec('gray', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023)
+    techdict['sky130'] = TechSpec('green', 'o', args.sky130freq, 99.5e-3, 1440.600027, 714.057, 0.658023)
+    techdict['sky90'] = TechSpec('gray', 'o', args.sky90freq, 43.2e-3, 1440.600027, 714.057, 0.658023)
     techdict['tsmc28psyn'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533)
 
     current_directory = os.getcwd()
@@ -262,9 +265,12 @@ if __name__ == '__main__':
     synthsfromcsv('Summary.csv')
     freqPlot('tsmc28psyn', 'rv32', 'e')
     freqPlot('sky90', 'rv32', 'e')
+    freqPlot('sky130', 'rv32', 'e')
     plotFeatures('sky90', 'rv64', 'gc')
+    plotFeatures('sky130', 'rv64', 'gc')
     plotFeatures('tsmc28psyn', 'rv64', 'gc')
     plotConfigs('sky90', mod='orig')
+    plotConfigs('sky130', mod='orig')
     plotConfigs('tsmc28psyn', mod='orig')
     normAreaDelay(mod='orig')
     os.system("./extractArea.pl");

synthDC/scripts/synth.tcl

@@ -12,6 +12,8 @@ suppress_message {VER-130}
 # statements in initial blocks are ignored
 suppress_message {VER-281} 
 suppress_message {VER-173} 
+ # Unsupported system task '$warn'
+suppress_message {VER-274}
 
 # Enable Multicore
 set_host_options -max_cores $::env(MAXCORES)
@@ -34,8 +36,8 @@ eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
 set wrapper 0
 if {[eval exec grep "cvw_t" {$outputDir/hdl/$::env(DESIGN).sv}] ne ""} {
     set wrapper 1
-	exec python3 $::env(WALLY)/synthDC/scripts/wrapperGen.py $::env(DESIGN)
-    eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/}
+    # make the wrapper
+	exec python3 $::env(WALLY)/synthDC/scripts/wrapperGen.py $::env(DESIGN) $outputDir/hdl
 }
 
 # Only for FMA class project; comment out when done
@@ -107,6 +109,7 @@ if { $saifpower == 1 } {
 if {$drive != "INV"} {
     set_false_path -from [get_ports reset]
 }
+# for PPA multiplexer synthesis
 if {(($::env(DESIGN) == "ppa_mux2d_1") || ($::env(DESIGN) == "ppa_mux4d_1") || ($::env(DESIGN) == "ppa_mux8d_1"))} {
     set_false_path -from {s}
 }
@@ -124,12 +127,13 @@ if {  $find_clock != [list] } {
     set my_clk $my_clock_pin
     create_clock -period $my_period $my_clk
     set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
-} else {
+ } else {
     echo "Did not find clock! Design is probably combinational!"
     set my_clk vclk
     create_clock -period $my_period -name $my_clk
 }
 
+
 # Optimize paths that are close to critical
 set_critical_range 0.05 $current_design
 
@@ -253,6 +257,19 @@ set write_hier 1        ;# generate hierarchy report
 if { $wrapper == 1 } {
     set designname [format "%s%s" $my_design "__*"]
     current_design $designname
+
+    # recreate clock below wrapper level or reporting doesn't work properly
+    set find_clock [ find port [list $my_clock_pin] ]
+    if {  $find_clock != [list] } {
+        echo "Found clock!"
+        set my_clk $my_clock_pin
+        create_clock -period $my_period $my_clk
+        set_clock_uncertainty $my_uncertainty [get_clocks $my_clk]
+    } else {
+        echo "Did not find clock! Design is probably combinational!"
+        set my_clk vclk
+        create_clock -period $my_period -name $my_clk
+    }
 } 
 
 # Report Constraint Violators

synthDC/scripts/wrapperGen.py

@@ -15,6 +15,7 @@ import os
 parser = argparse.ArgumentParser()
 
 parser.add_argument("DESIGN")
+parser.add_argument("HDLPATH");
 
 args=parser.parse_args()
 
@@ -60,11 +61,7 @@ for l in lines:
 buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
 
 # path to wrapper
-wrapperPath = f"{os.getenv('WALLY')}/synthDC/wrappers/{moduleName}wrapper.sv"
-
-# clear wrappers directory 
-os.system(f"rm -f {os.getenv('WALLY')}/synthDC/wrappers/*")
-os.system(f"mkdir -p {os.getenv('WALLY')}/synthDC/wrappers")
+wrapperPath = f"{args.HDLPATH}/{moduleName}wrapper.sv"
 
 fout = open(wrapperPath, "w")
 
@@ -73,6 +70,4 @@ fout.write(buf)
 fin.close()
 fout.close()
 
-
-
 #print(buf)

synthDC/wallySynth.py

@@ -16,7 +16,7 @@ def mask(command):
 
 if __name__ == '__main__':
     
-    techs = ['sky90', 'tsmc28', 'tsmc28psyn']
+    techs = ['sky130', 'sky90', 'tsmc28', 'tsmc28psyn']
     allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i']
     freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20]
 #    freqVaryPct = [-20, -10, 0, 10, 20]

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output

@@ -55,7 +55,7 @@ FFFFFFFF # stimecmp readback
 8000000b # mcause value from m ext interrupt
 00000000 # mtval for mext interrupt (0x0)
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
-0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
+0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) # skipping instruction address fault since they're impossible with compressed instrs enabled
 00000001 # mcause from an instruction access fault
 00000000 # mtval of faulting instruction address (0x0)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output

@@ -48,7 +48,7 @@
 00000009 # scause from S mode ecall
 00000000 # stval of ecall (*** defined to be zero for now)
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
-0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
+0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
 0000000b # scause from M mode ecall
 00000000 # stval of ecall (*** defined to be zero for now)

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output

@@ -45,7 +45,7 @@
 00000008 # scause from U mode ecall
 00000000 # stval of ecall (*** defined to be zero for now)
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
-0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
+0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
 0000000b # scause from M mode ecall 
 00000000 # stval of ecall (*** defined to be zero for now)

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output

@@ -113,7 +113,7 @@ FFFFFFFF # stimecmp low bits
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
+0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
 00000000
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
 00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output

@@ -98,7 +98,7 @@
 00000000
 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
-0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
+0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
 00000000
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
 00000000

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output

@@ -92,7 +92,7 @@
 00000000
 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
 00000000
-0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable)
+0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable)
 00000000
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
 00000000