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Merge pull request #576 from ross144/main
Fixes some but not all of the Issue #405 bugs. Fixes non-cached atomics, zifence when there is no dcache, and more serious bug with compressedF not supressed on the last cycle of a bus fetch.
This commit is contained in:
David Harris
GitHub
commit
0c331e7828
6 changed files with 46 additions and 30 deletions
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@ -29,7 +29,7 @@
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module ahbinterface #(
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parameter XLEN,
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parameter LSU = 0 // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
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parameter logic LSU = 1'b0 // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
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)(
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input logic HCLK, HRESETn,
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// bus interface
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@ -44,6 +44,7 @@ module ahbinterface #(
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input logic Stall, // Core pipeline is stalled
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input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
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input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write
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input logic BusAtomic, // Uncache atomic memory operation
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input logic [XLEN/8-1:0] ByteMask, // Bytes enables within a word
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input logic [XLEN-1:0] WriteData, // IEU write data for a store
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output logic BusStall, // Bus is busy with an in flight memory operation
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@ -64,7 +65,7 @@ module ahbinterface #(
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assign HWSTRB = '0;
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end
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busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
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busfsm #(~LSU) busfsm(.HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic,
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.BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY,
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.HTRANS, .HWRITE);
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@ -66,7 +66,7 @@ module buscachefsm #(
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output logic [2:0] HBURST // AHB burst length
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);
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typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, ATOMIC_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype;
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typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, ATOMIC_READ_DATA_PHASE, ATOMIC_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype;
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typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
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busstatetype CurrState, NextState;
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@ -87,13 +87,15 @@ module buscachefsm #(
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always_comb begin
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case(CurrState)
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ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE;
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else if (HREADY & BusWrite) NextState = CACHE_WRITEBACK;
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else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH;
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else NextState = ADR_PHASE;
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DATA_PHASE: if(HREADY & BusAtomic) NextState = ATOMIC_PHASE;
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else if(HREADY & ~BusAtomic) NextState = MEM3;
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ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE;
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else if (HREADY & BusWrite) NextState = CACHE_WRITEBACK;
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else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH;
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else NextState = ADR_PHASE;
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DATA_PHASE: if(HREADY & BusAtomic) NextState = ATOMIC_READ_DATA_PHASE;
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else if(HREADY & ~BusAtomic) NextState = MEM3;
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else NextState = DATA_PHASE;
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ATOMIC_READ_DATA_PHASE: if(HREADY) NextState = ATOMIC_PHASE;
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else NextState = ATOMIC_READ_DATA_PHASE;
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ATOMIC_PHASE: if(HREADY) NextState = MEM3;
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else NextState = ATOMIC_PHASE;
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MEM3: if(Stall) NextState = MEM3;
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@ -107,7 +109,7 @@ module buscachefsm #(
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else if(HREADY & FinalBeatCount & BusCMOZero) NextState = MEM3;
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else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE;
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else NextState = CACHE_WRITEBACK;
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default: NextState = ADR_PHASE;
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default: NextState = ADR_PHASE;
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endcase
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end
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@ -129,6 +131,7 @@ module buscachefsm #(
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//(CurrState == DATA_PHASE & ~BusRW[0]) | // *** replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem.
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(CurrState == DATA_PHASE) |
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(CurrState == ATOMIC_PHASE) |
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(CurrState == ATOMIC_READ_DATA_PHASE) |
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(CurrState == CACHE_FETCH & ~FinalBeatCount) |
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(CurrState == CACHE_WRITEBACK & ~FinalBeatCount);
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@ -136,11 +139,11 @@ module buscachefsm #(
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// AHB bus interface
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW) | BusCMOZero) & ~Flush) |
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(CurrState == DATA_PHASE & BusAtomic) |
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(CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) |
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(CacheAccess & FinalBeatCount & |CacheBusRW & HREADY & ~Flush) ? AHB_NONSEQ : // if we have a pipelined request
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(CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE;
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assign HWRITE = ((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == DATA_PHASE & BusAtomic) |
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assign HWRITE = ((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) |
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(CurrState == CACHE_WRITEBACK & |BeatCount);
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assign HBURST = `BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0;
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@ -159,6 +162,7 @@ module buscachefsm #(
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assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | BusWrite)) |
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(CurrState == DATA_PHASE & BusRW[0]) |
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(CurrState == ATOMIC_PHASE & BusRW[0]) |
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(CurrState == ATOMIC_READ_DATA_PHASE & BusRW[0]) |
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(CurrState == CACHE_WRITEBACK) |
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(CurrState == CACHE_FETCH);
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@ -28,7 +28,9 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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// HCLK and clk must be the same clock!
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module busfsm (
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module busfsm #(
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parameter logic READ_ONLY
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)(
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input logic HCLK,
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input logic HRESETn,
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@ -36,6 +38,7 @@ module busfsm (
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input logic Stall, // Core pipeline is stalled
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input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting
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input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write
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input logic BusAtomic, // Uncache atomic memory operation
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output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA
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output logic BusStall, // Bus is busy with an in flight memory operation
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output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
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@ -45,7 +48,7 @@ module busfsm (
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output logic HWRITE // AHB 0: Read operation 1: Write operation
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);
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typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3} busstatetype;
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typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, ATOMIC_READ_DATA_PHASE, ATOMIC_PHASE} busstatetype;
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typedef enum logic [1:0] {AHB_IDLE = 2'b00, AHB_BUSY = 2'b01, AHB_NONSEQ = 2'b10, AHB_SEQ = 2'b11} ahbtranstype;
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busstatetype CurrState, NextState;
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@ -56,24 +59,33 @@ module busfsm (
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always_comb begin
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case(CurrState)
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ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE;
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else NextState = ADR_PHASE;
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DATA_PHASE: if(HREADY) NextState = MEM3;
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else NextState = DATA_PHASE;
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MEM3: if(Stall) NextState = MEM3;
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else NextState = ADR_PHASE;
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default: NextState = ADR_PHASE;
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ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE;
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else NextState = ADR_PHASE;
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DATA_PHASE: if(HREADY & BusAtomic) NextState = ATOMIC_READ_DATA_PHASE;
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else if(HREADY & ~BusAtomic) NextState = MEM3;
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else NextState = DATA_PHASE;
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ATOMIC_READ_DATA_PHASE: if(HREADY) NextState = ATOMIC_PHASE;
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else NextState = ATOMIC_READ_DATA_PHASE;
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ATOMIC_PHASE: if(HREADY) NextState = MEM3;
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else NextState = ATOMIC_PHASE;
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MEM3: if(Stall) NextState = MEM3;
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else NextState = ADR_PHASE;
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default: NextState = ADR_PHASE;
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endcase
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end
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assign BusStall = (CurrState == ADR_PHASE & |BusRW) |
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// (CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid.
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(CurrState == ATOMIC_PHASE) |
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(CurrState == ATOMIC_READ_DATA_PHASE) |
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(CurrState == DATA_PHASE);
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assign BusCommitted = CurrState != ADR_PHASE;
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assign BusCommitted = (CurrState != ADR_PHASE) & ~(READ_ONLY & CurrState == MEM3);
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) |
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(CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) ? AHB_NONSEQ : AHB_IDLE;
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assign HWRITE = (BusRW[0] & ~BusAtomic) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic);
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assign HTRANS = (CurrState == ADR_PHASE & HREADY & |BusRW & ~Flush) ? AHB_NONSEQ : AHB_IDLE;
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assign HWRITE = BusRW[0];
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assign CaptureEn = CurrState == DATA_PHASE;
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endmodule
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@ -370,7 +370,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
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// Fences
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// Ordinary fence is presently a nop
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// fence.i flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented
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if (P.ZIFENCEI_SUPPORTED & P.ICACHE_SUPPORTED) begin:fencei
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if (P.ZIFENCEI_SUPPORTED & (P.ICACHE_SUPPORTED | P.DCACHE_SUPPORTED)) begin:fencei
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logic FenceID;
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assign FenceID = FenceXD & (Funct3D == 3'b001); // is it a FENCE.I instruction?
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assign InvalidateICacheD = FenceID;
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@ -273,9 +273,9 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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assign BusRW = ~ITLBMissF & ~SelIROM ? IFURWF : '0;
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assign IFUHSIZE = 3'b010;
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ahbinterface #(P.XLEN, 0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY),
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ahbinterface #(P.XLEN, 1'b0) ahbinterface(.HCLK(clk), .Flush(FlushD), .HRESETn(~reset), .HREADY(IFUHREADY),
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.HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(),
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.HWSTRB(), .BusRW, .ByteMask(), .WriteData('0),
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.HWSTRB(), .BusRW, .BusAtomic('0), .ByteMask(), .WriteData('0),
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.Stall(GatedStallD), .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer));
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assign CacheCommittedF = '0;
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@ -342,7 +342,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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assign DCacheStallM = CacheStall & ~IgnoreRequestTLB;
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assign CacheBusRW = CacheBusRWTemp;
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// *** add support for cboz
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ahbcacheinterface #(.AHBW(P.AHBW), .LLEN(P.LLEN), .PA_BITS(P.PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
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.HCLK(clk), .HRESETn(~reset), .Flush(FlushW | IgnoreRequestTLB),
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.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
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@ -368,9 +367,9 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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assign LSUHADDR = PAdrM;
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assign LSUHSIZE = LSUFunct3M;
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ahbinterface #(P.XLEN, 1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
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ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(FlushW), .HREADY(LSUHREADY),
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.HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA),
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.HWSTRB(LSUHWSTRB), .BusRW, .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
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.HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM), .WriteData(LSUWriteDataM[P.XLEN-1:0]),
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.Stall(GatedStallW), .BusStall, .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer));
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// Mux between the 2 sources of read data, 0: Bus, 1: DTIM
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