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https://github.com/openhwgroup/cvw.git
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Merge branch 'main' of https://github.com/openhwgroup/cvw
Plus major cleanup of wally-batch.do
This commit is contained in:
Rose Thompson
commit
0d008c9281
5 changed files with 38 additions and 33 deletions
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@ -28,14 +28,14 @@ vlib wkdir/work_${1}_${2}
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# Create directory for coverage data
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mkdir -p cov
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# Need to be able to pass arguments to vopt. Unforunately argv does not work because
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# it takes on different values if vsim and the do file are called from the command line or
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# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n
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# variables and compacts into a single list for passing to vopt.
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set coverage 0
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set CoverageVoptArg ""
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set CoverageVsimArg ""
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# Need to be able to pass arguments to vopt. Unforunately argv does not work because
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# it takes on different values if vsim and the do file are called from the command line or
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# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n
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# variables and compacts into a single list for passing to vopt.
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set configOptions ""
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set from 4
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set step 1
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@ -67,17 +67,12 @@ if {$argc >= 3} {
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# do wally-pipelined-batch.do ../config/rv32imc rv32imc
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vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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if {$coverage} {
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# vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbectf
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puts "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt ${CoverageVoptArg}
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vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 ${CoverageVsimArg}
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} else {
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt
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vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
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}
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vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg}
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vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 ${CoverageVsimArg}
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# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
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# power add generates the logging necessary for said generation.
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# power add -r /dut/core/*
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@ -86,7 +81,6 @@ run -all
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if {$coverage} {
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puts "???????????????????????????"
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echo "Saving coverage to ${1}_${2}.ucdb"
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do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration
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coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb
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@ -237,11 +237,10 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
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5'b00010: ControlsD = `FCTRLW'b0_1_01_00_011_0_0_1_0; // fcvt.l.q q->l
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5'b00011: ControlsD = `FCTRLW'b0_1_01_00_010_0_0_1_0; // fcvt.lu.q q->lu
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endcase
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// coverage on
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// coverage off
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// Not covered in testing because rv64gc is not RV64Q or RV32D
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7'b1011001: if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct3D == 3'b000)
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ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.d.x (Zfa) *** untested, controls could be wrong
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// Not covered in testing because rv64gc does not support quad precision
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// coverage off
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7'b1011011: if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct3D == 3'b000)
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ControlsD = `FCTRLW'b1_0_01_00_101_0_0_0_0; // fmvp.q.x (Zfa)
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// coverage on
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@ -320,7 +320,7 @@ module testbench;
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if (TEST == "coremark")
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if (dut.core.priv.priv.EcallFaultM) begin
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$display("Benchmark: coremark is done.");
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$finish;
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$stop;
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end
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if(Validate) begin
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if (TEST == "embench") begin
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@ -357,7 +357,7 @@ module testbench;
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if (test == tests.size()) begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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$finish;
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$stop; // if this is changed to $finish, wally-batch.do does not go to the next step to run coverage
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end
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end
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end
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@ -798,7 +798,7 @@ end
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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$finish;
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$stop; // if this is changed to $finish, wally-batch.do does not get to the next step to run coverage
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end
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end
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if (errors) $display("%s failed with %d errors. :(", TestName, errors);
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@ -1134,10 +1134,10 @@ string imperas32f[] = '{
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string arch64zfh_fma[] = '{
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`RISCVARCHTEST,
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//"rv64i_m/F/src/fmadd_b15-01.S",
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"rv64i_m/Zfh/src/fmsub_b15-01.S"
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// "rv64i_m/F/src/fnmadd_b15-01.S",
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// "rv64i_m/F/src/fnmsub_b15-01.S"
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"rv64i_m/Zfh/src/fmadd_b15-01.S",
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"rv64i_m/Zfh/src/fmsub_b15-01.S",
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"rv64i_m/Zfh/src/fnmadd_b15-01.S",
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"rv64i_m/Zfh/src/fnmsub_b15-01.S"
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};
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string arch64f_divsqrt[] = '{
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@ -2178,10 +2178,10 @@ string arch64zbs[] = '{
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string arch32zfh_fma[] = '{
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`RISCVARCHTEST,
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//"rv32i_m/D/src/fmadd.d_b15-01.S",
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//"rv32i_m/D/src/fmsub.d_b15-01.S",
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// "rv32i_m/D/src/fnmadd.d_b15-01.S",
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"rv32i_m/Zfh/src/fnmsub.d_b15-01.S"
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"rv32i_m/Zfh/src/fmadd_b15-01.S",
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"rv32i_m/Zfh/src/fmsub_b15-01.S",
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"rv32i_m/Zfh/src/fnmadd_b15-01.S",
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"rv32i_m/Zfh/src/fnmsub_b15-01.S"
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};
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string arch32d_divsqrt[] = '{
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@ -40,12 +40,24 @@ main:
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# zfa instructions (because Zfa tests aren't running yet)
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fli.d fs0, 16
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fcvtmod.w.d t0, fs0, rtz
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fminm.d fs1, fs0, fs0
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fmaxm.d fs1, fs0, fs0
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fround.d fs1, fs0
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# fminm.d fs1, fs0, fs0
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# fmaxm.d fs1, fs0, fs0
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# fltq.d t0, fs1, ft0
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# fleq.d t0, fs1, ft0
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fcvt.d.q fs1, fs0
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fcvt.h.q fs1, fs0
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fcvt.s.q fs1, fs0
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# round for now because these tests are excluded from Zfa until rounding is implemented
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fround.s fs1, fs0
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froundnx.s fs1, fs0
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fround.d fs1, fs0
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froundnx.d fs1, fs0
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fltq.d t0, fs1, ft0
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fleq.d t0, fs1, ft0
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fround.h fs1, fs0
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froundnx.h fs1, fs0
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fround.s fs1, fs0
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froundnx.s fs1, fs0
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fmvp.d.x
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#Result Sign Test Coverage
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la t0, TestData2
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