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Merged ross's spacing fixes

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This commit is contained in:
David Harris 2023-03-24 15:47:26 -07:00
commit 0dc6f9b991
82 changed files with 1786 additions and 1822 deletions
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8
src/cache/cacheway.sv vendored
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@ -86,8 +86,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
assign SelNonHit = FlushWayEn | SetValid | SelWriteback;
mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
//assign SelTag = VictimWay | FlushWay;
//assign SelData = HitWay | FlushWayEn | VictimWayEn;
mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData);
@ -95,10 +93,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
// Write Enable demux
/////////////////////////////////////////////////////////////////////////////////////////////
// RT: Can we merge these two muxes? This is also shared in cacheLRU.
//mux3 #(1) selectwaymux(HitWay, VictimWay, FlushWay, {SelFlush, SetValid}, SelData);
//mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelNonHit}, SelData);
assign SetValidWay = SetValid & SelData;
assign ClearValidWay = ClearValid & SelData;
assign SetDirtyWay = SetDirty & SelData;
@ -117,8 +111,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
.addr(CacheSet), .dout(ReadTag), .bwe('1),
.din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
// AND portion of distributed tag multiplexer
assign TagWay = SelTag ? ReadTag : '0; // AND part of AOMux
assign DirtyWay = SelTag & Dirty & ValidWay;

2
src/ebu/ahbinterface.sv
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@ -53,7 +53,6 @@ module ahbinterface #(
);
logic CaptureEn;
localparam LEN = (LSU ? `XLEN : 32); // 32 bits for IFU, XLEN for LSU
flopen #(LEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA[LEN-1:0]), .q(FetchBuffer));
@ -70,4 +69,5 @@ module ahbinterface #(
busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
.BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY,
.HTRANS, .HWRITE);
endmodule

3
src/ebu/ebu.sv
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@ -66,7 +66,6 @@ module ebu (
output logic HMASTLOCK // AHB master lock. Wally does not use
);
logic LSUDisable;
logic LSUSelect;
logic IFUSave;
@ -89,8 +88,6 @@ module ebu (
logic IFUReq;
logic LSUReq;
assign HCLK = clk;
assign HRESETn = ~reset;

34
src/ebu/ebufsmarb.sv
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@ -41,7 +41,6 @@ module ebufsmarb (
input logic LSUReq,
input logic IFUReq,
output logic IFUSave,
output logic IFURestore,
output logic IFUDisable,
@ -57,7 +56,7 @@ module ebufsmarb (
logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst
logic BeatCntEn;
logic [3:0] BeatCount; // Position within a burst transfer
logic CntReset;
logic BeatCntReset;
logic [3:0] Threshold; // Number of beats derived from HBURST
////////////////////////////////////////////////////////////////////////////////////////////////////
@ -98,29 +97,26 @@ module ebufsmarb (
// Burst mode logic
////////////////////////////////////////////////////////////////////////////////////////////////////
assign CntReset = NextState == IDLE;
assign BeatCntReset = NextState == IDLE;
assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access.
// Counting the beats in the EBU is only necessary when both the LSU and IFU request concurrently.
// LSU has priority. HREADY serves double duty during a burst transaction. It indicates when the
// beat completes and when the transaction finishes. However there is nothing external to
// differentiate them. The EBU counts the HREADY beats so it knows when to switch to the IFU's
// request.
assign BeatCntEn = (NextState == ARBITRATE) & HREADY;
counter #(4) BeatCounter(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, BeatCount);
counter #(4) BeatCounter(HCLK, ~HRESETn | BeatCntReset | FinalBeat, BeatCntEn, BeatCount);
// Used to store data from data phase of AHB.
flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | CntReset, BeatCntEn, FinalBeat, FinalBeatD);
flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, FinalBeat, FinalBeatD);
// unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST.
// HBURST[2:1] Beats
// 00 1
// 01 4
// 10 8
// 11 16
// unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST, Threshold = num beats - 1.
// HBURST[2:1] Beats threshold
// 00 1 0
// 01 4 3
// 10 8 7
// 11 16 15
always_comb
if (HBURST[2:1] == 2'b00) Threshold = 4'b0000;
else Threshold = (2 << HBURST[2:1]) - 1;
/* case(HBURST)
0: Threshold = 4'b0000;
3: Threshold = 4'b0011; // INCR4
5: Threshold = 4'b0111; // INCR8
7: Threshold = 4'b1111; // INCR16
default: Threshold = 4'b0000; // INCR without end.
endcase
end */
endmodule

2
src/fpu/fdivsqrt/fdivsqrtstage4.sv
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@ -31,7 +31,7 @@
module fdivsqrtstage4 (
input logic [`DIVb-1:0] D,
input logic [`DIVb+3:0] DBar, D2, DBar2,
input logic [`DIVb:0] U, UM,
input logic [`DIVb:0] U,UM,
input logic [`DIVb+3:0] WS, WC,
input logic [`DIVb+1:0] C,
input logic SqrtE, j1,

1
src/generic/mem/ram1p1rwbe.sv
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@ -94,7 +94,6 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
always_ff @(posedge clk)
if(ce) dout <= #1 mem[addr]; */
// Write divided into part for bytes and part for extra msbs
// Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
// Therefore these always blocks use the older always @(posedge clk)

4
src/generic/mem/ram2p1r1wbe.sv
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@ -85,7 +85,6 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
logic [SRAMWIDTH-1:0] SRAMBitMask;
logic [$clog2(DEPTH)-1:0] RA1Q;
onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre);
genvar index;
for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux
@ -118,7 +117,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d);
assign rd1 = mem[ra1d];
/* // Read
/* // Read
always_ff @(posedge clk)
if(ce1) rd1 <= #1 mem[ra1]; */
@ -133,7 +132,6 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
always @(posedge clk)
if (ce2 & we2 & bwe2[WIDTH/8])
mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
end
endmodule

2
src/generic/mem/rom1p1r_128x64.sv
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@ -32,7 +32,7 @@ module rom1p1r_128x64(
);
// replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor
ts3n28hpcpa128x64m8m romIP (.CLK, .CEB, .A, .Q);
ts3n28hpcpa128x64m8m romIP (.CLK, .CEB, .A, .Q);
// generic64x128ROM romIP (.CLK, .CEB, .A, .Q);
endmodule

11
src/ieu/alu.sv
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@ -52,19 +52,12 @@ module alu #(parameter WIDTH=32) (
logic LT, LTU; // Less than, Less than unsigned
logic Asign, Bsign; // Sign bits of A, B
// *** explain this part better; possibly move into shifter and BMU?
if (WIDTH == 64) begin
mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, CondExtA); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
end else begin
assign CondExtA = A;
end
// Addition
assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB;
assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith};
// Shifts (configurable for rotation)
shifter sh(.A(CondExtA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
// Condition code flags are based on subtraction output Sum = A-B.
// Overflow occurs when the numbers being subtracted have the opposite sign
@ -97,7 +90,7 @@ module alu #(parameter WIDTH=32) (
// Final Result B instruction select mux
if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu
bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect,
.Funct3, .CompFlags, .BALUControl, .CondExtA, .ALUResult, .FullResult,
.Funct3, .CompFlags, .BALUControl, .ALUResult, .FullResult,
.CondMaskB, .CondShiftA, .Result);
end else begin
assign Result = ALUResult;

7
src/ieu/bmu/bitmanipalu.sv
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@ -37,7 +37,6 @@ module bitmanipalu #(parameter WIDTH=32) (
input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform
input logic [1:0] CompFlags, // Comparator flags
input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
input logic [WIDTH-1:0] CondExtA, // A Conditional Extend Intermediary Signal
input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals
output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions
output logic [WIDTH-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions
@ -50,6 +49,7 @@ module bitmanipalu #(parameter WIDTH=32) (
logic Mask; // Indicates if it is ZBS instruction
logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction
logic [1:0] PreShiftAmt; // Amount to Pre-Shift A
logic [WIDTH-1:0] CondZextA; // A Conditional Extend Intermediary Signal
// Extract control signals from bitmanip ALUControl.
assign {Mask, PreShift} = BALUControl[1:0];
@ -62,8 +62,11 @@ module bitmanipalu #(parameter WIDTH=32) (
// 0-3 bit Pre-Shift Mux
if (`ZBA_SUPPORTED) begin: zbapreshift
if (WIDTH == 64) begin
mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, W64, CondZextA);
end else assign CondZextA = A;
assign PreShiftAmt = Funct3[2:1] & {2{PreShift}};
assign CondShiftA = CondExtA << (PreShiftAmt);
assign CondShiftA = CondZextA << (PreShiftAmt);
end else begin
assign PreShiftAmt = 2'b0;
assign CondShiftA = A;

41
src/ieu/shifter.sv
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@ -40,42 +40,41 @@ module shifter (
logic Sign; // Sign bit for sign extension
assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension
if (`ZBB_SUPPORTED) begin: rotfunnel
if (`XLEN==32) begin // rv32 with rotates
if (`XLEN==32) begin // rv32
if (`ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
always_comb // funnel mux
case({Right, Rotate})
2'b00: Z = {A[31:0], 31'b0};
2'b01: Z = {A[31:0], A[31:1]};
2'b10: Z = {{31{Sign}}, A[31:0]};
2'b11: Z = {A[30:0], A};
2'b11: Z = {A[30:0], A[31:0]};
endcase
end else begin: norotfunnel32 //rv32 shifter without rotates
always_comb // funnel mux
if (Right) Z = {{31{Sign}}, A[31:0]};
else Z = {A[31:0], 31'b0};
end
assign TruncAmt = Amt; // shift amount
end else begin // rv64 with rotates
end else begin // rv64
logic [`XLEN-1:0] A64;
mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, A64); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
if (`ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
// shifter rotate source select mux
logic [`XLEN-1:0] RotA; // rotate source
mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons
always_comb // funnel mux
case ({Right, Rotate})
2'b00: Z = {A[63:0],{63'b0}};
2'b01: Z = {RotA, RotA[63:1]};
2'b10: Z = {{63{Sign}}, A[63:0]};
2'b11: Z = {RotA[62:0], RotA};
2'b00: Z = {A64[63:0],{63'b0}};
2'b01: Z = {RotA[63:0], RotA[63:1]};
2'b10: Z = {{63{Sign}}, A64[63:0]};
2'b11: Z = {RotA[62:0], RotA[63:0]};
endcase
assign TruncAmt = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
end
end else begin: norotfunnel
if (`XLEN==32) begin:shifter // RV32
end else begin: norotfunnel64 // rv64 shifter without rotates
always_comb // funnel mux
if (Right) Z = {{31{Sign}}, A[31:0]};
else Z = {A[31:0], 31'b0};
assign TruncAmt = Amt; // shift amount
end else begin:shifter // RV64
always_comb // funnel mux
if (Right) Z = {{63{Sign}}, A[63:0]};
else Z = {A[63:0], {63'b0}};
assign TruncAmt = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
if (Right) Z = {{63{Sign}}, A64[63:0]};
else Z = {A64[63:0], {63'b0}};
end
assign TruncAmt = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift
end
// Opposite offset for right shifts

2
src/ifu/bpred/bpred.sv
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@ -97,8 +97,6 @@ module bpred (
logic BPReturnWrongD;
logic [`XLEN-1:0] BPBTAE;
// Part 1 branch direction prediction
// look into the 2 port Sram model. something is wrong.
if (`BPRED_TYPE == "BP_TWOBIT") begin:Predictor

1
src/ifu/bpred/btb.sv
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@ -111,5 +111,4 @@ module btb #(parameter Depth = 10 ) (
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
flopenr #(`XLEN) IEUAdrWReg(clk, reset, ~StallW, IEUAdrM, IEUAdrW);
endmodule

3
src/ifu/spill.sv
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@ -51,8 +51,9 @@ module spill #(
// Spill threshold occurs when all the cache offset PC bits are 1 (except [0]). Without a cache this is just PCF[1]
typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
statetype CurrState, NextState;
localparam SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1;
statetype CurrState, NextState;
logic [`XLEN-1:0] PCPlus2F;
logic TakeSpillF;
logic SpillF;

2
src/lsu/subwordread.sv
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@ -88,7 +88,7 @@ module subwordread
3'b010: ReadDataM = {{`LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw
3'b011: ReadDataM = {{`LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld
3'b100: ReadDataM = {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu
// 3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128
//3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{`LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128
3'b101: ReadDataM = {{`LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
3'b110: ReadDataM = {{`LLEN-32{1'b0}}, WordM[31:0]}; // lwu
default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen

2
src/mdu/div.sv
View file

@ -36,7 +36,7 @@ module div(
input logic IntDivE, // integer division/remainder instruction of any type
input logic DivSignedE, // signed division
input logic W64E, // W-type instructions (divw, divuw, remw, remuw)
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Forwarding mux outputs for Source A and B
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE,// Forwarding mux outputs for Source A and B
output logic DivBusyE, // Divide is busy - stall pipeline
output logic [`XLEN-1:0] QuotM, RemM // Quotient and remainder outputs
);

1
src/uncore/ram_ahb.sv
View file

@ -109,6 +109,5 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
assign DelayReady = 0;
end
endmodule

16
src/wally/wallypipelinedcore.sv
View file

@ -247,20 +247,10 @@ module wallypipelinedcore (
ebu ebu(// IFU connections
.clk, .reset,
// IFU interface
.IFUHADDR,
.IFUHBURST,
.IFUHTRANS,
.IFUHREADY,
.IFUHSIZE,
.IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHSIZE,
// LSU interface
.LSUHADDR,
.LSUHWDATA,
.LSUHWSTRB,
.LSUHSIZE,
.LSUHBURST,
.LSUHTRANS,
.LSUHWRITE,
.LSUHREADY,
.LSUHADDR, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST,
.LSUHTRANS, .LSUHWRITE, .LSUHREADY,
// BUS interface
.HREADY, .HRESP, .HCLK, .HRESETn,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,

2
src/wally/wallypipelinedsoc.sv
View file

@ -66,7 +66,7 @@ module wallypipelinedsoc (
// Uncore signals
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
logic HRESP; // response from AHB
logic MTimerInt, MSwInt; // timer and software interrupts from CLINT
logic MTimerInt, MSwInt;// timer and software interrupts from CLINT
logic [63:0] MTIME_CLINT; // from CLINT to CSRs
logic MExtInt,SExtInt; // from PLIC