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Parallel FSR's and F CTRL logic
This commit is contained in:
Brett Mathis
parent
088fbbcbf0
commit
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5 changed files with 839 additions and 0 deletions
89
wally-pipelined/config/rv64icfd/wally-config.vh
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89
wally-pipelined/config/rv64icfd/wally-config.vh
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//////////////////////////////////////////
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// wally-config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified: Brett Mathis
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 64
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//`define MISA (32'h00000104)
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`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20)
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
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`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
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`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
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`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
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`define ZCSR_SUPPORTED 1
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`define ZCOUNTERS_SUPPORTED 1
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// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
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//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
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`define N_SUPPORTED 0
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`define M_MODE (2'b11)
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`define S_MODE (2'b01)
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`define U_MODE (2'b00)
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// Microarchitectural Features
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DCACHE 0
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`define MEM_DTIM 1
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`define MEM_ICACHE 0
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`define MEM_VIRTMEM 0
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// Address space
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`define RESET_VECTOR 64'h0000000080000000
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// Bus Interface width
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`define AHBW 64
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define TIMBASE 32'h80000000
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`define TIMRANGE 32'h0007FFFF
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`define CLINTBASE 32'h02000000
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`define CLINTRANGE 32'h0000FFFF
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`define GPIOBASE 32'h10012000
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`define GPIORANGE 32'h000000FF
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`define UARTBASE 32'h10000000
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`define UARTRANGE 32'h00000007
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// Test modes
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 0
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// Hardware configuration
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`define UART_PRESCALE 1
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/* verilator lint_off STMTDLY */
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/* verilator lint_off WIDTH */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off PINCONNECTEMPTY */
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29
wally-pipelined/src/fpu/build_temp/fcsr.sv
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29
wally-pipelined/src/fpu/build_temp/fcsr.sv
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@ -0,0 +1,29 @@
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`include "../../config/rv64icfd/wally-config.vh"
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module fcsr(
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input logic [2:0] frm,
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input logic reset,
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input logic clear,
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input logic clk,
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input logic write,
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input logic [4:0] flags,
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output logic [31:0] readData);
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//register I/O assignment
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logic [31:0] regInput;
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logic [31:0] regOutput;
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//no L instruction support
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//only last 8 bits used for FCSR
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//latching input to write signal
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//AND clk and write and remove latch
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//for clk-based write
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assign regInput = (write) ? {24'h0,frm,flags} : regInput;
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floprc #(32) (.clk(clk), .reset(reset), .clear(clear), .d(regInput), .q(regOutput));
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assign readData = regOutput;
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endmodule
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143
wally-pipelined/src/fpu/build_temp/fctrl.sv
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143
wally-pipelined/src/fpu/build_temp/fctrl.sv
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@ -0,0 +1,143 @@
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`include "../../config/rv64icfd/wally-config.vh"
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module fctrl (
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input logic [6:0] Funct7D,
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input logic [6:0] OpD,
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input logic [4:0] Rs2D,
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input logic [4:0] Rs1D,
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input logic [2:0] FrmW,
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output logic WriteEnD,
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output logic DivSqrtStartD,
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output logic [2:0] regSelD,
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output logic [2:0] writeSelD,
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output logic [3:0] OpCtrlD,
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output logic FmtD,
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output logic WriteIntD);
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//precision is taken directly from instruction
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assign FmtD = Funct7D[0];
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//all subsequent logic is based on the table present
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//in Section 5 of Wally Architecture Specification
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//write is enabled for all fp instruciton op codes
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//sans fp load
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logic isFP, isFPLD;
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always_comb begin
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//case statement is easier to modify
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//in case of errors
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case(OpD)
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//fp instructions sans load
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7'b1010011 : begin isFP = 1'b1; isFPLD = 1'b0; end
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7'b1000011 : begin isFP = 1'b1; isFPLD = 1'b0; end
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7'b1000111 : begin isFP = 1'b1; isFPLD = 1'b0; end
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7'b1001011 : begin isFP = 1'b1; isFPLD = 1'b0; end
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7'b1001111 : begin isFP = 1'b1; isFPLD = 1'b0; end
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7'b0100111 : begin isFP = 1'b1; isFPLD = 1'b0; end
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//fp load
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7'b1010011 : begin isFP = 1'b1; isFPLD = 1'b1; end
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default : begin isFP = 1'b0; isFPLD = 1'b0; end
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endcase
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end
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assign WriteEnD = isFP & ~isFPLD;
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//useful intermediary signals
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//
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//(mult only not supported in current datapath)
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//set third FMA operand to zero in this case
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//(or equivalent)
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logic isAddSub, isFMA, isMult, isDivSqrt, isCvt, isCmp, isFPSTR;
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always_comb begin
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//checks all but FMA/store/load
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if(OpD == 7'b1010011) begin
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case(Funct7D)
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//compare
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7'b10100?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b1; isFPSTR = 1'b0; end
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//div/sqrt
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7'b0?011?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b1; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end
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//add/sub
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7'b0000??? : begin isAddSub = 1'b1; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end
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//mult
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7'b00010?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b1; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end
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//convert (not precision)
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7'b110?0?? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b1; isCmp = 1'b0; isFPSTR = 1'b0; end
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//convert (precision)
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7'b010000? : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b1; isCmp = 1'b0; isFPSTR = 1'b0; end
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endcase
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end
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//FMA/store/load
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else begin
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case(OpD)
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//4 FMA instructions
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7'b1000011 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end
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7'b1000111 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end
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7'b1001011 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end
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7'b1001111 : begin isAddSub = 1'b0; isFMA = 1'b1; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b0; end
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//store (load already found)
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7'b0100111 : begin isAddSub = 1'b0; isFMA = 1'b0; isMult = 1'b0; isDivSqrt = 1'b0; isCvt = 1'b0; isCmp = 1'b0; isFPSTR = 1'b1; end
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endcase
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end
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end
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//register is chosen based on operation performed
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//----
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//write selection is chosen in the same way as
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//register selection
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//
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// reg/write sel logic and assignment
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//
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// 3'b000 = add/sub/cvt
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// 3'b001 = sign
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// 3'b010 = fma
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// 3'b011 = cmp
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// 3'b100 = div/sqrt
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//
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//reg select
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//this value is used enough to be shorthand
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logic isSign;
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assign isSign = ~Funct7D[6] & ~Funct7D[5] & Funct7D[4] & ~Funct7D[3] & ~Funct7D[2];
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assign regSelD[2] = isDivSqrt & ~isFMA;
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assign regSelD[1] = isFMA | isCmp;
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//AND of Funct7 for sign
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assign regSelD[0] = isCmp | isSign;
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//write select
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assign writeSelD[2] = isDivSqrt & ~isFMA;
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assign writeSelD[1] = isFMA | isCmp;
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//AND of Funct7 for sign
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assign writeSelD[0] = isCmp | isSign;
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//if op is div/sqrt - start div/sqrt
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assign DivSqrtStartD = isDivSqrt & ~isFMA;
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//operation control for each fp operation
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//has to be expanded over standard to account for
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//integrated fpadd/cvt
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//
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//will integrate FMA opcodes into design later
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//
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//conversion instructions will
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//also need to be added later as I find the opcode
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//version I used for this repo
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assign OpCtrlD[3] = 1'b0;
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//if is positive sign injection OR is precision convert
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assign OpCtrlD[2] = (isSign & ~FrmW[0]) | (~Funct7D[6] & Funct7D[5] & ~Funct7D[4] & ~Funct7D[3] & ~Funct7D[2] & ~Funct7D[1]);
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//if is precision convert OR is sign xor
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assign OpCtrlD[1] = (isSign & FrmW[1]) | (~Funct7D[6] & Funct7D[5] & ~Funct7D[4] & ~Funct7D[3] & ~Funct7D[2] & ~Funct7D[1]);
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//if is sqrt OR is sub OR is single-precision cmp OR negation
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assign OpCtrlD[0] = (isDivSqrt & ~isFMA & Funct7D[6]) | (isAddSub & ~isFMA & Funct7D[2]) | (isCmp & ~isFMA & Funct7D[0]) | (isSign & FrmW[0]);
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//write to integer source if conv to int occurs
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//AND of Funct7 for int results
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assign WriteIntD = isCvt & (Funct7D[6] & Funct7D[5] & ~Funct7D[4] & ~Funct7D[3] & ~Funct7D[2] & ~Funct7D[1]);
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endmodule
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65
wally-pipelined/src/fpu/build_temp/fputop.sv
Normal file
65
wally-pipelined/src/fpu/build_temp/fputop.sv
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@ -0,0 +1,65 @@
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`include "../../config/rv64icfd/wally-config.vh"
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module fputop (
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input logic [2:0] FrmW,
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input logic reset,
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input logic clear,
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input logic clk,
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input logic [31:0] InstrD,
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input logic [`XLEN-1:0] SrcAE,
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input logic [`XLEN-1:0] SrcAW,
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output logic [31:0] FSROutW,
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output logic DivSqrtDoneE,
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output logic FInvalInstrD,
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output logic [`XLEN-1:0] FPUResultW);
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/*fctrl ();
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//regfile instantiation and decode stage
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//write signal mux
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//address signal mux
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//parallel floating-point registers are
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//used for modularity and future performance
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//comparisons between operation sets
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freg1adr ();
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freg2adr ();
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freg2adr ();
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freg2adr ();
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freg3adr ();
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//can easily be merged into privledged core
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//if necessary
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fcsr ();
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//E pipe and execution stage
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fpdivsqrt ();
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fma1 ();
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fpaddcvt1 ();
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fpcmp1 ();
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fpsign ();
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//M pipe and memory stage
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fma2 ();
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fpaddcvt2 ();
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fpcmp2 ();
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//W pipe and writeback stage
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//flag signal mux
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*/
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endmodule
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513
wally-pipelined/src/fpu/build_temp/freg.sv
Normal file
513
wally-pipelined/src/fpu/build_temp/freg.sv
Normal file
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@ -0,0 +1,513 @@
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`include "../../config/rv64icfd/wally-config.vh"
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module freg1adr (
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input logic [2:0] frm,
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input logic reset,
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input logic clear,
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input logic clk,
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input logic [4:0] rd,
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input logic write,
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input logic [4:0] adr1,
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input logic [`XLEN-1:0] writeData,
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output logic [`XLEN-1:0] readData);
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//note - not word aligning based on precision of
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//operation (frm)
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//reg number should remain static, but it doesn't hurt
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//to parameterize
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parameter numRegs = 32;
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//intermediary signals - useful for debugging
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//and easy instatiation of generated modules
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logic [`XLEN-1:0] [numRegs-1:0] regInput;
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logic [`XLEN-1:0] [numRegs-1:0] regOutput;
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//generate fp registers themselves
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genvar i;
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generate
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for (i = 0; i < numRegs; i = i + 1) begin:register
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floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0]));
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end
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endgenerate
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//this could be done with:
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//
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//assign readData = regOutput[adr1];
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//
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//but always_comb allows for finer control
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//address decoder
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//only 1 for this fp register set
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//used with fpsign
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//defaults to outputting zeroes
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always_comb begin
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case(adr1)
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5'b00000 : readData = regOutput[0];
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5'b00001 : readData = regOutput[1];
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5'b00010 : readData = regOutput[2];
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5'b00011 : readData = regOutput[3];
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5'b00100 : readData = regOutput[4];
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5'b00101 : readData = regOutput[5];
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5'b00110 : readData = regOutput[6];
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5'b00111 : readData = regOutput[7];
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5'b01000 : readData = regOutput[8];
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5'b01001 : readData = regOutput[9];
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5'b01010 : readData = regOutput[10];
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5'b01011 : readData = regOutput[11];
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5'b01100 : readData = regOutput[12];
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5'b01101 : readData = regOutput[13];
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5'b01110 : readData = regOutput[14];
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5'b01111 : readData = regOutput[15];
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5'b10000 : readData = regOutput[16];
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5'b10001 : readData = regOutput[17];
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5'b10010 : readData = regOutput[18];
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5'b10011 : readData = regOutput[19];
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5'b10100 : readData = regOutput[20];
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5'b10101 : readData = regOutput[21];
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5'b10110 : readData = regOutput[22];
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5'b10111 : readData = regOutput[23];
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5'b11000 : readData = regOutput[24];
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5'b11001 : readData = regOutput[25];
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5'b11010 : readData = regOutput[26];
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5'b11011 : readData = regOutput[27];
|
||||
5'b11100 : readData = regOutput[28];
|
||||
5'b11101 : readData = regOutput[29];
|
||||
5'b11110 : readData = regOutput[30];
|
||||
5'b11111 : readData = regOutput[31];
|
||||
default : readData = `XLEN'h0;
|
||||
endcase
|
||||
end
|
||||
|
||||
//destination register decoder
|
||||
//only change input values on write
|
||||
//defaults to undefined with invalid address
|
||||
//
|
||||
//note - this is an intermediary signal, so
|
||||
//this is not asynch assignment. FF in flopr
|
||||
//will not update data until clk pulse
|
||||
always_comb begin
|
||||
if(write) begin
|
||||
case(rd)
|
||||
5'b00000 : regInput[0] = writeData;
|
||||
5'b00001 : regInput[1] = writeData;
|
||||
5'b00010 : regInput[2] = writeData;
|
||||
5'b00011 : regInput[3] = writeData;
|
||||
5'b00100 : regInput[4] = writeData;
|
||||
5'b00101 : regInput[5] = writeData;
|
||||
5'b00110 : regInput[6] = writeData;
|
||||
5'b00111 : regInput[7] = writeData;
|
||||
5'b01000 : regInput[8] = writeData;
|
||||
5'b01000 : regInput[9] = writeData;
|
||||
5'b01001 : regInput[10] = writeData;
|
||||
5'b01010 : regInput[11] = writeData;
|
||||
5'b01111 : regInput[12] = writeData;
|
||||
5'b01101 : regInput[13] = writeData;
|
||||
5'b01110 : regInput[14] = writeData;
|
||||
5'b01111 : regInput[15] = writeData;
|
||||
5'b10000 : regInput[16] = writeData;
|
||||
5'b10001 : regInput[17] = writeData;
|
||||
5'b10010 : regInput[18] = writeData;
|
||||
5'b10011 : regInput[19] = writeData;
|
||||
5'b10100 : regInput[20] = writeData;
|
||||
5'b10101 : regInput[21] = writeData;
|
||||
5'b10110 : regInput[22] = writeData;
|
||||
5'b10111 : regInput[23] = writeData;
|
||||
5'b11000 : regInput[24] = writeData;
|
||||
5'b11000 : regInput[25] = writeData;
|
||||
5'b11001 : regInput[26] = writeData;
|
||||
5'b11010 : regInput[27] = writeData;
|
||||
5'b11111 : regInput[28] = writeData;
|
||||
5'b11101 : regInput[29] = writeData;
|
||||
5'b11110 : regInput[30] = writeData;
|
||||
5'b11111 : regInput[31] = writeData;
|
||||
default : regInput[0] = `XLEN'hx;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//********
|
||||
//formatting separation
|
||||
//********
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module freg2adr (
|
||||
input logic [2:0] frm,
|
||||
input logic reset,
|
||||
input logic clear,
|
||||
input logic clk,
|
||||
input logic [4:0] rd,
|
||||
input logic write,
|
||||
input logic [4:0] adr1,
|
||||
input logic [4:0] adr2,
|
||||
input logic [`XLEN-1:0] writeData,
|
||||
output logic [`XLEN-1:0] readData1,
|
||||
output logic [`XLEN-1:0] readData2);
|
||||
|
||||
//note - not word aligning based on precision of
|
||||
//operation (frm)
|
||||
|
||||
//reg number should remain static, but it doesn't hurt
|
||||
//to parameterize
|
||||
parameter numRegs = 32;
|
||||
|
||||
//intermediary signals - useful for debugging
|
||||
//and easy instatiation of generated modules
|
||||
logic [`XLEN-1:0] [numRegs-1:0] regInput;
|
||||
logic [`XLEN-1:0] [numRegs-1:0] regOutput;
|
||||
|
||||
//generate fp registers themselves
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < numRegs; i = i + 1) begin:register
|
||||
|
||||
floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0]));
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
//address decoder
|
||||
//2 are used for this fp register set
|
||||
//used with fpadd/cvt, fpdiv/sqrt, and fpcmp
|
||||
//defaults to outputting zeroes
|
||||
always_comb begin
|
||||
|
||||
//adderss 1 decoder
|
||||
case(adr1)
|
||||
5'b00000 : readData1 = regOutput[0];
|
||||
5'b00001 : readData1 = regOutput[1];
|
||||
5'b00010 : readData1 = regOutput[2];
|
||||
5'b00011 : readData1 = regOutput[3];
|
||||
5'b00100 : readData1 = regOutput[4];
|
||||
5'b00101 : readData1 = regOutput[5];
|
||||
5'b00110 : readData1 = regOutput[6];
|
||||
5'b00111 : readData1 = regOutput[7];
|
||||
5'b01000 : readData1 = regOutput[8];
|
||||
5'b01001 : readData1 = regOutput[9];
|
||||
5'b01010 : readData1 = regOutput[10];
|
||||
5'b01011 : readData1 = regOutput[11];
|
||||
5'b01100 : readData1 = regOutput[12];
|
||||
5'b01101 : readData1 = regOutput[13];
|
||||
5'b01110 : readData1 = regOutput[14];
|
||||
5'b01111 : readData1 = regOutput[15];
|
||||
5'b10000 : readData1 = regOutput[16];
|
||||
5'b10001 : readData1 = regOutput[17];
|
||||
5'b10010 : readData1 = regOutput[18];
|
||||
5'b10011 : readData1 = regOutput[19];
|
||||
5'b10100 : readData1 = regOutput[20];
|
||||
5'b10101 : readData1 = regOutput[21];
|
||||
5'b10110 : readData1 = regOutput[22];
|
||||
5'b10111 : readData1 = regOutput[23];
|
||||
5'b11000 : readData1 = regOutput[24];
|
||||
5'b11001 : readData1 = regOutput[25];
|
||||
5'b11010 : readData1 = regOutput[26];
|
||||
5'b11011 : readData1 = regOutput[27];
|
||||
5'b11100 : readData1 = regOutput[28];
|
||||
5'b11101 : readData1 = regOutput[29];
|
||||
5'b11110 : readData1 = regOutput[30];
|
||||
5'b11111 : readData1 = regOutput[31];
|
||||
default : readData1 = `XLEN'h0;
|
||||
endcase
|
||||
|
||||
//address 2 decoder
|
||||
case(adr2)
|
||||
5'b00000 : readData2 = regOutput[0];
|
||||
5'b00001 : readData2 = regOutput[1];
|
||||
5'b00010 : readData2 = regOutput[2];
|
||||
5'b00011 : readData2 = regOutput[3];
|
||||
5'b00100 : readData2 = regOutput[4];
|
||||
5'b00101 : readData2 = regOutput[5];
|
||||
5'b00110 : readData2 = regOutput[6];
|
||||
5'b00111 : readData2 = regOutput[7];
|
||||
5'b01000 : readData2 = regOutput[8];
|
||||
5'b01001 : readData2 = regOutput[9];
|
||||
5'b01010 : readData2 = regOutput[10];
|
||||
5'b01011 : readData2 = regOutput[11];
|
||||
5'b01100 : readData2 = regOutput[12];
|
||||
5'b01101 : readData2 = regOutput[13];
|
||||
5'b01110 : readData2 = regOutput[14];
|
||||
5'b01111 : readData2 = regOutput[15];
|
||||
5'b10000 : readData2 = regOutput[16];
|
||||
5'b10001 : readData2 = regOutput[17];
|
||||
5'b10010 : readData2 = regOutput[18];
|
||||
5'b10011 : readData2 = regOutput[19];
|
||||
5'b10100 : readData2 = regOutput[20];
|
||||
5'b10101 : readData2 = regOutput[21];
|
||||
5'b10110 : readData2 = regOutput[22];
|
||||
5'b10111 : readData2 = regOutput[23];
|
||||
5'b11000 : readData2 = regOutput[24];
|
||||
5'b11001 : readData2 = regOutput[25];
|
||||
5'b11010 : readData2 = regOutput[26];
|
||||
5'b11011 : readData2 = regOutput[27];
|
||||
5'b11100 : readData2 = regOutput[28];
|
||||
5'b11101 : readData2 = regOutput[29];
|
||||
5'b11110 : readData2 = regOutput[30];
|
||||
5'b11111 : readData2 = regOutput[31];
|
||||
default : readData2 = `XLEN'h0;
|
||||
endcase
|
||||
end
|
||||
|
||||
//destination register decoder
|
||||
//only change input values on write
|
||||
//defaults to undefined with invalid address
|
||||
//
|
||||
//note - this is an intermediary signal, so
|
||||
//this is not asynch assignment. FF in flopr
|
||||
//will not update data until clk pulse
|
||||
always_comb begin
|
||||
if(write) begin
|
||||
case(rd)
|
||||
5'b00000 : regInput[0] = writeData;
|
||||
5'b00001 : regInput[1] = writeData;
|
||||
5'b00010 : regInput[2] = writeData;
|
||||
5'b00011 : regInput[3] = writeData;
|
||||
5'b00100 : regInput[4] = writeData;
|
||||
5'b00101 : regInput[5] = writeData;
|
||||
5'b00110 : regInput[6] = writeData;
|
||||
5'b00111 : regInput[7] = writeData;
|
||||
5'b01000 : regInput[8] = writeData;
|
||||
5'b01000 : regInput[9] = writeData;
|
||||
5'b01001 : regInput[10] = writeData;
|
||||
5'b01010 : regInput[11] = writeData;
|
||||
5'b01111 : regInput[12] = writeData;
|
||||
5'b01101 : regInput[13] = writeData;
|
||||
5'b01110 : regInput[14] = writeData;
|
||||
5'b01111 : regInput[15] = writeData;
|
||||
5'b10000 : regInput[16] = writeData;
|
||||
5'b10001 : regInput[17] = writeData;
|
||||
5'b10010 : regInput[18] = writeData;
|
||||
5'b10011 : regInput[19] = writeData;
|
||||
5'b10100 : regInput[20] = writeData;
|
||||
5'b10101 : regInput[21] = writeData;
|
||||
5'b10110 : regInput[22] = writeData;
|
||||
5'b10111 : regInput[23] = writeData;
|
||||
5'b11000 : regInput[24] = writeData;
|
||||
5'b11000 : regInput[25] = writeData;
|
||||
5'b11001 : regInput[26] = writeData;
|
||||
5'b11010 : regInput[27] = writeData;
|
||||
5'b11111 : regInput[28] = writeData;
|
||||
5'b11101 : regInput[29] = writeData;
|
||||
5'b11110 : regInput[30] = writeData;
|
||||
5'b11111 : regInput[31] = writeData;
|
||||
default : regInput[0] = `XLEN'hx;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//********
|
||||
//formatting separation
|
||||
//********
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module freg3adr (
|
||||
input logic [2:0] frm,
|
||||
input logic reset,
|
||||
input logic clear,
|
||||
input logic clk,
|
||||
input logic [4:0] rd,
|
||||
input logic write,
|
||||
input logic [4:0] adr1,
|
||||
input logic [4:0] adr2,
|
||||
input logic [4:0] adr3,
|
||||
input logic [`XLEN-1:0] writeData,
|
||||
output logic [`XLEN-1:0] readData1,
|
||||
output logic [`XLEN-1:0] readData2,
|
||||
output logic [`XLEN-1:0] readData3);
|
||||
|
||||
//note - not word aligning based on precision of
|
||||
//operation (frm)
|
||||
|
||||
//reg number should remain static, but it doesn't hurt
|
||||
//to parameterize
|
||||
parameter numRegs = 32;
|
||||
|
||||
//intermediary signals - useful for debugging
|
||||
//and easy instatiation of generated modules
|
||||
logic [`XLEN-1:0] [numRegs-1:0] regInput;
|
||||
logic [`XLEN-1:0] [numRegs-1:0] regOutput;
|
||||
|
||||
//generate fp registers themselves
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < numRegs; i = i + 1) begin:register
|
||||
|
||||
floprc #(`XLEN) (.clk(clk), .reset(reset), .clear(clear), .d(regInput[i][`XLEN-1:0]), .q(regOutput[i][`XLEN-1:0]));
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
//address decoder
|
||||
//3 are used for this fp register set
|
||||
//used exclusively for fma
|
||||
//defaults to outputting zeroes
|
||||
always_comb begin
|
||||
|
||||
//adderss 1 decoder
|
||||
case(adr1)
|
||||
5'b00000 : readData1 = regOutput[0];
|
||||
5'b00001 : readData1 = regOutput[1];
|
||||
5'b00010 : readData1 = regOutput[2];
|
||||
5'b00011 : readData1 = regOutput[3];
|
||||
5'b00100 : readData1 = regOutput[4];
|
||||
5'b00101 : readData1 = regOutput[5];
|
||||
5'b00110 : readData1 = regOutput[6];
|
||||
5'b00111 : readData1 = regOutput[7];
|
||||
5'b01000 : readData1 = regOutput[8];
|
||||
5'b01001 : readData1 = regOutput[9];
|
||||
5'b01010 : readData1 = regOutput[10];
|
||||
5'b01011 : readData1 = regOutput[11];
|
||||
5'b01100 : readData1 = regOutput[12];
|
||||
5'b01101 : readData1 = regOutput[13];
|
||||
5'b01110 : readData1 = regOutput[14];
|
||||
5'b01111 : readData1 = regOutput[15];
|
||||
5'b10000 : readData1 = regOutput[16];
|
||||
5'b10001 : readData1 = regOutput[17];
|
||||
5'b10010 : readData1 = regOutput[18];
|
||||
5'b10011 : readData1 = regOutput[19];
|
||||
5'b10100 : readData1 = regOutput[20];
|
||||
5'b10101 : readData1 = regOutput[21];
|
||||
5'b10110 : readData1 = regOutput[22];
|
||||
5'b10111 : readData1 = regOutput[23];
|
||||
5'b11000 : readData1 = regOutput[24];
|
||||
5'b11001 : readData1 = regOutput[25];
|
||||
5'b11010 : readData1 = regOutput[26];
|
||||
5'b11011 : readData1 = regOutput[27];
|
||||
5'b11100 : readData1 = regOutput[28];
|
||||
5'b11101 : readData1 = regOutput[29];
|
||||
5'b11110 : readData1 = regOutput[30];
|
||||
5'b11111 : readData1 = regOutput[31];
|
||||
default : readData1 = `XLEN'h0;
|
||||
endcase
|
||||
|
||||
//address 2 decoder
|
||||
case(adr2)
|
||||
5'b00000 : readData2 = regOutput[0];
|
||||
5'b00001 : readData2 = regOutput[1];
|
||||
5'b00010 : readData2 = regOutput[2];
|
||||
5'b00011 : readData2 = regOutput[3];
|
||||
5'b00100 : readData2 = regOutput[4];
|
||||
5'b00101 : readData2 = regOutput[5];
|
||||
5'b00110 : readData2 = regOutput[6];
|
||||
5'b00111 : readData2 = regOutput[7];
|
||||
5'b01000 : readData2 = regOutput[8];
|
||||
5'b01001 : readData2 = regOutput[9];
|
||||
5'b01010 : readData2 = regOutput[10];
|
||||
5'b01011 : readData2 = regOutput[11];
|
||||
5'b01100 : readData2 = regOutput[12];
|
||||
5'b01101 : readData2 = regOutput[13];
|
||||
5'b01110 : readData2 = regOutput[14];
|
||||
5'b01111 : readData2 = regOutput[15];
|
||||
5'b10000 : readData2 = regOutput[16];
|
||||
5'b10001 : readData2 = regOutput[17];
|
||||
5'b10010 : readData2 = regOutput[18];
|
||||
5'b10011 : readData2 = regOutput[19];
|
||||
5'b10100 : readData2 = regOutput[20];
|
||||
5'b10101 : readData2 = regOutput[21];
|
||||
5'b10110 : readData2 = regOutput[22];
|
||||
5'b10111 : readData2 = regOutput[23];
|
||||
5'b11000 : readData2 = regOutput[24];
|
||||
5'b11001 : readData2 = regOutput[25];
|
||||
5'b11010 : readData2 = regOutput[26];
|
||||
5'b11011 : readData2 = regOutput[27];
|
||||
5'b11100 : readData2 = regOutput[28];
|
||||
5'b11101 : readData2 = regOutput[29];
|
||||
5'b11110 : readData2 = regOutput[30];
|
||||
5'b11111 : readData2 = regOutput[31];
|
||||
default : readData2 = `XLEN'h0;
|
||||
endcase
|
||||
|
||||
//address 3 decoder
|
||||
case(adr3)
|
||||
5'b00000 : readData3 = regOutput[0];
|
||||
5'b00001 : readData3 = regOutput[1];
|
||||
5'b00010 : readData3 = regOutput[2];
|
||||
5'b00011 : readData3 = regOutput[3];
|
||||
5'b00100 : readData3 = regOutput[4];
|
||||
5'b00101 : readData3 = regOutput[5];
|
||||
5'b00110 : readData3 = regOutput[6];
|
||||
5'b00111 : readData3 = regOutput[7];
|
||||
5'b01000 : readData3 = regOutput[8];
|
||||
5'b01001 : readData3 = regOutput[9];
|
||||
5'b01010 : readData3 = regOutput[10];
|
||||
5'b01011 : readData3 = regOutput[11];
|
||||
5'b01100 : readData3 = regOutput[12];
|
||||
5'b01101 : readData3 = regOutput[13];
|
||||
5'b01110 : readData3 = regOutput[14];
|
||||
5'b01111 : readData3 = regOutput[15];
|
||||
5'b10000 : readData3 = regOutput[16];
|
||||
5'b10001 : readData3 = regOutput[17];
|
||||
5'b10010 : readData3 = regOutput[18];
|
||||
5'b10011 : readData3 = regOutput[19];
|
||||
5'b10100 : readData3 = regOutput[20];
|
||||
5'b10101 : readData3 = regOutput[21];
|
||||
5'b10110 : readData3 = regOutput[22];
|
||||
5'b10111 : readData3 = regOutput[23];
|
||||
5'b11000 : readData3 = regOutput[24];
|
||||
5'b11001 : readData3 = regOutput[25];
|
||||
5'b11010 : readData3 = regOutput[26];
|
||||
5'b11011 : readData3 = regOutput[27];
|
||||
5'b11100 : readData3 = regOutput[28];
|
||||
5'b11101 : readData3 = regOutput[29];
|
||||
5'b11110 : readData3 = regOutput[30];
|
||||
5'b11111 : readData3 = regOutput[31];
|
||||
default : readData3 = `XLEN'h0;
|
||||
endcase
|
||||
end
|
||||
|
||||
//destination register decoder
|
||||
//only change input values on write
|
||||
//defaults to undefined with invalid address
|
||||
//
|
||||
//note - this is an intermediary signal, so
|
||||
//this is not asynch assignment. FF in flopr
|
||||
//will not update data until clk pulse
|
||||
always_comb begin
|
||||
if(write) begin
|
||||
case(rd)
|
||||
5'b00000 : regInput[0] = writeData;
|
||||
5'b00001 : regInput[1] = writeData;
|
||||
5'b00010 : regInput[2] = writeData;
|
||||
5'b00011 : regInput[3] = writeData;
|
||||
5'b00100 : regInput[4] = writeData;
|
||||
5'b00101 : regInput[5] = writeData;
|
||||
5'b00110 : regInput[6] = writeData;
|
||||
5'b00111 : regInput[7] = writeData;
|
||||
5'b01000 : regInput[8] = writeData;
|
||||
5'b01000 : regInput[9] = writeData;
|
||||
5'b01001 : regInput[10] = writeData;
|
||||
5'b01010 : regInput[11] = writeData;
|
||||
5'b01111 : regInput[12] = writeData;
|
||||
5'b01101 : regInput[13] = writeData;
|
||||
5'b01110 : regInput[14] = writeData;
|
||||
5'b01111 : regInput[15] = writeData;
|
||||
5'b10000 : regInput[16] = writeData;
|
||||
5'b10001 : regInput[17] = writeData;
|
||||
5'b10010 : regInput[18] = writeData;
|
||||
5'b10011 : regInput[19] = writeData;
|
||||
5'b10100 : regInput[20] = writeData;
|
||||
5'b10101 : regInput[21] = writeData;
|
||||
5'b10110 : regInput[22] = writeData;
|
||||
5'b10111 : regInput[23] = writeData;
|
||||
5'b11000 : regInput[24] = writeData;
|
||||
5'b11000 : regInput[25] = writeData;
|
||||
5'b11001 : regInput[26] = writeData;
|
||||
5'b11010 : regInput[27] = writeData;
|
||||
5'b11111 : regInput[28] = writeData;
|
||||
5'b11101 : regInput[29] = writeData;
|
||||
5'b11110 : regInput[30] = writeData;
|
||||
5'b11111 : regInput[31] = writeData;
|
||||
default : regInput[0] = `XLEN'hx;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue