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JAL testing
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bbracker
parent
a886e222c1
commit
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2 changed files with 263 additions and 1 deletions
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@ -137,6 +137,7 @@ string tests64iNOc[] = {
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"rv64i/I-XORI-01", "3000",
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"rv64i/WALLY-ADD", "4000",
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"rv64i/WALLY-SUB", "4000",
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"rv64i/WALLY-JAL", "4000",
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"rv64i/WALLY-STORE", "3000"
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};
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string tests32ic[] = '{
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@ -219,7 +220,8 @@ string tests32i[] = {
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"rv32i/I-XORI-01","2000",
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"rv32i/WALLY-ADD", "3000",
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"rv32i/WALLY-SUB", "3000",
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"rv32i/WALLY-STORE", "2000"
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"rv32i/WALLY-STORE", "2000",
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"rv32i/WALLY-JAL", "3000"
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};
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string tests[];
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260
wally-pipelined/testgen/testgen-JAL.py
Executable file
260
wally-pipelined/testgen/testgen-JAL.py
Executable file
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@ -0,0 +1,260 @@
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#!/usr/bin/python3
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##################################
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# testgen-JAL.py
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#
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# Ben Bracker (bbracker@hmc.edu) 19 January 2021
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# Based on testgen-ADD-SUB.py by David Harris
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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##################################
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##################################
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# libraries
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##################################
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from datetime import datetime
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from random import randint
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from random import choice
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from random import seed
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from random import getrandbits
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from copy import deepcopy
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##################################
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# functions
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##################################
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def InitTestGroup():
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global TestGroup,TestGroupSizes,AllRegs,UnusedRegs,StoreAdrReg
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TestGroup += 1
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TestGroupSizes.append(0)
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UnusedRegs = deepcopy(AllRegs)
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oldStoreAdrReg = StoreAdrReg
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while ((StoreAdrReg == oldStoreAdrReg) or (StoreAdrReg == 0) or (StoreAdrReg == 31)):
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StoreAdrReg = choice(UnusedRegs)
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UnusedRegs.remove(StoreAdrReg)
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f.write("\n # ---------------------------------------------------------------------------------------------\n")
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f.write(" # new register for address of test results\n")
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addInst(" la x"+str(StoreAdrReg)+", test_1_res\n")
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f.write(" # ---------------------------------------------------------------------------------------------\n")
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def registerSelect():
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# ensures that rd experiences all possible registers
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# *** does not yet ensure that rs experiences all possible registers
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# ensures that at least once rd = rs
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global UnusedRegs
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if len(UnusedRegs)==0:
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InitTestGroup()
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rd = choice(UnusedRegs)
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rs = choice(UnusedRegs)
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UnusedRegs.remove(rd)
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OtherRegs = deepcopy(AllRegs)
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OtherRegs.remove(StoreAdrReg)
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OtherRegs.remove(rd)
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try:
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OtherRegs.remove(0)
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except:
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pass
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try:
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OtherRegs.remove(rs)
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except:
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pass
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DataReg = choice(OtherRegs)
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OtherRegs.remove(DataReg)
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OtherRd = choice(OtherRegs)
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return (rd,rs,DataReg,OtherRd)
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def addInst(line):
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global CurrAdr
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f.write(line)
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if ("li x" in line):
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CurrAdr += 8 if (xlen == 32) else 20
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elif ("la x" in line):
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CurrAdr += 8
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else:
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CurrAdr += 4
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def writeForwardsJumpVector(spacers):
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global TestNum
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rd, rs, DataReg, OtherRd = registerSelect()
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if (xlen==64):
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expected = int("fedbca9876540000",16)
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unexpected = int("ffff0000ffff0000",16)
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else:
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expected = int("fedbca98",16)
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unexpected = int("ff00ff00",16)
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f.write("\n")
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f.write(" # Testcase "+str(TestNum)+" address cmp result rd:x"+str(rd)+"("+formatstr.format(CurrAdr+44)+") data result rd:x"+str(DataReg)+"("+formatstr.format(expected)+")\n")
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addInst(" li x"+str(DataReg)+", "+formatstr.format(expected)+"\n")
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addInst(" JAL x"+str(rd)+", 1f\n")
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LinkAdr = CurrAdr if (rd!=0) else 0 # rd's expected value
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for i in range(spacers):
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addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
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f.write("1:\n")
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addInst(" "+storecmd+" x"+str(rd)+", "+str(wordsize*(2*TestNum+0))+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(rd)+", "+formatstr.format(LinkAdr)+")\n")
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addInst(" "+storecmd+" x"+str(DataReg)+", "+str(wordsize*(2*TestNum+1))+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(DataReg)+", "+formatstr.format(expected)+")\n")
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writeExpectedToRef(LinkAdr)
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writeExpectedToRef(expected)
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TestNum = TestNum+1
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def writeBackwardsJumpVector(spacers):
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global TestNum
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rd, rs, DataReg,OtherRd = registerSelect()
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if (xlen==64):
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expected = int("fedbca9876540000",16)
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unexpected = int("ffff0000ffff0000",16)
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else:
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expected = int("fedbca98",16)
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unexpected = int("ff00ff00",16)
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f.write("\n")
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f.write(" # Testcase "+str(TestNum)+" address cmp result rd:x"+str(rd)+"("+formatstr.format(CurrAdr+20+8*spacers)+") data result rd:x"+str(DataReg)+"("+formatstr.format(expected)+")\n")
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addInst(" JAL x"+str(OtherRd)+", 2f\n")
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f.write("1:\n")
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addInst(" li x"+str(DataReg)+", "+formatstr.format(expected)+"\n")
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addInst(" JAL x"+str(OtherRd)+", 3f\n")
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f.write("2:\n")
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for i in range(spacers):
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addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
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addInst(" JAL x"+str(rd)+", 1b\n")
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LinkAdr = CurrAdr if (rd!=0) else 0 # rd's expected value
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f.write("3:\n")
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addInst(" "+storecmd+" x"+str(rd)+", "+str(wordsize*(2*TestNum+0))+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(rd)+", "+formatstr.format(LinkAdr)+")\n")
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addInst(" "+storecmd+" x"+str(DataReg)+", "+str(wordsize*(2*TestNum+1))+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(DataReg)+", "+formatstr.format(expected)+")\n")
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writeExpectedToRef(LinkAdr)
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writeExpectedToRef(expected)
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TestNum = TestNum+1
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def writeChainVector(repetitions,spacers):
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global TestNum
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rd, rs, DataReg,OtherRd = registerSelect()
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if (xlen==64):
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expected = int("fedbca9876540000",16)
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unexpected = int("ffff0000ffff0000",16)
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else:
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expected = int("fedbca98",16)
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unexpected = int("ff00ff00",16)
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f.write("\n")
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f.write(" # Testcase "+str(TestNum)+" address cmp result rd:x"+str(rd)+"(ugh; if you really wanted to, you could figure it out) data result rd:x"+str(DataReg)+"("+formatstr.format(expected)+")\n")
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addInst(" li x"+str(DataReg)+", "+formatstr.format(expected)+"\n")
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for i in range(repetitions):
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addInst(" JAL x"+str(OtherRd)+", "+str(3*i+2)+"f\n")
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if spacers:
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for j in range(i):
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addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
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f.write(str(3*i+1)+":\n")
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addInst(" JAL x"+str(OtherRd)+", "+str(3*i+3)+"f\n")
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if spacers:
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for j in range(i):
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addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
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f.write(str(3*i+2)+":\n")
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addInst(" JAL x"+str(rd)+", "+str(3*i+1)+"b\n")
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LinkAdr = CurrAdr if (rd!=0) else 0 # rd's expected value
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if spacers:
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for j in range(i):
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addInst(" li x"+str(DataReg)+", "+formatstr.format(unexpected)+"\n")
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f.write(str(3*i+3)+":\n")
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addInst(" "+storecmd+" x"+str(rd)+", "+str(wordsize*(2*TestNum+0))+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(rd)+", "+formatstr.format(LinkAdr)+")\n")
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addInst(" "+storecmd+" x"+str(DataReg)+", "+str(wordsize*(2*TestNum+1))+"(x"+str(StoreAdrReg)+")\n")
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f.write(" RVTEST_IO_ASSERT_GPR_EQ(x"+str(StoreAdrReg+1)+", x"+str(DataReg)+", "+formatstr.format(expected)+")\n")
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writeExpectedToRef(LinkAdr)
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writeExpectedToRef(expected)
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TestNum = TestNum+1
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def writeExpectedToRef(expected):
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global TestGroupSizes
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TestGroupSizes[TestGroup-1] += 1
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if (xlen == 32):
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r.write(formatrefstr.format(expected)+"\n")
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else:
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r.write(formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32)+"\n")
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##################################
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# main body
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##################################
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# change these to suite your tests
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tests = ["JAL"]
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author = "Ben Bracker (bbracker@hmc.edu)"
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xlens = [32,64]
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numtests = 100;
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# setup
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seed(0) # make tests reproducible
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# generate files for each test
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for xlen in xlens:
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CurrAdr = int("80000108",16)
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TestNum = 0
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TestGroup = 1
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TestGroupSizes = [0]
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AllRegs = list(range(0,32))
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UnusedRegs = deepcopy(AllRegs)
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StoreAdrReg = 6 # matches what's in header script
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UnusedRegs.remove(6)
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formatstrlen = str(int(xlen/4))
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formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
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formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
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if (xlen == 32):
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storecmd = "sw"
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wordsize = 4
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else:
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storecmd = "sd"
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wordsize = 8
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for test in tests:
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imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
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basename = "WALLY-" + test
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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f.write("///////////////////////////////////////////\n")
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f.write("// "+fname+ "\n")
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f.write("//\n")
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f.write("// This file can be used to test the RISC-V JAL instruction.\n")
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f.write("// But be warned that altering the test environment may break this test!\n")
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f.write("// In order to work, this test expects that the first instruction (la)\n")
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f.write("// be allocated at 0x80000100.\n")
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f.write("//\n")
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f.write("// " + author + "\n")
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f.write("// Created "+str(datetime.now())+"\n")
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# insert generic header
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h = open("testgen_header.S", "r")
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for line in h:
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f.write(line)
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# print directed test vectors
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for i in range(0,31):
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writeForwardsJumpVector(randint(0,4))
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for i in range(0,31):
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writeBackwardsJumpVector(randint(0,4))
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writeForwardsJumpVector(100)
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writeBackwardsJumpVector(100)
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writeChainVector(6,True)
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writeChainVector(16,False)
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# print footer
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h = open("testgen_footer.S", "r")
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for line in h:
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f.write(line)
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# Finish
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f.write(".fill "+str(sum(TestGroupSizes))+", "+str(wordsize)+", -1\n")
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f.write("\nRV_COMPLIANCE_DATA_END\n")
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f.close()
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r.close()
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