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Added PLIC signals for debugging on FPGA.

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This commit is contained in:
Jacob Pease 2022-10-25 13:57:09 -05:00
parent ff7d6b2932
commit 160ca366c8
2 changed files with 529 additions and 302 deletions
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817
fpga/constraints/debug2.xdc
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File diff suppressed because one or more lines are too long

14
pipelined/src/uncore/plic_apb.sv
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@ -61,7 +61,7 @@ module plic_apb (
logic memwrite, memread, initTrans;
logic [23:0] entry;
logic [31:0] Din, Dout;
(* mark_debug = "true" *) logic [31:0] Din, Dout;
// context-independent signals
(* mark_debug = "true" *) logic [`N:1] requests;
@ -69,14 +69,14 @@ module plic_apb (
(* mark_debug = "true" *) logic [`N:1] intInProgress, intPending, nextIntPending;
// context-dependent signals
logic [`C-1:0][2:0] intThreshold;
(* mark_debug = "true" *) logic [`C-1:0][2:0] intThreshold;
(* mark_debug = "true" *) logic [`C-1:0][`N:1] intEn;
logic [`C-1:0][5:0] intClaim; // ID's are 6 bits if we stay within 63 sources
(* mark_debug = "true" *) logic [`C-1:0][5:0] intClaim; // ID's are 6 bits if we stay within 63 sources
(* mark_debug = "true" *) logic [`C-1:0][7:1][`N:1] irqMatrix;
logic [`C-1:0][7:1] priorities_with_irqs;
logic [`C-1:0][7:1] max_priority_with_irqs;
logic [`C-1:0][`N:1] irqs_at_max_priority;
logic [`C-1:0][7:1] threshMask;
(* mark_debug = "true" *) logic [`C-1:0][7:1] priorities_with_irqs;
(* mark_debug = "true" *) logic [`C-1:0][7:1] max_priority_with_irqs;
(* mark_debug = "true" *) logic [`C-1:0][`N:1] irqs_at_max_priority;
(* mark_debug = "true" *) logic [`C-1:0][7:1] threshMask;
// =======
// AHB I/O