Merge remote-tracking branch 'upstream/main'

benchmarks/coremark/Makefile

@@ -28,8 +28,7 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
 all: $(work_dir)/coremark.bare.riscv.elf.memfile
 
 run: $(work_dir)/coremark.bare.riscv.elf.memfile
-#	time wsim rv$(XLEN)gc coremark --sim verilator 2>&1 | tee $(work_dir)/coremark.sim.log
-	time wsim ${CONFIG} coremark 2>&1 | tee $(work_dir)/coremark.sim.log
+	time wsim --sim verilator ${CONFIG} coremark 2>&1 | tee $(work_dir)/coremark.sim.log
 
 $(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
 	riscv64-unknown-elf-objdump -D $< > $<.elf.objdump

benchmarks/embench/Makefile

@@ -43,7 +43,7 @@ sim: sim_build_memfile sim_run speed
 
 # launches sim to simulate tests on wally
 sim_run:
-	wsim rv32gc embench --params "BPRED_LOGGER=1\'b1" 
+	wsim --sim verilator rv32gc embench --params "BPRED_LOGGER=1\'b1" 
 
 # builds the objdump based on the compiled c elf files
 objdump:

bin/regression-wally

@@ -392,7 +392,6 @@ def parse_args():
     parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true")
     parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true")
     parser.add_argument("--branch", help="Run branch predictor accuracy tests", action="store_true")
-    parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true") # Currently not used
     parser.add_argument("--breker", help="Run Breker tests", action="store_true") # Requires a license for the breker tool. See tests/breker/README.md for details
     parser.add_argument("--dryrun", help="Print commands invoked to console without running regression", action="store_true")
 

sim/questa/wally.do

@@ -195,7 +195,8 @@ vlog -permissive -lint -work ${WKDIR} {*}${INC_DIRS} {*}${DefineArgs} {*}${locks
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
 vopt $accFlag ${WKDIR}.${TESTBENCH} ${brekervopt} -work ${WKDIR} {*}${ExpandedParamArgs} -o testbenchopt ${CoverageVoptArg}
 
-vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} -suppress 3829 ${CoverageVsimArg}
+vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} {*}${PlusArgs} -fatal 7 {*}${SVLib} -suppress 3829 ${CoverageVsimArg} 
+# +IDV_TRACE2LOG=1  (add this to vsim command to enable ImperasDV RVVI trace logging)
 
 # power add generates the logging necessary for saif generation.
 # power add -r /dut/core/*

sim/verilator/README.md

@@ -1,32 +0,0 @@
-# Simulation with Verilator
-
-Different executables will be built for different architecture configurations, e.g., rv64gc, rv32i. A executable can run all the test suites that it can run with `+TEST=<testsuite>`.
-
-Demand:
-
-- Avoid unnecessary compilation by sharing the same executable for a specific configuration
-    - executables are stored in `obj_dir_non_profiling` and `obj_dir_profiling` correspondingly
-- Wsim should support `-s verilator` option and run simulation with Verilator.
-
-## Folder Structure
-
-This folder contains the following files that help the simulation of Wally with Verilator:
-
-- Makefile: simplify the usage with Verialtor
-- executables
-    - `obj_dir_non_profiling`: non-profiling executables for different configurations
-    - `obj_dir_profiling`: profiling executables for different configurations
-- logs in `logs` and `logs_profiling` correspondingly
-- [NOT WORKING] `logs`: contains all the logs
-
-## Examples
-
-```shell
-# non-profiling mode
-make WALLYCONF=rv64gc TEST=arch64i run
-# profiling mode
-make WALLYCONF=rv64gc TEST=arch64i profile
-
-# remove all the temporary files, including executables and logs
-make clean
-```

testbench/common/wallyTracer.sv

@@ -81,6 +81,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   logic [1:0]              IPageTypeF, IPageTypeD, IPageTypeE, IPageTypeM, IPageTypeW, DPageTypeM, DPageTypeW;
   logic                    ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
   logic                    ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
+  logic [P.XLEN-1:0]       order;
 
   assign clk = testbench.dut.clk;
   //  assign InstrValidF = testbench.dut.core.ieu.InstrValidF;  // not needed yet
@@ -375,10 +376,16 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   // Initially connecting the writeback stage signals, but may need to use M stage
   // and gate on ~FlushW.
 
+
+  // count the number of valid instructions to provide ordering to RVVI tracer
+  always @(posedge clk)
+    if (reset) order <= 0;
+    else if (valid) order <= order + 1;
+
   assign valid  = ((InstrValidW | TrapW) & ~StallW) & ~reset;
   assign rvvi.clk = clk;
   assign rvvi.valid[0][0]    = valid;
-  assign rvvi.order[0][0]    = rvvi.csr[0][0][12'hB02];  // TODO: IMPERAS Should be event order
+  assign rvvi.order[0][0]    = order; 
   assign rvvi.insn[0][0]     = InstrRawW;
   assign rvvi.pc_rdata[0][0] = PCW;
   assign rvvi.trap[0][0]     = TrapW;

testbench/testbench.sv

@@ -762,6 +762,7 @@ end
               .CMP_VR      (0),
               .CMP_CSR     (P.ZICSR_SUPPORTED)
               ) idv_trace2api(rvvi);
+  trace2log idv_trace2log(rvvi); // enable Imperas tracer
 
   string filename;
   initial begin

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h

@@ -611,7 +611,7 @@ ext_interrupt_\MODE\():
     // lists what to do on each exception (not interrupts)
     // unexpected exceptions should cause segfaults for easy detection
     // Expected exceptions should increment the EPC to the next instruction and return
-
+.data
     .align 2 // aligns this data table to an 4 byte boundary
 exception_vector_table_\MODE\():
     .4byte addr_misaligned_\MODE\()      // 0: instruction address misaligned
@@ -652,6 +652,7 @@ trap_return_pagetype_table_\MODE\():
     .4byte 0xC  // 0: kilopage has 12 offset bits
     .4byte 0x16 // 1: megapage has 22 offset bits
 
+.section .text.init
 trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler and continue with the test
 .endm
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h

@@ -606,6 +606,7 @@ ext_interrupt_\MODE\():
     // unexpected exceptions should cause segfaults for easy detection
     // Expected exceptions should increment the EPC to the next instruction and return
 
+.data
     .align 3 // aligns this data table to an 8 byte boundary
 exception_vector_table_\MODE\():
     .8byte addr_misaligned_\MODE\()      // 0: instruction address misaligned
@@ -647,6 +648,8 @@ trap_return_pagetype_table_\MODE\():
     .8byte 0x1E // 2: gigapage has 30 offset bits
     .8byte 0x27 // 3: terapage has 39 offset bits
 
+.section .text.init
+
 trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler and continue with the test
 .endm