Progress on Verilator simulation. Full adder compiles and runs. Wally builds.

.gitignore

@@ -182,3 +182,5 @@ benchmarks/embench/run*
 sim/cfi.log
 sim/cfi/*
 sim/branch/*
+sim/obj_dir
+examples/verilog/fulladder/obj_dir

bin/wally-tool-chain-install.sh

@@ -166,7 +166,7 @@ sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
 
 # riscof
 sudo pip3 install -U testresources riscv_config
-pip3 install git+https://github.com/riscv/riscof.git
+sudo pip3 install git+https://github.com/riscv/riscof.git
 
 # Download OSU Skywater 130 cell library
 sudo mkdir -p $RISCV/cad/lib

examples/verilog/fulladder/fulladder.sv

@@ -3,6 +3,7 @@ module testbench();
   logic        a, b, c, s, cout, sexpected, coutexpected;
   logic [31:0] vectornum, errors;
   logic [4:0]  testvectors[10000:0];
+  integer cycle;
 
   // instantiate device under test
   fulladder dut(a, b, c, s, cout);
@@ -11,12 +12,15 @@ module testbench();
   always 
     begin
       clk = 1; #5; clk = 0; #5;
+      cycle = cycle + 1;
+      $display("cycle: %x vectornum %x testvectors[vectornum]: %b", cycle, vectornum, testvectors[vectornum]);
     end
 
   // at start of test, load vectors and pulse reset
   initial
     begin
       $readmemb("fulladder.tv", testvectors);
+      cycle = 0;
       vectornum = 0; errors = 0;
       reset = 1; #22; reset = 0;
     end
@@ -36,10 +40,11 @@ module testbench();
         errors = errors + 1;
       end
       vectornum = vectornum + 1;
-      if (testvectors[vectornum] === 5'bx) begin 
+      //if (testvectors[vectornum] === 5'bx) begin 
+      if (vectornum === 10) begin 
         $display("%d tests completed with %d errors", 
 	           vectornum, errors);
-        $stop;
+        $finish;
       end
     end
 endmodule

examples/verilog/fulladder/verilate

@@ -0,0 +1,5 @@
+#verilator --timescale "1ns/1ns" --timing -cc --exe --build --top-module testbench fulladder.sv
+#verilator --timescale "1ns/1ns" --timing -cc --exe --top-module testbench fulladder.sv
+#verilator --binary --top-module testbench fulladder.sv
+verilator --timescale "1ns/1ns" --timing --binary --top-module testbench fulladder.sv
+

sim/verilate

@@ -8,9 +8,11 @@ basepath=$(dirname $0)/..
 #for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
 for config in  rv64gc; do
     echo "$config simulating..."
-    if !($verilator --timescale "1ns/1ns" --timing --exe --cc "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv   $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
+    # not working: -GTEST="arch64i"
+    if !($verilator --timescale "1ns/1ns" --timing --binary "$@" --top-module testbench "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/cvw.sv $basepath/testbench/testbench.sv $basepath/testbench/common/*.sv   $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
         echo "Exiting after $config lint due to errors or warnings"
         exit 1
     fi
+    ./obj_dir/Vtestbench 
 done
 echo "Verilation complete"