mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-24 22:07:12 -04:00
Setup the testbench to exclude the warmup from performance counter reports.
This commit is contained in:
Ross Thompson
parent
f6e97cf516
commit
1c381b0546
3 changed files with 89 additions and 62 deletions
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@ -67,12 +67,24 @@ def ComputeICacheMissRate(benchmark):
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ICacheMR = 100.0 * int(dataDict['I Cache Miss']) / int(dataDict['I Cache Access'])
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dataDict['ICacheMR'] = ICacheMR
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def ComputeICacheMissTime(benchmark):
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'Computes and inserts instruction class miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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ICacheMR = 100.0 * int(dataDict['I Cache Cycles']) / int(dataDict['I Cache Miss'])
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dataDict['ICacheMT'] = ICacheMR
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def ComputeDCacheMissRate(benchmark):
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'Computes and inserts instruction class miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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DCacheMR = 100.0 * int(dataDict['D Cache Miss']) / int(dataDict['D Cache Access'])
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dataDict['DCacheMR'] = DCacheMR
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def ComputeDCacheMissTime(benchmark):
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'Computes and inserts instruction class miss prediction rate.'
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(nameString, opt, dataDict) = benchmark
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ICacheMR = 100.0 * int(dataDict['D Cache Cycles']) / int(dataDict['D Cache Miss'])
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dataDict['DCacheMT'] = ICacheMR
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def ComputeAll(benchmarks):
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for benchmark in benchmarks:
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ComputeCPI(benchmark)
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@ -81,23 +93,23 @@ def ComputeAll(benchmarks):
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ComputeRASMissRate(benchmark)
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ComputeInstrClassMissRate(benchmark)
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ComputeICacheMissRate(benchmark)
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ComputeICacheMissTime(benchmark)
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ComputeDCacheMissRate(benchmark)
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ComputeDCacheMissTime(benchmark)
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def printStats(benchmark):
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(nameString, opt, dataDict) = benchmark
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CPI = dataDict['CPI']
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BDMR = dataDict['BDMR']
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BTMR = dataDict['BTMR']
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RASMPR = dataDict['RASMPR']
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print('Test', nameString)
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print('Compile configuration', opt)
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print('CPI \t\t\t %1.2f' % CPI)
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print('Branch Dir Pred Miss Rate %2.2f' % BDMR)
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print('Branch Target Pred Miss Rate %2.2f' % BTMR)
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print('RAS Miss Rate \t\t %1.2f' % RASMPR)
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print('CPI \t\t\t %1.2f' % dataDict['CPI'])
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print('Branch Dir Pred Miss Rate %2.2f' % dataDict['BDMR'])
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print('Branch Target Pred Miss Rate %2.2f' % dataDict['BTMR'])
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print('RAS Miss Rate \t\t %1.2f' % dataDict['RASMPR'])
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print('Instr Class Miss Rate %1.2f' % dataDict['ClassMPR'])
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print('I Cache Miss Rate %1.4f' % dataDict['ICacheMR'])
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print('I Cache Miss Ave Cycles %1.4f' % dataDict['ICacheMT'])
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print('D Cache Miss Rate %1.4f' % dataDict['DCacheMR'])
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print('D Cache Miss Ave Cycles %1.4f' % dataDict['DCacheMT'])
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print()
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def ProcessFile(fileName):
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@ -156,7 +168,7 @@ def GeometricAverage(benchmarks, field):
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return Product ** (1.0/index)
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def ComputeGeometricAverage(benchmarks):
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fields = ['BDMR', 'BTMR', 'RASMPR', 'ClassMPR', 'ICacheMR', 'DCacheMR', 'CPI']
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fields = ['BDMR', 'BTMR', 'RASMPR', 'ClassMPR', 'ICacheMR', 'DCacheMR', 'CPI', 'ICacheMT', 'DCacheMT']
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AllAve = {}
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for field in fields:
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Product = 1
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76
sim/wave.do
76
sim/wave.do
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@ -6,7 +6,6 @@ add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset_ext
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add wave -noupdate /testbench/memfilename
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add wave -noupdate /testbench/dut/core/SATP_REGW
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
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@ -56,11 +55,11 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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@ -91,19 +90,10 @@ add wave -noupdate -group CSRs -group {user mode} /testbench/dut/core/priv/priv/
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add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
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add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
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add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
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add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/BPPredPCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/SelBPPredF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
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add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
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@ -457,7 +447,6 @@ add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbe
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add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
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add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
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add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
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add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
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add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF
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add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
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add wave -noupdate -group ifu /testbench/dut/core/ifu/IFUStallF
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@ -465,7 +454,6 @@ add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/Spill/spill/C
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add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/SpillF
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add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallD
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add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF
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add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/InstrDAPageFaultF
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add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF
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add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/SelNextSpillF
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add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
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@ -558,19 +546,29 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c
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add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1}
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add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
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add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
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add wave -noupdate -expand -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Branch -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {Jump (Not Return)} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label Return -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP Dir Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BTA Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {RAS Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
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add wave -noupdate -expand -group {Performance Counters} -expand -group BP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
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add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Access} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[16]}
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add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[17]}
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add wave -noupdate -expand -group {Performance Counters} -group ICACHE -label {I Cache Miss Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[18]}
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add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Load Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
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add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {Store Stall} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
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add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
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add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
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add wave -noupdate -expand -group {Performance Counters} -group DCACHE -label {D Cache Miss Cycles} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
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add wave -noupdate -expand -group {Performance Counters} -group Privileged -label {CSR Write} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[19]}
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add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Fence.I {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[20]}
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add wave -noupdate -expand -group {Performance Counters} -group Privileged -label sfence.VMA {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[21]}
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add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Interrupt {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[22]}
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add wave -noupdate -expand -group {Performance Counters} -group Privileged -label Exception {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[23]}
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add wave -noupdate -expand -group {Performance Counters} -label {FDiv or IDiv Cycles} {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[24]}
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add wave -noupdate -expand -group {Performance Counters} /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
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add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY
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add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer
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@ -604,10 +602,6 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd
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add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
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add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
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add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
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add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
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add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
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add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE
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add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
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add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
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add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
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@ -615,27 +609,23 @@ add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/c
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add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
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add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
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add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
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add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
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add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
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add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
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add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
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add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheAccess
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheMiss
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheAccess
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheMiss
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/InstrValidNotFlushedM
|
||||
add wave -noupdate /testbench/clk
|
||||
add wave -noupdate /testbench/HPMCSample/FinalHPMCOUNTERH
|
||||
add wave -noupdate /testbench/HPMCSample/InitialHPMCOUNTERH
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {368581 ns} 0} {{Cursor 5} {394987 ns} 1}
|
||||
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {717301 ns} 0} {{Cursor 5} {394987 ns} 1}
|
||||
quietly wave cursor active 4
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 194
|
||||
|
|
@ -651,4 +641,4 @@ configure wave -griddelta 40
|
|||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {368125 ns} {368797 ns}
|
||||
WaveRestoreZoom {717254 ns} {717585 ns}
|
||||
|
|
|
|||
|
|
@ -401,17 +401,24 @@ logic [3:0] dummy;
|
|||
end // always @ (negedge clk)
|
||||
|
||||
|
||||
if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin
|
||||
if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample
|
||||
integer HPMCindex;
|
||||
logic StartSampleFirst;
|
||||
logic StartSampleDelayed;
|
||||
logic StartSample;
|
||||
logic EndSample;
|
||||
logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
|
||||
logic [`XLEN-1:0] FinalHPMCOUNTERH[`COUNTERS-1:0];
|
||||
|
||||
string HPMCnames[] = '{"Mcycle",
|
||||
"------",
|
||||
"InstRet",
|
||||
"Br Count",
|
||||
"Jump, JR, Jal",
|
||||
"Jump Not Return",
|
||||
"Return",
|
||||
"Br Dir Wrong",
|
||||
"Br Pred Wrong",
|
||||
"Br Target Wrong",
|
||||
"BP Wrong",
|
||||
"BP Dir Wrong",
|
||||
"BP Target Wrong",
|
||||
"RAS Wrong",
|
||||
"Instr Class Wrong",
|
||||
"Load Stall",
|
||||
|
|
@ -429,16 +436,34 @@ logic [3:0] dummy;
|
|||
"Exception",
|
||||
"Divide Cycles"
|
||||
};
|
||||
assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
|
||||
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
|
||||
assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
|
||||
|
||||
assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
|
||||
|
||||
always @(negedge clk) begin
|
||||
if(DCacheFlushStart & ~DCacheFlushDone) begin
|
||||
if(StartSample) begin
|
||||
for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
|
||||
InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
|
||||
end
|
||||
end
|
||||
if(EndSample) begin
|
||||
for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
|
||||
FinalHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
|
||||
end
|
||||
end
|
||||
if(EndSample) begin
|
||||
for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
|
||||
// unlikely to have more than 10M in any counter.
|
||||
$display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex], HPMCnames[HPMCindex]);
|
||||
end
|
||||
end
|
||||
end
|
||||
$display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]);
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
// track the current function or global label
|
||||
if (DEBUG == 1) begin : FunctionName
|
||||
FunctionName FunctionName(.reset(reset),
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue