github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-06-27 17:01:20 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Generate UCDB with riscof plugin

Browse source
This commit is contained in:
Jordan Carlin 2025-05-09 13:17:55 -07:00
parent 638919d094
commit 1f87d87a81
No known key found for this signature in database
1 changed files with 5 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

5
tests/riscof/sail_cSim/riscof_sail_cSim.py
View file

@ -116,6 +116,11 @@ class sail_cSim(pluginTemplate):
trace_command = f'{cvw_arch_verif_dir}/bin/sail-parse.py {test_name}.log {test_name}.trace;'
execute += trace_command
# Generate ucdb coverage file
questa_do_file = f'{cvw_arch_verif_dir}/bin/cvw-arch-verif.do'
coverage_command = f'vsim -c -do "do {questa_do_file} {test_dir} {test_name} {cvw_arch_verif_dir}/fcov";'
execute += coverage_command
# TODO: generate trace from sail log, send into questa to gen ucdb, both dumped in test specific dir