mirror of
https://github.com/openhwgroup/cvw.git
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Holy smokes! first try and I got the genesys2 board running!
This commit is contained in:
Rose Thompson
parent
19a26cfbd0
commit
23c0c751da
9 changed files with 1296 additions and 1 deletions
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@ -62,6 +62,9 @@ BPRED_SIZE 32'd12
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deriv fpgaArtyA7 fpga
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EXT_MEM_RANGE 64'h0FFFFFFF
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deriv fpgagenesys2 fpga
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EXT_MEM_RANGE 64'h3FFFFFFF
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deriv fpgavcu108 fpga
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EXT_MEM_RANGE 64'h7FFFFFFF
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283
fpga/constraints/constraints-genesys2.xdc
Normal file
283
fpga/constraints/constraints-genesys2.xdc
Normal file
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@ -0,0 +1,283 @@
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# The main clocks are all autogenerated by the Xilinx IP
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# clk_out3_xlnx_mmcm is the 20Mhz clock from the mmcm used to drive wally and the AHB Bus.
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# mmcm_clkout0 is the clock output of the DDR3 memory interface / 4.
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# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP.
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#create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
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create_generated_clock -name SPISDCClock -source [get_pins mmcm/clk_out3] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK]
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##### clock #####
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set_property PACKAGE_PIN AD12 [get_ports default_200mhz_clk_p]
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set_property PACKAGE_PIN AD11 [get_ports default_200mhz_clk_n]
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set_property IOSTANDARD LVDS [get_ports default_200mhz_clk_p]
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# *** don't love this hack. RT: Don't understand why the recomemded input clock is causing a clock routing issue.
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set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets default_200mhz_clk_p]
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set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets default_200mhz_clk_n]
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##### RVVI Ethernet ####
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# taken from https://github.com/Digilent/digilent-xdc/blob/master/Genesys-2-Master.xdc
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set_property -dict { PACKAGE_PIN AH11 IOSTANDARD LVCMOS15 } [get_ports { phy_rxctl }]; #IO_L18P_T2_33 Sch=eth_rx_ctl
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set_property -dict { PACKAGE_PIN AG10 IOSTANDARD LVCMOS15 } [get_ports { phy_rx_clk }]; #IO_L13P_T2_MRCC_33 Sch=eth_rx_clk
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set_property -dict { PACKAGE_PIN AJ14 IOSTANDARD LVCMOS15 } [get_ports { phy_rxd[0] }]; #IO_L21N_T3_DQS_33 Sch=eth_rx_d[0]
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set_property -dict { PACKAGE_PIN AH14 IOSTANDARD LVCMOS15 } [get_ports { phy_rxd[1] }]; #IO_L21P_T3_DQS_33 Sch=eth_rx_d[1]
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set_property -dict { PACKAGE_PIN AK13 IOSTANDARD LVCMOS15 } [get_ports { phy_rxd[2] }]; #IO_L20N_T3_33 Sch=eth_rx_d[2]
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set_property -dict { PACKAGE_PIN AJ13 IOSTANDARD LVCMOS15 } [get_ports { phy_rxd[3] }]; #IO_L22P_T3_33 Sch=eth_rx_d[3]
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set_property -dict { PACKAGE_PIN AE10 IOSTANDARD LVCMOS15 } [get_ports { phy_tx_clk }]; #IO_L14P_T2_SRCC_33 Sch=eth_tx_clk
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set_property -dict { PACKAGE_PIN AK14 IOSTANDARD LVCMOS15 } [get_ports { phy_tx_en }]; #IO_L20P_T3_33 Sch=eth_tx_en
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set_property -dict { PACKAGE_PIN AJ12 IOSTANDARD LVCMOS15 } [get_ports { phy_txd[0] }]; #IO_L22N_T3_33 Sch=eth_tx_d[0]
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set_property -dict { PACKAGE_PIN AK11 IOSTANDARD LVCMOS15 } [get_ports { phy_txd[1] }]; #IO_L17P_T2_33 Sch=eth_tx_d[1]
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set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15 } [get_ports { phy_txd[2] }]; #IO_L18N_T2_33 Sch=eth_tx_d[2]
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set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS15 } [get_ports { phy_txd[3] }]; #IO_L17N_T2_33 Sch=eth_tx_d[3]
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# have to update these in the future. Follow the rvviopt branch from the vcu108 config.
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#set_property -dict { PACKAGE_PIN AK16 IOSTANDARD LVCMOS18 } [get_ports { eth_int_b }]; #IO_L1P_T0_32 Sch=eth_intb
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#set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdc }]; #IO_L23P_T3_33 Sch=eth_mdc
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#set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdio }]; #IO_L23N_T3_33 Sch=eth_mdio
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#set_property -dict { PACKAGE_PIN AH24 IOSTANDARD LVCMOS33 } [get_ports { ETH_PHYRST_N }]; #IO_L14N_T2_SRCC_12 Sch=eth_phyrst_n
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#set_property -dict { PACKAGE_PIN AK15 IOSTANDARD LVCMOS18 } [get_ports { eth_pme_b }]; #IO_L1N_T0_32 Sch=eth_pmeb
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##### GPI ####
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set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { GPI[0] }]; #IO_25_17 Sch=btnc
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set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS12 } [get_ports { GPI[1] }]; #IO_0_15 Sch=btnd
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set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS12 } [get_ports { GPI[2] }]; #IO_L6P_T0_15 Sch=btnl
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set_property -dict { PACKAGE_PIN C19 IOSTANDARD LVCMOS12 } [get_ports { GPI[3] }]; #IO_L24P_T3_17 Sch=btnr
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}]
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set_max_delay -from [get_ports {GPI[*]}] 20.000
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##### GPO ####
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set_property -dict { PACKAGE_PIN T28 IOSTANDARD LVCMOS33 } [get_ports { GPO[0] }]; #IO_L11N_T1_SRCC_14 Sch=led[0]
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set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { GPO[1] }]; #IO_L19P_T3_A10_D26_14 Sch=led[1]
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set_property -dict { PACKAGE_PIN U30 IOSTANDARD LVCMOS33 } [get_ports { GPO[2] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[2]
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set_property -dict { PACKAGE_PIN U29 IOSTANDARD LVCMOS33 } [get_ports { GPO[3] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=led[3]
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set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { GPO[4] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=led[4]
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set_max_delay -to [get_ports {GPO[*]}] 20.000
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set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
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set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]
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##### UART #####
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# *** IOSTANDARD is probably wrong
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set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { UARTSout }]; #IO_L1P_T0_12 Sch=uart_rx_out
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set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { UARTSin }]; #IO_0_12 Sch=uart_tx_in
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#set_property DRIVE 4 [get_ports UARTSout]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSin]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSin]
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set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
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set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSout]
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##### reset #####
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#************** reset is inverted
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set_property -dict { PACKAGE_PIN B19 IOSTANDARD LVCMOS12 } [get_ports { south_reset }]; #IO_L24N_T3_17 Sch=btnu
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set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { resetn }]; #IO_0_14 Sch=cpu_resetn
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports resetn]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports resetn]
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set_max_delay -from [get_ports resetn] 20.000
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set_false_path -from [get_ports resetn]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports south_reset]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports south_reset]
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set_max_delay -from [get_ports south_reset] 20.000
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set_false_path -from [get_ports south_reset]
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##### SD Card I/O #####
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#***** may have to switch to Pmod JB or JC.
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# SDCDat[3]
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set_property PACKAGE_PIN V27 [get_ports SDCCS]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCS]
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set_property PULLTYPE PULLUP [get_ports SDCCS]
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# set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[2]}]
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# set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS33 PULLUP true} [get_ports {SDCDat[1]}]
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# SDCDat[0]
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set_property PACKAGE_PIN V24 [get_ports SDCIn]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCIn]
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set_property PULLTYPE PULLUP [get_ports SDCIn]
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set_property PACKAGE_PIN W22 [get_ports SDCCLK]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCLK]
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set_property PULLTYPE PULLUP [get_ports SDCCLK]
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set_property PACKAGE_PIN Y30 [get_ports SDCCmd]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCmd]
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set_property PULLTYPE PULLUP [get_ports SDCCmd]
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set_property PACKAGE_PIN V22 [get_ports SDCCD]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCCD]
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set_property PULLTYPE PULLUP [get_ports SDCCD]
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set_property PACKAGE_PIN W21 [get_ports SDCWP]
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set_property IOSTANDARD LVCMOS33 [get_ports SDCWP]
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set_property PULLTYPE PULLUP [get_ports SDCWP]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
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set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
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set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
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set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks SPISDCClock] 0.000 [get_ports SDCCLK]
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#set_multicycle_path -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10
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set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000
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# *********************************
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#set_property DCI_CASCADE {64} [get_iobanks 65]
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#set_property INTERNAL_VREF 0.9 [get_iobanks 65]
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# ddr3
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[31]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_p[0]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_n[0]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_p[1]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_n[1]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_p[2]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_n[2]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_p[3]]
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set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports ddr3_dqs_n[3]]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
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set_property IOSTANDARD DIFF_SSTL15_DCI [get_ports ddr3_ck_p[0]]
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set_property IOSTANDARD DIFF_SSTL15_DCI [get_ports ddr3_ck_n[0]]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_reset_n]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n[0]}]
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set_property PACKAGE_PIN AC12 [get_ports ddr3_addr[0]]
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set_property PACKAGE_PIN AB8 [get_ports ddr3_addr[10]]
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set_property PACKAGE_PIN AA8 [get_ports ddr3_addr[11]]
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set_property PACKAGE_PIN AB12 [get_ports ddr3_addr[12]]
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set_property PACKAGE_PIN AA12 [get_ports ddr3_addr[13]]
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set_property PACKAGE_PIN AH9 [get_ports ddr3_addr[14]]
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set_property PACKAGE_PIN AE8 [get_ports ddr3_addr[1]]
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set_property PACKAGE_PIN AD8 [get_ports ddr3_addr[2]]
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set_property PACKAGE_PIN AC10 [get_ports ddr3_addr[3]]
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set_property PACKAGE_PIN AD9 [get_ports ddr3_addr[4]]
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set_property PACKAGE_PIN AA13 [get_ports ddr3_addr[5]]
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set_property PACKAGE_PIN AA10 [get_ports ddr3_addr[6]]
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set_property PACKAGE_PIN AA11 [get_ports ddr3_addr[7]]
|
||||
set_property PACKAGE_PIN Y10 [get_ports ddr3_addr[8]]
|
||||
set_property PACKAGE_PIN Y11 [get_ports ddr3_addr[9]]
|
||||
set_property PACKAGE_PIN AE9 [get_ports ddr3_ba[0]]
|
||||
set_property PACKAGE_PIN AB10 [get_ports ddr3_ba[1]]
|
||||
set_property PACKAGE_PIN AC11 [get_ports ddr3_ba[2]]
|
||||
set_property PACKAGE_PIN AF11 [get_ports ddr3_cas_n]
|
||||
set_property PACKAGE_PIN AC9 [get_ports ddr3_ck_n[0]]
|
||||
set_property PACKAGE_PIN AB9 [get_ports ddr3_ck_p[0]]
|
||||
set_property PACKAGE_PIN AJ9 [get_ports ddr3_cke[0]]
|
||||
set_property PACKAGE_PIN AH12 [get_ports ddr3_cs_n[0]]
|
||||
set_property PACKAGE_PIN AD4 [get_ports ddr3_dm[0]]
|
||||
set_property PACKAGE_PIN AF3 [get_ports ddr3_dm[1]]
|
||||
set_property PACKAGE_PIN AH4 [get_ports ddr3_dm[2]]
|
||||
set_property PACKAGE_PIN AF8 [get_ports ddr3_dm[3]]
|
||||
set_property PACKAGE_PIN AD3 [get_ports ddr3_dq[0]]
|
||||
set_property PACKAGE_PIN AF1 [get_ports ddr3_dq[10]]
|
||||
set_property PACKAGE_PIN AE4 [get_ports ddr3_dq[11]]
|
||||
set_property PACKAGE_PIN AE3 [get_ports ddr3_dq[12]]
|
||||
set_property PACKAGE_PIN AE5 [get_ports ddr3_dq[13]]
|
||||
set_property PACKAGE_PIN AF5 [get_ports ddr3_dq[14]]
|
||||
set_property PACKAGE_PIN AF6 [get_ports ddr3_dq[15]]
|
||||
set_property PACKAGE_PIN AJ4 [get_ports ddr3_dq[16]]
|
||||
set_property PACKAGE_PIN AH6 [get_ports ddr3_dq[17]]
|
||||
set_property PACKAGE_PIN AH5 [get_ports ddr3_dq[18]]
|
||||
set_property PACKAGE_PIN AH2 [get_ports ddr3_dq[19]]
|
||||
set_property PACKAGE_PIN AC2 [get_ports ddr3_dq[1]]
|
||||
set_property PACKAGE_PIN AJ2 [get_ports ddr3_dq[20]]
|
||||
set_property PACKAGE_PIN AJ1 [get_ports ddr3_dq[21]]
|
||||
set_property PACKAGE_PIN AK1 [get_ports ddr3_dq[22]]
|
||||
set_property PACKAGE_PIN AJ3 [get_ports ddr3_dq[23]]
|
||||
set_property PACKAGE_PIN AF7 [get_ports ddr3_dq[24]]
|
||||
set_property PACKAGE_PIN AG7 [get_ports ddr3_dq[25]]
|
||||
set_property PACKAGE_PIN AJ6 [get_ports ddr3_dq[26]]
|
||||
set_property PACKAGE_PIN AK6 [get_ports ddr3_dq[27]]
|
||||
set_property PACKAGE_PIN AJ8 [get_ports ddr3_dq[28]]
|
||||
set_property PACKAGE_PIN AK8 [get_ports ddr3_dq[29]]
|
||||
set_property PACKAGE_PIN AC1 [get_ports ddr3_dq[2]]
|
||||
set_property PACKAGE_PIN AK5 [get_ports ddr3_dq[30]]
|
||||
set_property PACKAGE_PIN AK4 [get_ports ddr3_dq[31]]
|
||||
set_property PACKAGE_PIN AC5 [get_ports ddr3_dq[3]]
|
||||
set_property PACKAGE_PIN AC4 [get_ports ddr3_dq[4]]
|
||||
set_property PACKAGE_PIN AD6 [get_ports ddr3_dq[5]]
|
||||
set_property PACKAGE_PIN AE6 [get_ports ddr3_dq[6]]
|
||||
set_property PACKAGE_PIN AC7 [get_ports ddr3_dq[7]]
|
||||
set_property PACKAGE_PIN AF2 [get_ports ddr3_dq[8]]
|
||||
set_property PACKAGE_PIN AE1 [get_ports ddr3_dq[9]]
|
||||
set_property PACKAGE_PIN AD1 [get_ports ddr3_dqs_n[0]]
|
||||
set_property PACKAGE_PIN AG3 [get_ports ddr3_dqs_n[1]]
|
||||
set_property PACKAGE_PIN AH1 [get_ports ddr3_dqs_n[2]]
|
||||
set_property PACKAGE_PIN AJ7 [get_ports ddr3_dqs_n[3]]
|
||||
set_property PACKAGE_PIN AD2 [get_ports ddr3_dqs_p[0]]
|
||||
set_property PACKAGE_PIN AG4 [get_ports ddr3_dqs_p[1]]
|
||||
set_property PACKAGE_PIN AG2 [get_ports ddr3_dqs_p[2]]
|
||||
set_property PACKAGE_PIN AH7 [get_ports ddr3_dqs_p[3]]
|
||||
set_property PACKAGE_PIN AK9 [get_ports ddr3_odt[0]]
|
||||
set_property PACKAGE_PIN AE11 [get_ports ddr3_ras_n]
|
||||
set_property PACKAGE_PIN AG5 [get_ports ddr3_reset_n]
|
||||
set_property PACKAGE_PIN AG13 [get_ports ddr3_we_n]
|
||||
|
|
@ -2,7 +2,7 @@ dst := IP
|
|||
|
||||
all: ArtyA7
|
||||
|
||||
.PHONY: ArtyA7 vcu118 vcu108
|
||||
.PHONY: ArtyA7 vcu118 vcu108 genesys2
|
||||
|
||||
ArtyA7: export XILINX_PART := xc7a100tcsg324-1
|
||||
ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
|
||||
|
|
@ -25,6 +25,13 @@ vcu108: export SYSTEMCLOCK := 50000000
|
|||
vcu108: export MAXSDCCLOCK := 12500000
|
||||
vcu108: FPGA_VCU
|
||||
|
||||
genesys2: export XILINX_PART := xc7k325tffg900-2
|
||||
genesys2: export XILINX_BOARD := digilentinc.com:genesys2:part0:1.1
|
||||
genesys2: export board := genesys2
|
||||
genesys2: export SYSTEMCLOCK := 25000000
|
||||
genesys2: export MAXSDCCLOCK := 12500000
|
||||
genesys2: FPGA_GENESYS2
|
||||
|
||||
# variables computed from config
|
||||
EXT_MEM_BASE = $(shell grep 'EXT_MEM_BASE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/0x\1/g')
|
||||
|
||||
|
|
@ -37,6 +44,9 @@ FPGA_Arty: PreProcessFiles IP_Arty zsbl
|
|||
FPGA_VCU: PreProcessFiles IP_VCU zsbl
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
|
||||
FPGA_GENESYS2: PreProcessFiles IP_GENESYS2 zsbl
|
||||
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
|
||||
|
||||
# Generate IP Blocks
|
||||
.PHONY: IP_Arty IP_VCU
|
||||
IP_VCU: $(dst)/sysrst.log \
|
||||
|
|
@ -49,6 +59,12 @@ IP_Arty: $(dst)/sysrst.log \
|
|||
$(dst)/clkconverter.log \
|
||||
$(dst)/ahbaxibridge.log
|
||||
|
||||
IP_GENESYS2: $(dst)/sysrst.log \
|
||||
MEM_GENESYS2 \
|
||||
$(dst)/mmcm-genesys2.log \
|
||||
$(dst)/clkconverter.log \
|
||||
$(dst)/ahbaxibridge.log
|
||||
|
||||
# Generate Memory IP Blocks
|
||||
.PHONY: MEM_VCU MEM_Arty
|
||||
MEM_VCU:
|
||||
|
|
@ -56,6 +72,9 @@ MEM_VCU:
|
|||
MEM_Arty:
|
||||
$(MAKE) $(dst)/ddr3-$(board).log
|
||||
|
||||
MEM_GENESYS2:
|
||||
$(MAKE) $(dst)/ddr3-$(board).log
|
||||
|
||||
# Copy files and make necessary modifications
|
||||
.PHONY: PreProcessFiles
|
||||
PreProcessFiles:
|
||||
|
|
|
|||
22
fpga/generator/ddr3-genesys2.tcl
Normal file
22
fpga/generator/ddr3-genesys2.tcl
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
|
||||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
|
||||
set ipName ddr3
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
# really just these two lines which change
|
||||
create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
|
||||
|
||||
exec mkdir -p IP/$ipName.srcs/sources_1/ip/$ipName
|
||||
exec cp ../xlnx_ddr3-genesys2-mig.prj $ipName.srcs/sources_1/ip/$ipName/xlnx_ddr3-genesys2-mig.prj
|
||||
|
||||
set_property -dict [list CONFIG.XML_INPUT_FILE {xlnx_ddr3-genesys2-mig.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName]
|
||||
|
||||
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
launch_run -jobs 8 ${ipName}_synth_1
|
||||
wait_on_run ${ipName}_synth_1
|
||||
32
fpga/generator/mmcm-genesys2.tcl
Normal file
32
fpga/generator/mmcm-genesys2.tcl
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
set partNumber $::env(XILINX_PART)
|
||||
set boardName $::env(XILINX_BOARD)
|
||||
set SYSTEMCLOCK $::env(SYSTEMCLOCK)
|
||||
set ipName mmcm
|
||||
|
||||
set SYSTEMCLOCK_MHz [expr $SYSTEMCLOCK/1000000.0]
|
||||
|
||||
create_project $ipName . -force -part $partNumber
|
||||
set_property board_part $boardName [current_project]
|
||||
|
||||
create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
|
||||
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000} \
|
||||
CONFIG.CLK_IN1_BOARD_INTERFACE {sys_diff_clock} \
|
||||
CONFIG.NUM_OUT_CLKS {4} \
|
||||
CONFIG.CLKOUT2_USED {true} \
|
||||
CONFIG.CLKOUT3_USED {true} \
|
||||
CONFIG.CLKOUT4_USED {true} \
|
||||
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200} \
|
||||
CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
|
||||
CONFIG.CLKOUT3_REQUESTED_OUT_FREQ $SYSTEMCLOCK_MHz \
|
||||
CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {25} \
|
||||
CONFIG.CLKIN1_JITTER_PS {10.0} \
|
||||
] [get_ips $ipName]
|
||||
|
||||
#set_property CONFIG.CLKOUT3_REQUESTED_OUT_FREQ $SYSTEMCLOCK_MHz [get_ips $ipName]
|
||||
|
||||
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
|
||||
launch_run -jobs 8 ${ipName}_synth_1
|
||||
wait_on_run ${ipName}_synth_1
|
||||
|
|
@ -28,6 +28,8 @@ add_files ../src/CopiedFiles_do_not_add_to_repo/cvw.sv
|
|||
# then read top level
|
||||
if {$board=="ArtyA7"} {
|
||||
add_files {../src/fpgaTopArtyA7.sv}
|
||||
} elseif {$board=="genesys2"} {
|
||||
add_files {../src/fpgaTopGenesys2.sv}
|
||||
} else {
|
||||
add_files {../src/fpgaTop.sv}
|
||||
}
|
||||
|
|
@ -37,9 +39,13 @@ import_ip IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci
|
|||
import_ip IP/ahbaxibridge.srcs/sources_1/ip/ahbaxibridge/ahbaxibridge.xci
|
||||
import_ip IP/clkconverter.srcs/sources_1/ip/clkconverter/clkconverter.xci
|
||||
|
||||
# *** merge these first two ifs
|
||||
if {$board=="ArtyA7"} {
|
||||
import_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci
|
||||
import_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci
|
||||
} elseif {$board=="genesys2"} {
|
||||
import_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci
|
||||
import_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci
|
||||
} else {
|
||||
import_ip IP/ddr4.srcs/sources_1/ip/ddr4/ddr4.xci
|
||||
}
|
||||
|
|
@ -65,9 +71,13 @@ report_compile_order -constraints > reports/compile_order.rpt
|
|||
#synth_design -rtl -name rtl_1 -flatten_hierarchy none
|
||||
|
||||
# apply timing constraint after elaboration
|
||||
# *** also merge these if/else
|
||||
if {$board=="ArtyA7"} {
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
|
||||
} elseif {$board=="genesys2"} {
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
|
||||
} else {
|
||||
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
|
||||
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
|
||||
|
|
@ -99,6 +109,8 @@ if {$board=="ArtyA7"} {
|
|||
#source ../constraints/small-debug.xdc
|
||||
#source ../constraints/small-debug-rvvi.xdc
|
||||
source ../constraints/small-debug-wfi.xdc
|
||||
} elseif {$board=="genesys2"} {
|
||||
source ../constraints/small-debug.xdc
|
||||
} else {
|
||||
#source ../constraints/vcu-small-debug.xdc
|
||||
#source ../constraints/small-debug.xdc
|
||||
|
|
|
|||
185
fpga/generator/xlnx_ddr3-genesys2-mig.prj
Normal file
185
fpga/generator/xlnx_ddr3-genesys2-mig.prj
Normal file
|
|
@ -0,0 +1,185 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project NoOfControllers="1">
|
||||
|
||||
|
||||
|
||||
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
|
||||
|
||||
<ModuleName>mig_7series_0</ModuleName>
|
||||
|
||||
<dci_inouts_inputs>1</dci_inouts_inputs>
|
||||
|
||||
<dci_inputs>1</dci_inputs>
|
||||
|
||||
<Debug_En>OFF</Debug_En>
|
||||
|
||||
<DataDepth_En>1024</DataDepth_En>
|
||||
|
||||
<LowPower_En>ON</LowPower_En>
|
||||
|
||||
<XADC_En>Enabled</XADC_En>
|
||||
|
||||
<TargetFPGA>xc7k325t-ffg900/-2</TargetFPGA>
|
||||
|
||||
<Version>4.1</Version>
|
||||
|
||||
<SystemClock>Single-Ended</SystemClock>
|
||||
|
||||
<ReferenceClock>No Buffer</ReferenceClock>
|
||||
|
||||
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
|
||||
|
||||
<BankSelectionFlag>FALSE</BankSelectionFlag>
|
||||
|
||||
<InternalVref>0</InternalVref>
|
||||
|
||||
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
|
||||
|
||||
<dci_cascade>0</dci_cascade>
|
||||
|
||||
<FPGADevice>
|
||||
<selected>7k/xc7k325t-ffg900</selected>
|
||||
</FPGADevice>
|
||||
|
||||
<Controller number="0">
|
||||
<MemoryDevice>DDR3_SDRAM/Components/MT41J256M16XX-107</MemoryDevice>
|
||||
<TimePeriod>1250</TimePeriod>
|
||||
<VccAuxIO>2.0V</VccAuxIO>
|
||||
<PHYRatio>4:1</PHYRatio>
|
||||
<InputClkFreq>200</InputClkFreq>
|
||||
<UIExtraClocks>0</UIExtraClocks>
|
||||
<MMCM_VCO>800</MMCM_VCO>
|
||||
<MMCMClkOut0> 1.000</MMCMClkOut0>
|
||||
<MMCMClkOut1>1</MMCMClkOut1>
|
||||
<MMCMClkOut2>1</MMCMClkOut2>
|
||||
<MMCMClkOut3>1</MMCMClkOut3>
|
||||
<MMCMClkOut4>1</MMCMClkOut4>
|
||||
<DataWidth>32</DataWidth>
|
||||
<DeepMemory>1</DeepMemory>
|
||||
<DataMask>1</DataMask>
|
||||
<ECC>Disabled</ECC>
|
||||
<Ordering>Normal</Ordering>
|
||||
<BankMachineCnt>4</BankMachineCnt>
|
||||
<CustomPart>FALSE</CustomPart>
|
||||
<NewPartName/>
|
||||
<RowAddress>15</RowAddress>
|
||||
<ColAddress>10</ColAddress>
|
||||
<BankAddress>3</BankAddress>
|
||||
<MemoryVoltage>1.5V</MemoryVoltage>
|
||||
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
|
||||
<PinSelection>
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC12" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB8" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA8" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB12" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA12" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH9" SLEW="" name="ddr3_addr[14]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE8" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD8" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC10" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD9" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA13" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA10" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AA11" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y10" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="Y11" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE9" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AB10" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AC11" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF11" SLEW="" name="ddr3_cas_n" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AC9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15" PADName="AB9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AJ9" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH12" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AD4" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF3" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AH4" SLEW="" name="ddr3_dm[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AF8" SLEW="" name="ddr3_dm[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD3" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF1" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE4" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE3" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE5" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF5" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF6" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ4" SLEW="" name="ddr3_dq[16]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH6" SLEW="" name="ddr3_dq[17]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH5" SLEW="" name="ddr3_dq[18]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AH2" SLEW="" name="ddr3_dq[19]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC2" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ2" SLEW="" name="ddr3_dq[20]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ1" SLEW="" name="ddr3_dq[21]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK1" SLEW="" name="ddr3_dq[22]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ3" SLEW="" name="ddr3_dq[23]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF7" SLEW="" name="ddr3_dq[24]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AG7" SLEW="" name="ddr3_dq[25]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ6" SLEW="" name="ddr3_dq[26]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK6" SLEW="" name="ddr3_dq[27]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AJ8" SLEW="" name="ddr3_dq[28]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK8" SLEW="" name="ddr3_dq[29]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC1" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK5" SLEW="" name="ddr3_dq[30]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AK4" SLEW="" name="ddr3_dq[31]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC5" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC4" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AD6" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE6" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AC7" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AF2" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15_T_DCI" PADName="AE1" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG3" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH1" SLEW="" name="ddr3_dqs_n[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AJ7" SLEW="" name="ddr3_dqs_n[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AD2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG4" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AG2" SLEW="" name="ddr3_dqs_p[2]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="DIFF_SSTL15_T_DCI" PADName="AH7" SLEW="" name="ddr3_dqs_p[3]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AK9" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AE11" SLEW="" name="ddr3_ras_n" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="LVCMOS15" PADName="AG5" SLEW="" name="ddr3_reset_n" IN_TERM="" />
|
||||
<Pin VCCAUX_IO="HIGH" IOSTANDARD="SSTL15" PADName="AG13" SLEW="" name="ddr3_we_n" IN_TERM="" />
|
||||
</PinSelection>
|
||||
<System_Clock>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="sys_clk_i"/>
|
||||
</System_Clock>
|
||||
<System_Control>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
|
||||
<Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
|
||||
</System_Control>
|
||||
<TimingParameters>
|
||||
<Parameters twtr="7.5" trrd="6" trefi="7.8" tfaw="35" trtp="7.5" tcke="5" trfc="260" trp="13.91" tras="34" trcd="13.91" />
|
||||
</TimingParameters>
|
||||
<mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength>
|
||||
<mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType>
|
||||
<mrCasLatency name="CAS Latency">11</mrCasLatency>
|
||||
<mrMode name="Mode">Normal</mrMode>
|
||||
<mrDllReset name="DLL Reset">No</mrDllReset>
|
||||
<mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode>
|
||||
<emrDllEnable name="DLL Enable">Enable</emrDllEnable>
|
||||
<emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/7</emrOutputDriveStrength>
|
||||
<emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection>
|
||||
<emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
|
||||
<emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/6</emrRTT>
|
||||
<emrPosted name="Additive Latency (AL)">0</emrPosted>
|
||||
<emrOCD name="Write Leveling Enable">Disabled</emrOCD>
|
||||
<emrDQS name="TDQS enable">Enabled</emrDQS>
|
||||
<emrRDQS name="Qoff">Output Buffer Enabled</emrRDQS>
|
||||
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh">Full Array</mr2PartialArraySelfRefresh>
|
||||
<mr2CasWriteLatency name="CAS write latency">8</mr2CasWriteLatency>
|
||||
<mr2AutoSelfRefresh name="Auto Self Refresh">Enabled</mr2AutoSelfRefresh>
|
||||
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate">Normal</mr2SelfRefreshTempRange>
|
||||
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)">Dynamic ODT off</mr2RTTWR>
|
||||
<PortInterface>AXI</PortInterface>
|
||||
<AXIParameters>
|
||||
<C0_C_RD_WR_ARB_ALGORITHM>ROUND_ROBIN</C0_C_RD_WR_ARB_ALGORITHM>
|
||||
<C0_S_AXI_ADDR_WIDTH>30</C0_S_AXI_ADDR_WIDTH>
|
||||
<C0_S_AXI_DATA_WIDTH>64</C0_S_AXI_DATA_WIDTH>
|
||||
<C0_S_AXI_ID_WIDTH>4</C0_S_AXI_ID_WIDTH>
|
||||
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
|
||||
</AXIParameters>
|
||||
</Controller>
|
||||
|
||||
|
||||
</Project>
|
||||
621
fpga/src/fpgaTopGenesys2.sv
Normal file
621
fpga/src/fpgaTopGenesys2.sv
Normal file
|
|
@ -0,0 +1,621 @@
|
|||
///////////////////////////////////////////
|
||||
// fpgaTop.sv
|
||||
//
|
||||
// Written: rose@rosethompson.net November 17, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: This is a top level for the fpga's implementation of wally.
|
||||
// Instantiates wallysoc, ddr4, abh lite to axi converters, pll, etc
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
`include "config.vh"
|
||||
|
||||
import cvw::*;
|
||||
|
||||
module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
|
||||
(input logic default_200mhz_clk_p,
|
||||
input logic default_200mhz_clk_n,
|
||||
input logic resetn,
|
||||
input logic south_reset,
|
||||
|
||||
// GPIO signals
|
||||
input logic [3:0] GPI,
|
||||
output logic [4:0] GPO,
|
||||
|
||||
// UART Signals
|
||||
input logic UARTSin,
|
||||
output logic UARTSout,
|
||||
|
||||
// SDC Signals connecting to an SPI peripheral
|
||||
input logic SDCIn,
|
||||
output logic SDCCLK,
|
||||
output logic SDCCmd,
|
||||
output logic SDCCS,
|
||||
input logic SDCCD,
|
||||
input logic SDCWP,
|
||||
/*
|
||||
* Ethernet: 100BASE-T MII
|
||||
*/
|
||||
//output logic phy_ref_clk, // *** add back in when we add rvvi
|
||||
input logic phy_rx_clk,
|
||||
input logic [3:0] phy_rxd,
|
||||
input logic phy_rxctl,
|
||||
input logic phy_tx_clk,
|
||||
output logic [3:0] phy_txd,
|
||||
output logic phy_tx_en,
|
||||
//output logic phy_reset_n,
|
||||
|
||||
inout logic [31:0] ddr3_dq,
|
||||
inout logic [3:0] ddr3_dqs_n,
|
||||
inout logic [3:0] ddr3_dqs_p,
|
||||
output logic [14:0] ddr3_addr,
|
||||
output logic [2:0] ddr3_ba,
|
||||
output logic ddr3_ras_n,
|
||||
output logic ddr3_cas_n,
|
||||
output logic ddr3_we_n,
|
||||
output logic ddr3_reset_n,
|
||||
output logic [0:0] ddr3_ck_p,
|
||||
output logic [0:0] ddr3_ck_n,
|
||||
output logic [0:0] ddr3_cke,
|
||||
output logic [0:0] ddr3_cs_n,
|
||||
output logic [3:0] ddr3_dm,
|
||||
output logic [0:0] ddr3_odt
|
||||
);
|
||||
|
||||
// MMCM Signals
|
||||
logic CPUCLK;
|
||||
logic c0_ddr4_ui_clk_sync_rst;
|
||||
logic bus_struct_reset;
|
||||
logic peripheral_reset;
|
||||
logic interconnect_aresetn;
|
||||
logic peripheral_aresetn;
|
||||
logic mb_reset;
|
||||
|
||||
// AHB Signals from Wally
|
||||
logic HCLKOpen;
|
||||
logic HRESETnOpen;
|
||||
logic [63:0] HRDATAEXT;
|
||||
logic HREADYEXT;
|
||||
logic HRESPEXT;
|
||||
logic HSELEXT;
|
||||
logic [55:0] HADDR;
|
||||
logic [63:0] HWDATA;
|
||||
logic [64/8-1:0] HWSTRB;
|
||||
logic HWRITE;
|
||||
logic [2:0] HSIZE;
|
||||
logic [2:0] HBURST;
|
||||
logic [1:0] HTRANS;
|
||||
logic HREADY;
|
||||
logic [3:0] HPROT;
|
||||
logic HMASTLOCK;
|
||||
|
||||
// GPIO Signals
|
||||
logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
|
||||
|
||||
// AHB to AXI Bridge Signals
|
||||
logic [3:0] m_axi_awid;
|
||||
logic [7:0] m_axi_awlen;
|
||||
logic [2:0] m_axi_awsize;
|
||||
logic [1:0] m_axi_awburst;
|
||||
logic [3:0] m_axi_awcache;
|
||||
logic [31:0] m_axi_awaddr;
|
||||
logic [2:0] m_axi_awprot;
|
||||
logic m_axi_awvalid;
|
||||
logic m_axi_awready;
|
||||
logic m_axi_awlock;
|
||||
logic [63:0] m_axi_wdata;
|
||||
logic [7:0] m_axi_wstrb;
|
||||
logic m_axi_wlast;
|
||||
logic m_axi_wvalid;
|
||||
logic m_axi_wready;
|
||||
logic [3:0] m_axi_bid;
|
||||
logic [1:0] m_axi_bresp;
|
||||
logic m_axi_bvalid;
|
||||
logic m_axi_bready;
|
||||
logic [3:0] m_axi_arid;
|
||||
logic [7:0] m_axi_arlen;
|
||||
logic [2:0] m_axi_arsize;
|
||||
logic [1:0] m_axi_arburst;
|
||||
logic [2:0] m_axi_arprot;
|
||||
logic [3:0] m_axi_arcache;
|
||||
logic m_axi_arvalid;
|
||||
logic [31:0] m_axi_araddr;
|
||||
logic m_axi_arlock;
|
||||
logic m_axi_arready;
|
||||
logic [3:0] m_axi_rid;
|
||||
logic [63:0] m_axi_rdata;
|
||||
logic [1:0] m_axi_rresp;
|
||||
logic m_axi_rvalid;
|
||||
logic m_axi_rlast;
|
||||
logic m_axi_rready;
|
||||
|
||||
// AXI Signals going out of Clock Converter
|
||||
logic [3:0] BUS_axi_arregion;
|
||||
logic [3:0] BUS_axi_arqos;
|
||||
logic [3:0] BUS_axi_awregion;
|
||||
logic [3:0] BUS_axi_awqos;
|
||||
logic [3:0] BUS_axi_awid;
|
||||
logic [7:0] BUS_axi_awlen;
|
||||
logic [2:0] BUS_axi_awsize;
|
||||
logic [1:0] BUS_axi_awburst;
|
||||
logic [3:0] BUS_axi_awcache;
|
||||
logic [31:0] BUS_axi_awaddr;
|
||||
logic [2:0] BUS_axi_awprot;
|
||||
logic BUS_axi_awvalid;
|
||||
logic BUS_axi_awready;
|
||||
logic BUS_axi_awlock;
|
||||
logic [63:0] BUS_axi_wdata;
|
||||
logic [7:0] BUS_axi_wstrb;
|
||||
logic BUS_axi_wlast;
|
||||
logic BUS_axi_wvalid;
|
||||
logic BUS_axi_wready;
|
||||
logic [3:0] BUS_axi_bid;
|
||||
logic [1:0] BUS_axi_bresp;
|
||||
logic BUS_axi_bvalid;
|
||||
logic BUS_axi_bready;
|
||||
logic [3:0] BUS_axi_arid;
|
||||
logic [7:0] BUS_axi_arlen;
|
||||
logic [2:0] BUS_axi_arsize;
|
||||
logic [1:0] BUS_axi_arburst;
|
||||
logic [2:0] BUS_axi_arprot;
|
||||
logic [3:0] BUS_axi_arcache;
|
||||
logic BUS_axi_arvalid;
|
||||
logic [31:0] BUS_axi_araddr;
|
||||
logic BUS_axi_arlock;
|
||||
logic BUS_axi_arready;
|
||||
logic [3:0] BUS_axi_rid;
|
||||
logic [63:0] BUS_axi_rdata;
|
||||
logic [1:0] BUS_axi_rresp;
|
||||
logic BUS_axi_rvalid;
|
||||
logic BUS_axi_rlast;
|
||||
logic BUS_axi_rready;
|
||||
|
||||
logic BUSCLK;
|
||||
logic sdio_reset_open;
|
||||
|
||||
logic c0_init_calib_complete;
|
||||
logic dbg_clk;
|
||||
logic [511 : 0] dbg_bus;
|
||||
logic ui_clk_sync_rst;
|
||||
|
||||
logic CLK208;
|
||||
logic clk167;
|
||||
logic clk200;
|
||||
|
||||
logic app_sr_active;
|
||||
logic app_ref_ack;
|
||||
logic app_zq_ack;
|
||||
logic mmcm_locked;
|
||||
logic [11:0] device_temp;
|
||||
logic mmcm1_locked;
|
||||
|
||||
(* mark_debug = "true" *) logic RVVIStall;
|
||||
|
||||
assign GPIOIN = {25'b0, SDCCD, SDCWP, 1'b0, GPI};
|
||||
assign GPO = GPIOOUT[4:0];
|
||||
assign ahblite_resetn = peripheral_aresetn;
|
||||
assign cpu_reset = bus_struct_reset;
|
||||
assign calib = c0_init_calib_complete;
|
||||
|
||||
logic [3:0] SDCCSin;
|
||||
assign SDCCS = SDCCSin[0];
|
||||
|
||||
// mmcm
|
||||
|
||||
// the ddr3 mig7 requires 2 input clocks
|
||||
// 1. sys clock which is 167 MHz = ddr3 clock / 4
|
||||
// 2. a second clock which is 200 MHz
|
||||
// Wally requires a slower clock. At this point I don't know what speed the atrix 7 will run so I'm initially targeting 25Mhz.
|
||||
// the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot.
|
||||
logic phy_ref_clk; // *** fix when we add rvvi
|
||||
mmcm mmcm(.clk_out1(clk167),
|
||||
.clk_out2(clk200),
|
||||
.clk_out3(CPUCLK),
|
||||
.clk_out4(phy_ref_clk),
|
||||
.reset(1'b0),
|
||||
.locked(mmcm1_locked),
|
||||
.clk_in1_p(default_200mhz_clk_p),
|
||||
.clk_in1_n(default_200mhz_clk_n));
|
||||
|
||||
|
||||
|
||||
// reset controller XILINX IP
|
||||
sysrst sysrst
|
||||
(.slowest_sync_clk(CPUCLK),
|
||||
.ext_reset_in(1'b0),
|
||||
.aux_reset_in(south_reset),
|
||||
.mb_debug_sys_rst(1'b0),
|
||||
.dcm_locked(c0_init_calib_complete),
|
||||
.mb_reset(mb_reset), //open
|
||||
.bus_struct_reset(bus_struct_reset),
|
||||
.peripheral_reset(peripheral_reset), //open
|
||||
.interconnect_aresetn(interconnect_aresetn), //open
|
||||
.peripheral_aresetn(peripheral_aresetn));
|
||||
|
||||
`include "parameter-defs.vh"
|
||||
|
||||
// Wally
|
||||
wallypipelinedsoc #(P)
|
||||
wallypipelinedsoc(.clk(CPUCLK), .reset_ext(bus_struct_reset), .reset(),
|
||||
.HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT,
|
||||
.HCLK(HCLKOpen), .HRESETn(HRESETnOpen),
|
||||
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0),
|
||||
.GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout, .SDCIn, .SDCCmd, .SDCCS(SDCCSin), .SDCCLK, .ExternalStall(RVVIStall));
|
||||
|
||||
|
||||
// ahb lite to axi bridge
|
||||
ahbaxibridge ahbaxibridge
|
||||
(.s_ahb_hclk(CPUCLK),
|
||||
.s_ahb_hresetn(peripheral_aresetn),
|
||||
.s_ahb_hsel(HSELEXT),
|
||||
.s_ahb_haddr(HADDR[31:0]),
|
||||
.s_ahb_hprot(HPROT),
|
||||
.s_ahb_htrans(HTRANS),
|
||||
.s_ahb_hsize(HSIZE),
|
||||
.s_ahb_hwrite(HWRITE),
|
||||
.s_ahb_hburst(HBURST),
|
||||
.s_ahb_hwdata(HWDATA),
|
||||
.s_ahb_hready_out(HREADYEXT),
|
||||
.s_ahb_hready_in(HREADY),
|
||||
.s_ahb_hrdata(HRDATAEXT),
|
||||
.s_ahb_hresp(HRESPEXT),
|
||||
.m_axi_awid(m_axi_awid),
|
||||
.m_axi_awlen(m_axi_awlen),
|
||||
.m_axi_awsize(m_axi_awsize),
|
||||
.m_axi_awburst(m_axi_awburst),
|
||||
.m_axi_awcache(m_axi_awcache),
|
||||
.m_axi_awaddr(m_axi_awaddr),
|
||||
.m_axi_awprot(m_axi_awprot),
|
||||
.m_axi_awvalid(m_axi_awvalid),
|
||||
.m_axi_awready(m_axi_awready),
|
||||
.m_axi_awlock(m_axi_awlock),
|
||||
.m_axi_wdata(m_axi_wdata),
|
||||
.m_axi_wstrb(m_axi_wstrb),
|
||||
.m_axi_wlast(m_axi_wlast),
|
||||
.m_axi_wvalid(m_axi_wvalid),
|
||||
.m_axi_wready(m_axi_wready),
|
||||
.m_axi_bid(m_axi_bid),
|
||||
.m_axi_bresp(m_axi_bresp),
|
||||
.m_axi_bvalid(m_axi_bvalid),
|
||||
.m_axi_bready(m_axi_bready),
|
||||
.m_axi_arid(m_axi_arid),
|
||||
.m_axi_arlen(m_axi_arlen),
|
||||
.m_axi_arsize(m_axi_arsize),
|
||||
.m_axi_arburst(m_axi_arburst),
|
||||
.m_axi_arprot(m_axi_arprot),
|
||||
.m_axi_arcache(m_axi_arcache),
|
||||
.m_axi_arvalid(m_axi_arvalid),
|
||||
.m_axi_araddr(m_axi_araddr),
|
||||
.m_axi_arlock(m_axi_arlock),
|
||||
.m_axi_arready(m_axi_arready),
|
||||
.m_axi_rid(m_axi_rid),
|
||||
.m_axi_rdata(m_axi_rdata),
|
||||
.m_axi_rresp(m_axi_rresp),
|
||||
.m_axi_rvalid(m_axi_rvalid),
|
||||
.m_axi_rlast(m_axi_rlast),
|
||||
.m_axi_rready(m_axi_rready));
|
||||
|
||||
// AXI Clock Converter
|
||||
clkconverter clkconverter
|
||||
(.s_axi_aclk(CPUCLK),
|
||||
.s_axi_aresetn(peripheral_aresetn),
|
||||
.s_axi_awid(m_axi_awid),
|
||||
.s_axi_awlen(m_axi_awlen),
|
||||
.s_axi_awsize(m_axi_awsize),
|
||||
.s_axi_awburst(m_axi_awburst),
|
||||
.s_axi_awcache(m_axi_awcache),
|
||||
.s_axi_awaddr(m_axi_awaddr[30:0] ),
|
||||
.s_axi_awprot(m_axi_awprot),
|
||||
.s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs
|
||||
.s_axi_awqos(4'b0), // this could be a bug. bridge does not have these outputs
|
||||
.s_axi_awvalid(m_axi_awvalid),
|
||||
.s_axi_awready(m_axi_awready),
|
||||
.s_axi_awlock(m_axi_awlock),
|
||||
.s_axi_wdata(m_axi_wdata),
|
||||
.s_axi_wstrb(m_axi_wstrb),
|
||||
.s_axi_wlast(m_axi_wlast),
|
||||
.s_axi_wvalid(m_axi_wvalid),
|
||||
.s_axi_wready(m_axi_wready),
|
||||
.s_axi_bid(m_axi_bid),
|
||||
.s_axi_bresp(m_axi_bresp),
|
||||
.s_axi_bvalid(m_axi_bvalid),
|
||||
.s_axi_bready(m_axi_bready),
|
||||
.s_axi_arid(m_axi_arid),
|
||||
.s_axi_arlen(m_axi_arlen),
|
||||
.s_axi_arsize(m_axi_arsize),
|
||||
.s_axi_arburst(m_axi_arburst),
|
||||
.s_axi_arprot(m_axi_arprot),
|
||||
.s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs
|
||||
.s_axi_arqos(4'b0), // this could be a bug. bridge does not have these outputs
|
||||
.s_axi_arcache(m_axi_arcache),
|
||||
.s_axi_arvalid(m_axi_arvalid),
|
||||
.s_axi_araddr(m_axi_araddr[30:0]),
|
||||
.s_axi_arlock(m_axi_arlock),
|
||||
.s_axi_arready(m_axi_arready),
|
||||
.s_axi_rid(m_axi_rid),
|
||||
.s_axi_rdata(m_axi_rdata),
|
||||
.s_axi_rresp(m_axi_rresp),
|
||||
.s_axi_rvalid(m_axi_rvalid),
|
||||
.s_axi_rlast(m_axi_rlast),
|
||||
.s_axi_rready(m_axi_rready),
|
||||
|
||||
.m_axi_aclk(BUSCLK),
|
||||
.m_axi_aresetn(resetn),
|
||||
.m_axi_awid(BUS_axi_awid),
|
||||
.m_axi_awlen(BUS_axi_awlen),
|
||||
.m_axi_awsize(BUS_axi_awsize),
|
||||
.m_axi_awburst(BUS_axi_awburst),
|
||||
.m_axi_awcache(BUS_axi_awcache),
|
||||
.m_axi_awaddr(BUS_axi_awaddr),
|
||||
.m_axi_awprot(BUS_axi_awprot),
|
||||
.m_axi_awregion(BUS_axi_awregion),
|
||||
.m_axi_awqos(BUS_axi_awqos),
|
||||
.m_axi_awvalid(BUS_axi_awvalid),
|
||||
.m_axi_awready(BUS_axi_awready),
|
||||
.m_axi_awlock(BUS_axi_awlock),
|
||||
.m_axi_wdata(BUS_axi_wdata),
|
||||
.m_axi_wstrb(BUS_axi_wstrb),
|
||||
.m_axi_wlast(BUS_axi_wlast),
|
||||
.m_axi_wvalid(BUS_axi_wvalid),
|
||||
.m_axi_wready(BUS_axi_wready),
|
||||
.m_axi_bid(BUS_axi_bid),
|
||||
.m_axi_bresp(BUS_axi_bresp),
|
||||
.m_axi_bvalid(BUS_axi_bvalid),
|
||||
.m_axi_bready(BUS_axi_bready),
|
||||
.m_axi_arid(BUS_axi_arid),
|
||||
.m_axi_arlen(BUS_axi_arlen),
|
||||
.m_axi_arsize(BUS_axi_arsize),
|
||||
.m_axi_arburst(BUS_axi_arburst),
|
||||
.m_axi_arprot(BUS_axi_arprot),
|
||||
.m_axi_arregion(BUS_axi_arregion),
|
||||
.m_axi_arqos(BUS_axi_arqos),
|
||||
.m_axi_arcache(BUS_axi_arcache),
|
||||
.m_axi_arvalid(BUS_axi_arvalid),
|
||||
.m_axi_araddr(BUS_axi_araddr),
|
||||
.m_axi_arlock(BUS_axi_arlock),
|
||||
.m_axi_arready(BUS_axi_arready),
|
||||
.m_axi_rid(BUS_axi_rid),
|
||||
.m_axi_rdata(BUS_axi_rdata),
|
||||
.m_axi_rresp(BUS_axi_rresp),
|
||||
.m_axi_rvalid(BUS_axi_rvalid),
|
||||
.m_axi_rlast(BUS_axi_rlast),
|
||||
.m_axi_rready(BUS_axi_rready));
|
||||
|
||||
// DDR3 Controller
|
||||
ddr3 ddr3
|
||||
(
|
||||
// ddr3 I/O
|
||||
.ddr3_dq(ddr3_dq),
|
||||
.ddr3_dqs_n(ddr3_dqs_n),
|
||||
.ddr3_dqs_p(ddr3_dqs_p),
|
||||
.ddr3_addr(ddr3_addr),
|
||||
.ddr3_ba(ddr3_ba),
|
||||
.ddr3_ras_n(ddr3_ras_n),
|
||||
.ddr3_cas_n(ddr3_cas_n),
|
||||
.ddr3_we_n(ddr3_we_n),
|
||||
.ddr3_reset_n(ddr3_reset_n),
|
||||
.ddr3_ck_p(ddr3_ck_p),
|
||||
.ddr3_ck_n(ddr3_ck_n),
|
||||
.ddr3_cke(ddr3_cke),
|
||||
.ddr3_cs_n(ddr3_cs_n),
|
||||
.ddr3_dm(ddr3_dm),
|
||||
.ddr3_odt(ddr3_odt),
|
||||
|
||||
.sys_clk_i(clk167),
|
||||
.clk_ref_i(clk200),
|
||||
|
||||
.ui_clk(BUSCLK),
|
||||
.ui_clk_sync_rst(ui_clk_sync_rst),
|
||||
.aresetn(resetn),
|
||||
.sys_rst(resetn), // omg. this is active low?!?!??
|
||||
.mmcm_locked(mmcm_locked),
|
||||
|
||||
.app_sr_req(1'b0), // reserved command
|
||||
.app_ref_req(1'b0), // refresh command
|
||||
.app_zq_req(1'b0), // recalibrate command
|
||||
.app_sr_active(app_sr_active), // reserved response
|
||||
.app_ref_ack(app_ref_ack), // refresh ack
|
||||
.app_zq_ack(app_zq_ack), // recalibrate ack
|
||||
|
||||
// axi
|
||||
.s_axi_awid(BUS_axi_awid),
|
||||
.s_axi_awaddr(BUS_axi_awaddr[29:0]),
|
||||
.s_axi_awlen(BUS_axi_awlen),
|
||||
.s_axi_awsize(BUS_axi_awsize),
|
||||
.s_axi_awburst(BUS_axi_awburst),
|
||||
.s_axi_awlock(BUS_axi_awlock),
|
||||
.s_axi_awcache(BUS_axi_awcache),
|
||||
.s_axi_awprot(BUS_axi_awprot),
|
||||
.s_axi_awqos(BUS_axi_awqos),
|
||||
.s_axi_awvalid(BUS_axi_awvalid),
|
||||
.s_axi_awready(BUS_axi_awready),
|
||||
.s_axi_wdata(BUS_axi_wdata),
|
||||
.s_axi_wstrb(BUS_axi_wstrb),
|
||||
.s_axi_wlast(BUS_axi_wlast),
|
||||
.s_axi_wvalid(BUS_axi_wvalid),
|
||||
.s_axi_wready(BUS_axi_wready),
|
||||
.s_axi_bready(BUS_axi_bready),
|
||||
.s_axi_bid(BUS_axi_bid),
|
||||
.s_axi_bresp(BUS_axi_bresp),
|
||||
.s_axi_bvalid(BUS_axi_bvalid),
|
||||
.s_axi_arid(BUS_axi_arid),
|
||||
.s_axi_araddr(BUS_axi_araddr[29:0]),
|
||||
.s_axi_arlen(BUS_axi_arlen),
|
||||
.s_axi_arsize(BUS_axi_arsize),
|
||||
.s_axi_arburst(BUS_axi_arburst),
|
||||
.s_axi_arlock(BUS_axi_arlock),
|
||||
.s_axi_arcache(BUS_axi_arcache),
|
||||
.s_axi_arprot(BUS_axi_arprot),
|
||||
.s_axi_arqos(BUS_axi_arqos),
|
||||
.s_axi_arvalid(BUS_axi_arvalid),
|
||||
.s_axi_arready(BUS_axi_arready),
|
||||
.s_axi_rready(BUS_axi_rready),
|
||||
.s_axi_rlast(BUS_axi_rlast),
|
||||
.s_axi_rvalid(BUS_axi_rvalid),
|
||||
.s_axi_rresp(BUS_axi_rresp),
|
||||
.s_axi_rid(BUS_axi_rid),
|
||||
.s_axi_rdata(BUS_axi_rdata),
|
||||
|
||||
.init_calib_complete(c0_init_calib_complete),
|
||||
.device_temp(device_temp));
|
||||
|
||||
(* mark_debug = "true" *) logic IlaTrigger;
|
||||
|
||||
|
||||
if(RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
|
||||
localparam MAX_CSRS = 3;
|
||||
localparam TOTAL_CSRS = 36;
|
||||
localparam [31:0] RVVI_INIT_TIME_OUT = 32'd100000000;
|
||||
localparam [31:0] RVVI_PACKET_DELAY = 32'd400;
|
||||
|
||||
// pipeline controls
|
||||
logic StallE, StallM, StallW, FlushE, FlushM, FlushW;
|
||||
// required
|
||||
logic [P.XLEN-1:0] PCM;
|
||||
logic InstrValidM;
|
||||
logic [31:0] InstrRawD;
|
||||
logic [63:0] Mcycle, Minstret;
|
||||
logic TrapM;
|
||||
logic [1:0] PrivilegeModeW;
|
||||
// registers gpr and fpr
|
||||
logic GPRWen, FPRWen;
|
||||
logic [4:0] GPRAddr, FPRAddr;
|
||||
logic [P.XLEN-1:0] GPRValue, FPRValue;
|
||||
logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0];
|
||||
|
||||
logic valid;
|
||||
logic [72+(5*P.XLEN) + MAX_CSRS*(P.XLEN+16)-1:0] rvvi;
|
||||
|
||||
assign StallE = fpgaTop.wallypipelinedsoc.core.StallE;
|
||||
assign StallM = fpgaTop.wallypipelinedsoc.core.StallM;
|
||||
assign StallW = fpgaTop.wallypipelinedsoc.core.StallW;
|
||||
assign FlushE = fpgaTop.wallypipelinedsoc.core.FlushE;
|
||||
assign FlushM = fpgaTop.wallypipelinedsoc.core.FlushM;
|
||||
assign FlushW = fpgaTop.wallypipelinedsoc.core.FlushW;
|
||||
assign InstrValidM = fpgaTop.wallypipelinedsoc.core.ieu.InstrValidM;
|
||||
assign InstrRawD = fpgaTop.wallypipelinedsoc.core.ifu.InstrRawD;
|
||||
assign PCM = fpgaTop.wallypipelinedsoc.core.ifu.PCM;
|
||||
assign Mcycle = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
|
||||
assign Minstret = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
|
||||
assign TrapM = fpgaTop.wallypipelinedsoc.core.TrapM;
|
||||
assign PrivilegeModeW = fpgaTop.wallypipelinedsoc.core.priv.priv.privmode.PrivilegeModeW;
|
||||
assign GPRAddr = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.a3;
|
||||
assign GPRWen = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.we3;
|
||||
assign GPRValue = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.wd3;
|
||||
assign FPRAddr = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.a4;
|
||||
assign FPRWen = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.we4;
|
||||
assign FPRValue = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.wd4;
|
||||
|
||||
assign CSRArray[0] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
|
||||
assign CSRArray[1] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
|
||||
assign CSRArray[2] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
|
||||
assign CSRArray[3] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
|
||||
assign CSRArray[4] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
|
||||
assign CSRArray[5] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
|
||||
assign CSRArray[6] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
|
||||
assign CSRArray[7] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
|
||||
assign CSRArray[8] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
|
||||
assign CSRArray[9] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
|
||||
assign CSRArray[10] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
|
||||
assign CSRArray[11] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
|
||||
assign CSRArray[12] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
|
||||
assign CSRArray[13] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
|
||||
assign CSRArray[14] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
|
||||
assign CSRArray[15] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
|
||||
assign CSRArray[16] = 0; // 12'hF11
|
||||
assign CSRArray[17] = 0; // 12'hF12
|
||||
assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
|
||||
assign CSRArray[19] = 0; // 12'hF15
|
||||
assign CSRArray[20] = 0; // 12'h34A
|
||||
// supervisor CSRs
|
||||
assign CSRArray[21] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
|
||||
assign CSRArray[22] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
|
||||
assign CSRArray[23] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
|
||||
assign CSRArray[24] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
|
||||
assign CSRArray[25] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
|
||||
assign CSRArray[26] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
|
||||
assign CSRArray[27] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
|
||||
assign CSRArray[28] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
|
||||
assign CSRArray[29] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
|
||||
assign CSRArray[30] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
|
||||
assign CSRArray[31] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
|
||||
assign CSRArray[32] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
|
||||
// user CSRs
|
||||
assign CSRArray[33] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
|
||||
assign CSRArray[34] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
|
||||
assign CSRArray[35] = {fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW, fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
|
||||
|
||||
rvvisynth #(P, MAX_CSRS) rvvisynth(.clk(CPUCLK), .reset(bus_struct_reset), .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
|
||||
.PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM,
|
||||
.PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray,
|
||||
.valid, .rvvi);
|
||||
|
||||
// axi 4 write data channel
|
||||
logic [31:0] RvviAxiWdata;
|
||||
logic [3:0] RvviAxiWstrb;
|
||||
logic RvviAxiWlast;
|
||||
logic RvviAxiWvalid;
|
||||
logic RvviAxiWready;
|
||||
|
||||
logic [31:0] RvviAxiRdata;
|
||||
logic [3:0] RvviAxiRstrb;
|
||||
logic RvviAxiRlast;
|
||||
logic RvviAxiRvalid;
|
||||
|
||||
logic tx_error_underflow, tx_fifo_overflow, tx_fifo_bad_frame, tx_fifo_good_frame, rx_error_bad_frame;
|
||||
logic rx_error_bad_fcs, rx_fifo_overflow, rx_fifo_bad_frame, rx_fifo_good_frame;
|
||||
|
||||
packetizer #(P, MAX_CSRS, RVVI_INIT_TIME_OUT, RVVI_PACKET_DELAY) packetizer(.rvvi, .valid, .m_axi_aclk(CPUCLK), .m_axi_aresetn(~bus_struct_reset), .RVVIStall,
|
||||
.RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready);
|
||||
|
||||
eth_mac_mii_fifo #(.TARGET("XILINX"), .CLOCK_INPUT_STYLE("BUFG"), .AXIS_DATA_WIDTH(32), .TX_FIFO_DEPTH(1024)) ethernet(.rst(bus_struct_reset), .logic_clk(CPUCLK), .logic_rst(bus_struct_reset),
|
||||
.tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready),
|
||||
.tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(RvviAxiRdata),
|
||||
.rx_axis_tkeep(RvviAxiRstrb), .rx_axis_tvalid(RvviAxiRvalid), .rx_axis_tready(1'b1),
|
||||
.rx_axis_tlast(RvviAxiRlast), .rx_axis_tuser(),
|
||||
|
||||
.mii_rx_clk(phy_rx_clk),
|
||||
.mii_rxd(phy_rxd),
|
||||
.mii_rx_dv(phy_rx_dv),
|
||||
.mii_rx_er(phy_rx_er),
|
||||
.mii_tx_clk(phy_tx_clk),
|
||||
.mii_txd(phy_txd),
|
||||
.mii_tx_en(phy_tx_en),
|
||||
.mii_tx_er(),
|
||||
|
||||
// status
|
||||
.tx_error_underflow, .tx_fifo_overflow, .tx_fifo_bad_frame, .tx_fifo_good_frame, .rx_error_bad_frame,
|
||||
.rx_error_bad_fcs, .rx_fifo_overflow, .rx_fifo_bad_frame, .rx_fifo_good_frame,
|
||||
.cfg_ifg(8'd12), .cfg_tx_enable(1'b1), .cfg_rx_enable(1'b1)
|
||||
);
|
||||
|
||||
triggergen triggergen(.clk(CPUCLK), .reset(bus_struct_reset), .RvviAxiRdata,
|
||||
.RvviAxiRstrb, .RvviAxiRlast, .RvviAxiRvalid, .IlaTrigger);
|
||||
end else begin // if (P.RVVI_SYNTH_SUPPORTED)
|
||||
assign IlaTrigger = '0;
|
||||
assign RVVIStall = '0;
|
||||
end
|
||||
|
||||
//assign phy_reset_n = ~bus_struct_reset;
|
||||
//assign phy_reset_n = ~1'b0;
|
||||
|
||||
endmodule
|
||||
|
||||
118
linux/devicetree/wally-genesys2.dts
Normal file
118
linux/devicetree/wally-genesys2.dts
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <0x02>;
|
||||
#size-cells = <0x02>;
|
||||
compatible = "wally-virt";
|
||||
model = "wally-virt,qemu";
|
||||
|
||||
chosen {
|
||||
linux,initrd-end = <0x85c43a00>;
|
||||
linux,initrd-start = <0x84200000>;
|
||||
bootargs = "root=/dev/vda ro console=ttyS0,115200 loglevel=7";
|
||||
stdout-path = "/soc/uart@10000000";
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x00 0x80000000 0x00 0x40000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0x01>;
|
||||
#size-cells = <0x00>;
|
||||
clock-frequency = <25000000>;
|
||||
timebase-frequency = <25000000>;
|
||||
|
||||
cpu@0 {
|
||||
phandle = <0x01>;
|
||||
device_type = "cpu";
|
||||
reg = <0x00>;
|
||||
status = "okay";
|
||||
compatible = "riscv";
|
||||
riscv,isa-base = "rv64i";
|
||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svade", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm";
|
||||
riscv,cboz-block-size = <64>;
|
||||
riscv,cbom-block-size = <64>;
|
||||
mmu-type = "riscv,sv48";
|
||||
|
||||
interrupt-controller {
|
||||
#interrupt-cells = <0x01>;
|
||||
interrupt-controller;
|
||||
compatible = "riscv,cpu-intc";
|
||||
phandle = <0x02>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <0x02>;
|
||||
#size-cells = <0x02>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
refclk: refclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
clock-output-names = "xtal";
|
||||
};
|
||||
|
||||
gpio0: gpio@10060000 {
|
||||
compatible = "sifive,gpio0";
|
||||
interrupt-parent = <0x03>;
|
||||
interrupts = <3>;
|
||||
reg = <0x00 0x10060000 0x00 0x1000>;
|
||||
reg-names = "control";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
uart@10000000 {
|
||||
interrupts = <0x0a>;
|
||||
interrupt-parent = <0x03>;
|
||||
clock-frequency = <25000000>;
|
||||
reg = <0x00 0x10000000 0x00 0x100>;
|
||||
compatible = "ns16550a";
|
||||
};
|
||||
|
||||
plic@c000000 {
|
||||
phandle = <0x03>;
|
||||
riscv,ndev = <0x35>;
|
||||
reg = <0x00 0xc000000 0x00 0x210000>;
|
||||
interrupts-extended = <0x02 0x0b 0x02 0x09>;
|
||||
interrupt-controller;
|
||||
compatible = "sifive,plic-1.0.0\0riscv,plic0";
|
||||
#interrupt-cells = <0x01>;
|
||||
#address-cells = <0x00>;
|
||||
};
|
||||
|
||||
spi@13000 {
|
||||
compatible = "sifive,spi0";
|
||||
interrupt-parent = <0x03>;
|
||||
interrupts = <0x14>;
|
||||
reg = <0x0 0x13000 0x0 0x1000>;
|
||||
reg-names = "control";
|
||||
clocks = <&refclk>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mmc@0 {
|
||||
compatible = "mmc-spi-slot";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
voltage-ranges = <3300 3300>;
|
||||
disable-wp;
|
||||
// gpios = <&gpio0 6 1>;
|
||||
};
|
||||
};
|
||||
|
||||
clint@2000000 {
|
||||
interrupts-extended = <0x02 0x03 0x02 0x07>;
|
||||
reg = <0x00 0x2000000 0x00 0x10000>;
|
||||
compatible = "sifive,clint0\0riscv,clint0";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue