Merge pull request #1404 from rosethompson/main

Fixes two bugs with Issue #1263

fpga/constraints/debug6.xdc

@@ -1,5 +1,8 @@
 create_debug_core u_ila_0 ila
 
+
+
+
 set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
 set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
 set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
@@ -14,7 +17,8 @@ set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
 set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
 set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
 endgroup
-connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
+connect_debug_port u_ila_0/clk [get_nets CPUCLK]
+
 set_property port_width 64 [get_debug_ports u_ila_0/probe0]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
 connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/core/lsu/LSUHWDATA[0]} {wallypipelinedsoc/core/lsu/LSUHWDATA[1]} {wallypipelinedsoc/core/lsu/LSUHWDATA[2]} {wallypipelinedsoc/core/lsu/LSUHWDATA[3]} {wallypipelinedsoc/core/lsu/LSUHWDATA[4]} {wallypipelinedsoc/core/lsu/LSUHWDATA[5]} {wallypipelinedsoc/core/lsu/LSUHWDATA[6]} {wallypipelinedsoc/core/lsu/LSUHWDATA[7]} {wallypipelinedsoc/core/lsu/LSUHWDATA[8]} {wallypipelinedsoc/core/lsu/LSUHWDATA[9]} {wallypipelinedsoc/core/lsu/LSUHWDATA[10]} {wallypipelinedsoc/core/lsu/LSUHWDATA[11]} {wallypipelinedsoc/core/lsu/LSUHWDATA[12]} {wallypipelinedsoc/core/lsu/LSUHWDATA[13]} {wallypipelinedsoc/core/lsu/LSUHWDATA[14]} {wallypipelinedsoc/core/lsu/LSUHWDATA[15]} {wallypipelinedsoc/core/lsu/LSUHWDATA[16]} {wallypipelinedsoc/core/lsu/LSUHWDATA[17]} {wallypipelinedsoc/core/lsu/LSUHWDATA[18]} {wallypipelinedsoc/core/lsu/LSUHWDATA[19]} {wallypipelinedsoc/core/lsu/LSUHWDATA[20]} {wallypipelinedsoc/core/lsu/LSUHWDATA[21]} {wallypipelinedsoc/core/lsu/LSUHWDATA[22]} {wallypipelinedsoc/core/lsu/LSUHWDATA[23]} {wallypipelinedsoc/core/lsu/LSUHWDATA[24]} {wallypipelinedsoc/core/lsu/LSUHWDATA[25]} {wallypipelinedsoc/core/lsu/LSUHWDATA[26]} {wallypipelinedsoc/core/lsu/LSUHWDATA[27]} {wallypipelinedsoc/core/lsu/LSUHWDATA[28]} {wallypipelinedsoc/core/lsu/LSUHWDATA[29]} {wallypipelinedsoc/core/lsu/LSUHWDATA[30]} {wallypipelinedsoc/core/lsu/LSUHWDATA[31]} {wallypipelinedsoc/core/lsu/LSUHWDATA[32]} {wallypipelinedsoc/core/lsu/LSUHWDATA[33]} {wallypipelinedsoc/core/lsu/LSUHWDATA[34]} {wallypipelinedsoc/core/lsu/LSUHWDATA[35]} {wallypipelinedsoc/core/lsu/LSUHWDATA[36]} {wallypipelinedsoc/core/lsu/LSUHWDATA[37]} {wallypipelinedsoc/core/lsu/LSUHWDATA[38]} {wallypipelinedsoc/core/lsu/LSUHWDATA[39]} {wallypipelinedsoc/core/lsu/LSUHWDATA[40]} {wallypipelinedsoc/core/lsu/LSUHWDATA[41]} {wallypipelinedsoc/core/lsu/LSUHWDATA[42]} {wallypipelinedsoc/core/lsu/LSUHWDATA[43]} {wallypipelinedsoc/core/lsu/LSUHWDATA[44]} {wallypipelinedsoc/core/lsu/LSUHWDATA[45]} {wallypipelinedsoc/core/lsu/LSUHWDATA[46]} {wallypipelinedsoc/core/lsu/LSUHWDATA[47]} {wallypipelinedsoc/core/lsu/LSUHWDATA[48]} {wallypipelinedsoc/core/lsu/LSUHWDATA[49]} {wallypipelinedsoc/core/lsu/LSUHWDATA[50]} {wallypipelinedsoc/core/lsu/LSUHWDATA[51]} {wallypipelinedsoc/core/lsu/LSUHWDATA[52]} {wallypipelinedsoc/core/lsu/LSUHWDATA[53]} {wallypipelinedsoc/core/lsu/LSUHWDATA[54]} {wallypipelinedsoc/core/lsu/LSUHWDATA[55]} {wallypipelinedsoc/core/lsu/LSUHWDATA[56]} {wallypipelinedsoc/core/lsu/LSUHWDATA[57]} {wallypipelinedsoc/core/lsu/LSUHWDATA[58]} {wallypipelinedsoc/core/lsu/LSUHWDATA[59]} {wallypipelinedsoc/core/lsu/LSUHWDATA[60]} {wallypipelinedsoc/core/lsu/LSUHWDATA[61]} {wallypipelinedsoc/core/lsu/LSUHWDATA[62]} {wallypipelinedsoc/core/lsu/LSUHWDATA[63]} ]]
@@ -366,7 +370,7 @@ connect_debug_port u_ila_0/probe69 [get_nets [list {wallypipelinedsoc/core/priv.
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe70]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
-connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissF]]
+connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/core/lsu/ITLBMissOrUpdateAF]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe71]
@@ -547,3 +551,19 @@ create_debug_port u_ila_0 probe
 set_property port_width 48 [get_debug_ports u_ila_0/probe105]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105]
 connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[0]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[1]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[2]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[3]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[4]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[5]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[6]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[7]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[8]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[9]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[10]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[11]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[12]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[13]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[14]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[15]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[16]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[17]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[18]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[19]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[20]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[21]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[22]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[23]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[24]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[25]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[26]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[27]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[28]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[29]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[30]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[31]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[32]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[33]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[34]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[35]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[36]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[37]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[38]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[39]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[40]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[41]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[42]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[43]}  {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[60]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[61]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[62]} {wallypipelinedsoc/core/lsu/hptw.hptw/SATP_REGW[63]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe106]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106]
+connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/core/ieu/dp/ALUResultE[0]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[1]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[2]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[3]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[4]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[5]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[6]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[7]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[8]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[9]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[10]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[11]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[12]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[13]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[14]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[15]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[16]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[17]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[18]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[19]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[20]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[21]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[22]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[23]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[24]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[25]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[26]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[27]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[28]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[29]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[30]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[31]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[32]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[33]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[34]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[35]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[36]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[37]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[38]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[39]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[40]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[41]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[42]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[43]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[44]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[45]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[46]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[47]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[48]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[49]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[50]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[51]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[52]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[53]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[54]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[55]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[56]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[57]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[58]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[59]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[60]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[61]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[62]} {wallypipelinedsoc/core/ieu/dp/ALUResultE[63]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 56 [get_debug_ports u_ila_0/probe107]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107]
+connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/core/lsu/PAdrM[0]} {wallypipelinedsoc/core/lsu/PAdrM[1]} {wallypipelinedsoc/core/lsu/PAdrM[2]} {wallypipelinedsoc/core/lsu/PAdrM[3]} {wallypipelinedsoc/core/lsu/PAdrM[4]} {wallypipelinedsoc/core/lsu/PAdrM[5]} {wallypipelinedsoc/core/lsu/PAdrM[6]} {wallypipelinedsoc/core/lsu/PAdrM[7]} {wallypipelinedsoc/core/lsu/PAdrM[8]} {wallypipelinedsoc/core/lsu/PAdrM[9]} {wallypipelinedsoc/core/lsu/PAdrM[10]} {wallypipelinedsoc/core/lsu/PAdrM[11]} {wallypipelinedsoc/core/lsu/PAdrM[12]} {wallypipelinedsoc/core/lsu/PAdrM[13]} {wallypipelinedsoc/core/lsu/PAdrM[14]} {wallypipelinedsoc/core/lsu/PAdrM[15]} {wallypipelinedsoc/core/lsu/PAdrM[16]} {wallypipelinedsoc/core/lsu/PAdrM[17]} {wallypipelinedsoc/core/lsu/PAdrM[18]} {wallypipelinedsoc/core/lsu/PAdrM[19]} {wallypipelinedsoc/core/lsu/PAdrM[20]} {wallypipelinedsoc/core/lsu/PAdrM[21]} {wallypipelinedsoc/core/lsu/PAdrM[22]} {wallypipelinedsoc/core/lsu/PAdrM[23]} {wallypipelinedsoc/core/lsu/PAdrM[24]} {wallypipelinedsoc/core/lsu/PAdrM[25]} {wallypipelinedsoc/core/lsu/PAdrM[26]} {wallypipelinedsoc/core/lsu/PAdrM[27]} {wallypipelinedsoc/core/lsu/PAdrM[28]} {wallypipelinedsoc/core/lsu/PAdrM[29]} {wallypipelinedsoc/core/lsu/PAdrM[30]} {wallypipelinedsoc/core/lsu/PAdrM[31]} {wallypipelinedsoc/core/lsu/PAdrM[32]} {wallypipelinedsoc/core/lsu/PAdrM[33]} {wallypipelinedsoc/core/lsu/PAdrM[34]} {wallypipelinedsoc/core/lsu/PAdrM[35]} {wallypipelinedsoc/core/lsu/PAdrM[36]} {wallypipelinedsoc/core/lsu/PAdrM[37]} {wallypipelinedsoc/core/lsu/PAdrM[38]} {wallypipelinedsoc/core/lsu/PAdrM[39]} {wallypipelinedsoc/core/lsu/PAdrM[40]} {wallypipelinedsoc/core/lsu/PAdrM[41]} {wallypipelinedsoc/core/lsu/PAdrM[42]} {wallypipelinedsoc/core/lsu/PAdrM[43]} {wallypipelinedsoc/core/lsu/PAdrM[44]} {wallypipelinedsoc/core/lsu/PAdrM[45]} {wallypipelinedsoc/core/lsu/PAdrM[46]} {wallypipelinedsoc/core/lsu/PAdrM[47]} {wallypipelinedsoc/core/lsu/PAdrM[48]} {wallypipelinedsoc/core/lsu/PAdrM[49]} {wallypipelinedsoc/core/lsu/PAdrM[50]} {wallypipelinedsoc/core/lsu/PAdrM[51]} {wallypipelinedsoc/core/lsu/PAdrM[52]} {wallypipelinedsoc/core/lsu/PAdrM[53]} {wallypipelinedsoc/core/lsu/PAdrM[54]} {wallypipelinedsoc/core/lsu/PAdrM[55]}  ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe108]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108]
+connect_debug_port u_ila_0/probe108 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/MENVCFG_REGW[63]} ]]

fpga/constraints/marked_debug_debug6.txt

@@ -0,0 +1,135 @@
+lsu/lsu.sv: logic      IEUAdrM
+lsu/lsu.sv: logic      PAdrM
+lsu/lsu.sv: logic      WriteDataM
+lsu/lsu.sv: logic        LSUHADDR
+lsu/lsu.sv: logic        HRDATA
+lsu/lsu.sv: logic        LSUHWDATA
+lsu/lsu.sv: logic       LSUHREADY
+lsu/lsu.sv: logic       LSUHWRITE
+lsu/lsu.sv: logic        LSUHSIZE
+lsu/lsu.sv: logic        LSUHBURST
+lsu/lsu.sv: logic        LSUHTRANS
+lsu/lsu.sv: logic        LSUHWSTRB
+lsu/lsu.sv: logic      IHAdrM
+ieu/regfile.sv: logic    rf
+ieu/datapath.sv: logic                 RegWriteW
+hazard/hazard.sv: logic	         BPPredWrongE
+hazard/hazard.sv: logic	         LoadStallD
+hazard/hazard.sv: logic          FCvtIntStallD
+hazard/hazard.sv: logic	         DivBusyE
+hazard/hazard.sv: logic	         EcallFaultM
+hazard/hazard.sv: logic          WFIStallM
+hazard/hazard.sv: logic	        StallF
+hazard/hazard.sv: logic	        FlushD
+cache/cachefsm.sv:   statetype CurrState
+wally/wallypipelinedcore.sv: logic    TrapM
+wally/wallypipelinedcore.sv: logic            SrcAM
+wally/wallypipelinedcore.sv: logic                 InstrM
+wally/wallypipelinedcore.sv: logic             PCM
+wally/wallypipelinedcore.sv: logic           MemRWM
+wally/wallypipelinedcore.sv: logic                InstrValidM
+wally/wallypipelinedcore.sv: logic     WriteDataM
+wally/wallypipelinedcore.sv: logic     IEUAdrM
+ieu/datapath.sv: logic     ALUResultE
+wally/wallypipelinedcore.sv: logic   HRDATA
+ifu/spill.sv:    statetype CurrState
+ifu/ifu.sv: logic    				IFUStallF
+ifu/ifu.sv: logic     IFUHADDR
+ifu/ifu.sv: logic     	HRDATA
+ifu/ifu.sv: logic      IFUHREADY
+ifu/ifu.sv: logic     IFUHWRITE
+ifu/ifu.sv: logic      IFUHSIZE
+ifu/ifu.sv: logic      IFUHBURST
+ifu/ifu.sv: logic      IFUHTRANS
+ifu/ifu.sv: logic     PCF
+ifu/ifu.sv: logic                 PCNextF
+ifu/ifu.sv: logic            PCPF
+ifu/ifu.sv: logic     PostSpillInstrRawF
+mmu/hptw.sv: logic	   ITLBMissOrUpdateAF
+mmu/hptw.sv:	 statetype WalkerState
+mmu/hptw.sv: logic  ValidPTE
+privileged/csrs.sv: logic        CSRSReadValM
+privileged/csrs.sv: logic        SEPC_REGW
+privileged/csrs.sv: logic        MIP_REGW
+privileged/csrs.sv: logic      SSCRATCH_REGW
+privileged/csrs.sv: logic     SCAUSE_REGW      
+privileged/csr.sv: logic    CSRReadValM  
+privileged/csr.sv: logic    CSRSrcM
+privileged/csr.sv: logic    CSRWriteValM
+privileged/csr.sv: logic    MSTATUS_REGW
+privileged/trap.sv: logic      		   InstrMisalignedFaultM
+privileged/trap.sv: logic      		   BreakpointFaultM
+privileged/trap.sv: logic      		   LoadAccessFaultM
+privileged/trap.sv: logic      		   LoadPageFaultM
+privileged/trap.sv: logic      		   mretM
+privileged/trap.sv: logic      MIP_REGW
+privileged/trap.sv: logic           PendingIntsM
+privileged/privileged.sv: logic      CSRReadM
+privileged/csr.sv: logic      MENVCFG_REGW
+privileged/privileged.sv: logic    InterruptM
+privileged/csrc.sv: logic      HPMCOUNTER_REGW
+privileged/csri.sv: logic       MExtInt
+privileged/csri.sv: logic        MIP_REGW_writeabl
+privileged/csrm.sv: logic        	     MIP_REGW
+privileged/csrm.sv: logic       MEPC_REGW
+privileged/csrm.sv: logic     MEDELEG_REGW
+privileged/csrm.sv: logic          MIDELEG_REGW
+privileged/csrm.sv: logic      MSCRATCH_REGW
+privileged/csrm.sv: logic       MCAUSE_REGW
+uncore/uart_apb.sv: logic                  SIN
+uncore/uart_apb.sv: logic                 SOUT
+uncore/uart_apb.sv: logic                 OUT1b
+uncore/uartPC16550D.sv: logic       RBR
+uncore/uartPC16550D.sv: logic        FCR
+uncore/uartPC16550D.sv: logic        IER
+uncore/uartPC16550D.sv: logic        MCR
+uncore/uartPC16550D.sv: logic    	   baudpulse
+uncore/uartPC16550D.sv:     statetype rxstate
+uncore/uartPC16550D.sv: logic     					rxfifo
+uncore/uartPC16550D.sv: logic     					txfifo
+uncore/uartPC16550D.sv: logic    					rxfifohead
+uncore/uartPC16550D.sv: logic    					rxfifoentries
+uncore/uartPC16550D.sv: logic       					RXBR
+uncore/uartPC16550D.sv: logic     					rxtimeoutcnt
+uncore/uartPC16550D.sv: logic      						rxparityerr
+uncore/uartPC16550D.sv: logic   						rxdataready
+uncore/uartPC16550D.sv: logic   						rxfifoempty
+uncore/uartPC16550D.sv: logic     					rxdata
+uncore/uartPC16550D.sv: logic     					RXerrbit
+uncore/uartPC16550D.sv: logic     					rxfullbitunwrapped
+uncore/uartPC16550D.sv: logic     					txdata
+uncore/uartPC16550D.sv: logic    						txnextbit
+uncore/uartPC16550D.sv: logic    						txfifoempty
+uncore/uartPC16550D.sv: logic   						fifoenabled
+uncore/uartPC16550D.sv: logic   						RXerr
+uncore/uartPC16550D.sv: logic   						THRE
+uncore/uartPC16550D.sv: logic   						rxdataavailintr
+uncore/uartPC16550D.sv: logic    					intrID
+uncore/uncore.sv: logic HSELEXTSDCD
+uncore/plic_apb.sv: logic                    MExtInt
+uncore/plic_apb.sv: logic     Din
+uncore/plic_apb.sv: logic             requests
+uncore/plic_apb.sv: logic        intPriority
+uncore/plic_apb.sv: logic             intInProgress
+uncore/plic_apb.sv: logic           intThreshold
+uncore/plic_apb.sv: logic             intEn
+uncore/plic_apb.sv: logic           intClaim
+uncore/plic_apb.sv: logic        irqMatrix
+uncore/plic_apb.sv: logic           priorities_with_irqs
+uncore/plic_apb.sv: logic           max_priority_with_irqs
+uncore/plic_apb.sv: logic          irqs_at_max_priority
+uncore/plic_apb.sv: logic           threshMask
+uncore/clint_apb.sv: logic      MTIME
+uncore/clint_apb.sv: logic         MTIMECMP
+ebu/ebu.sv: logic     HCLK
+ebu/ebu.sv: logic      HREADY
+ebu/ebu.sv: logic      HRESP
+ebu/ebu.sv: logic      HADDR
+ebu/ebu.sv: logic     HWRITE
+ebu/ebu.sv: logic      HSIZE
+ebu/ebu.sv: logic      HBURST
+ebu/ebu.sv: logic      HPROT
+ebu/ebu.sv: logic      HTRANS
+ebu/ebu.sv: logic     HMASTLOC
+ebu/buscachefsm.sv:   busstatetype CurrState
+ebu/busfsm.sv:   busstatetype CurrState

src/lsu/align.sv

@@ -52,6 +52,7 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
   output logic [P.XLEN-1:0]       IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill
   output logic [P.XLEN-1:0]       IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill
+  output logic [P.XLEN-1:0]       IEUAdrxTvalM, // IEUAdrM or spilled and aligned to next page
   output logic                    SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline
   output logic [P.LLEN-1:0]       DCacheReadDataWordSpillM, // The final 32 bit instruction after merging the two spilled fetches into 1 instruction
   output logic                    SpillStallM);
@@ -80,10 +81,13 @@ module align import cvw::*;  #(parameter cvw_t P) (
 
 
   /* verilator lint_off WIDTHEXPAND */
+  //assign IEUAdrIncrementM = {IEUAdrM[P.XLEN-1:OFFSET_LEN], {{OFFSET_LEN}{1'b0}}} + LLENINBYTES;
   assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
   /* verilator lint_on WIDTHEXPAND */
   mux2 #(P.XLEN) ieuadrspillemux(.d0(IEUAdrE), .d1(IEUAdrIncrementM), .s(SelSpillE), .y(IEUAdrSpillE));
   mux2 #(P.XLEN) ieuadrspillmmux(.d0(IEUAdrM), .d1(IEUAdrIncrementM), .s(SelSpillM), .y(IEUAdrSpillM));
+  //assign IEUAdrxTvalM = {IEUAdrSpillM[P.XLEN-1:OFFSET_LEN], {{OFFSET_LEN}{1'b0}}};
+  mux2 #(P.XLEN) ieuadrxtvalmmux(.d0(IEUAdrM), .d1({IEUAdrIncrementM[P.XLEN-1:OFFSET_LEN], {{OFFSET_LEN}{1'b0}}}), .s(SelSpillM), .y(IEUAdrxTvalM));
 
   ////////////////////////////////////////////////////////////////////////////////////////////////////
   // Detect spill
@@ -148,7 +152,7 @@ module align import cvw::*;  #(parameter cvw_t P) (
   flopenr #(P.LLEN) SpillDataReg(clk, reset, SpillSaveM, DCacheReadDataWordM[P.LLEN-1:0], ReadDataWordFirstHalfM);
 
   // merge together
-  mux2 #(2*P.LLEN) postspillmux(DCacheReadDataWordM, {DCacheReadDataWordM[P.LLEN-1:0], ReadDataWordFirstHalfM}, SelSpillM, ReadDataWordSpillAllM);
+  mux2 #(2*P.LLEN) postspillmux(DCacheReadDataWordM, {DCacheReadDataWordM[P.LLEN-1:0], ReadDataWordFirstHalfM}, SelSpillM & ~SelHPTW, ReadDataWordSpillAllM);
 
 
   // shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)

src/lsu/lsu.sv

@@ -57,6 +57,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
   input  logic                    BigEndianM,                           // Swap byte order to big endian
   input  logic                    sfencevmaM,                           // Virtual memory address fence, invalidate TLB entries
   output logic                    DCacheStallM,                         // D$ busy with multicycle operation
+  output logic [P.XLEN-1:0]       IEUAdrxTvalM,                         // IEUAdrM, but could be spilled onto the next cacheline or virtual page.
   // fpu
   input  logic [P.FLEN-1:0]       FWriteDataM,                          // Write data from FPU
   input  logic                    FpLoadStoreM,                         // Selects FPU as store for write data
@@ -158,12 +159,13 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
 
   flopenrc #(P.XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
   if(MISALIGN_SUPPORT) begin : ziccslm_align
-    logic [P.XLEN-1:0] IEUAdrSpillE, IEUAdrSpillM;
+    logic [P.XLEN-1:0] IEUAdrSpillE;
+    logic [P.XLEN-1:0] IEUAdrSpillM;
     align #(P) align(.clk, .reset, .StallM, .FlushM, .IEUAdrE, .IEUAdrM, .Funct3M, .FpLoadStoreM, 
                      .MemRWM,
                      .DCacheReadDataWordM, .CacheBusHPWTStall, .SelHPTW,
                      .ByteMaskM, .ByteMaskExtendedM, .LSUWriteDataM, .ByteMaskSpillM, .LSUWriteDataSpillM,
-                     .IEUAdrSpillE, .IEUAdrSpillM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM);
+                     .IEUAdrSpillE, .IEUAdrSpillM, .IEUAdrxTvalM, .SelSpillE, .DCacheReadDataWordSpillM, .SpillStallM);
     assign IEUAdrExtM = {2'b00, IEUAdrSpillM}; 
     assign IEUAdrExtE = {2'b00, IEUAdrSpillE};
   end else begin : no_ziccslm_align
@@ -175,6 +177,7 @@ module lsu import cvw::*;  #(parameter cvw_t P) (
     assign LSUWriteDataSpillM = LSUWriteDataM;
     assign MemRWSpillM = MemRWM;
     assign {SpillStallM} = 1'b0;
+    assign IEUAdrxTvalM = IEUAdrM;
   end
 
     if(P.ZICBOZ_SUPPORTED) begin : cboz

src/privileged/csr.sv

@@ -36,7 +36,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
   input  logic [31:0]              InstrM,                    // current instruction
   input  logic [31:0]              InstrOrigM,                // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
   input  logic [P.XLEN-1:0]        PCM,                       // program counter, next PC going to trap/return logic
-  input  logic [P.XLEN-1:0]        SrcAM, IEUAdrM,            // SrcA and memory address from IEU
+  input  logic [P.XLEN-1:0]        SrcAM, IEUAdrxTvalM,       // SrcA and memory address from IEU
   input  logic                     CSRReadM, CSRWriteM,       // read or write CSR
   input  logic                     TrapM,                     // trap is occurring
   input  logic                     mretM, sretM,              // return instruction
@@ -142,7 +142,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
     else case (CauseM)
       12, 1, 3:               NextFaultMtvalM = PCM;  // Instruction page/access faults, breakpoint
       2:                      NextFaultMtvalM = {{(P.XLEN-32){1'b0}}, InstrOrigM}; // Illegal instruction fault 
-      0, 4, 6, 13, 15, 5, 7:  NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults
+      0, 4, 6, 13, 15, 5, 7:  NextFaultMtvalM = IEUAdrxTvalM; // Instruction misaligned, Load/Store Misaligned/page/access faults
       default:                NextFaultMtvalM = '0; // Ecall, interrupts
     endcase
 

src/privileged/privileged.sv

@@ -37,7 +37,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.XLEN-1:0] SrcAM,                                          // GPR register to write
   input  logic [31:0]       InstrM,                                         // Instruction
   input  logic [31:0]       InstrOrigM,                                     // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
-  input  logic [P.XLEN-1:0] IEUAdrM,                                        // address from IEU
+  input  logic [P.XLEN-1:0] IEUAdrxTvalM,                                   // address from IEU
   input  logic [P.XLEN-1:0] PCM,                                            // program counter
   // control signals                                                       
   input  logic              InstrValidM,                                    // Current instruction is valid (not flushed)
@@ -133,7 +133,7 @@ module privileged import cvw::*;  #(parameter cvw_t P) (
 
   // Control and Status Registers
   csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
-    .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, 
+    .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrxTvalM, 
     .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
     .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
     .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,

src/wally/wallypipelinedcore.sv

@@ -130,6 +130,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
   logic [P.XLEN-1:0]             IEUAdrE;
   logic [P.XLEN-1:0]             WriteDataM;
   logic [P.XLEN-1:0]             IEUAdrM;  
+  logic [P.XLEN-1:0]             IEUAdrxTvalM;  
   logic [P.LLEN-1:0]             ReadDataW;  
   logic                          CommittedM;
 
@@ -242,6 +243,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
     .ENVCFG_ADUE,                 // from csr
     .sfencevmaM,                  // connects to privilege
     .DCacheStallM,                // connects to privilege
+    .IEUAdrxTvalM,                // connects to privilege
     .LoadPageFaultM,              // connects to privilege
     .StoreAmoPageFaultM,          // connects to privilege
     .LoadMisalignedFaultM,        // connects to privilege
@@ -299,7 +301,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
       .InstrMisalignedFaultM, .IllegalIEUFPUInstrD, 
       .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
       .MTimerInt, .MExtInt, .SExtInt, .MSwInt,
-      .MTIME_CLINT, .IEUAdrM, .SetFflagsM,
+      .MTIME_CLINT, .IEUAdrxTvalM, .SetFflagsM,
       .InstrAccessFaultF, .HPTWInstrAccessFaultF, .HPTWInstrPageFaultF, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
       .PrivilegeModeW, .SATP_REGW,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, 

tests/coverage/misalignedStoreSpill.S

@@ -0,0 +1,219 @@
+///////////////////////////////////////////
+// misalignedStoreSpill.S
+//
+// Written: Rose Thompson rose@rosethompson.net 05 May 2025
+//
+// Purpose: Test coverage for EBU
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// https://github.com/openhwgroup/cvw
+//
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
+// either express or implied. See the License for the specific language governing permissions
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    li t5, 0x1
+    slli t5, t5, 62
+    ori t5, t5, 0xF0
+    csrs menvcfg, t5  # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1
+
+    # Page table root address at 0x80010000; SV48
+    li t5, 0x9000000000080010
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1
+    ecall
+
+
+
+    li a0, 0x80000fff
+    j label1
+
+.align  6   # start on multiple of 64 bytes / 16 instruction cache line
+label1:
+        # test 1
+    li t0, 0xdeadbeef01234567
+    sfence.vma          # flush tlb
+    sd t0, 0x0(a0)        # load to get an entry in the DTLB accessing top-level PTE
+
+        # test 2
+    li a1, 4096
+    add a0, a0, a1
+    sd t0, 0(a0)        # cause a store page fault to the second half of the access. mtval should be updated to the address of the second half.
+
+    # wrap up
+    li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
+    ecall
+    j done
+
+
+.data
+
+.align 16
+# root Page table situated at 0x80010000
+pagetable:
+    .8byte 0x20004401  # 0x00000000-0x80_00000000: PTE at 0x80011000 01 valid
+    .8byte 0x000000000000100F # misaligned terapage at 0x80_00000000
+
+# next page table at 0x80011000
+.align 12
+    .8byte 0x000000000000100F # misaligned gigapage at 0x00000000
+    .8byte 0x0000000020005801 # PTE for pages at 0x40000000
+    .8byte 0x0000000020004801 #  
+
+
+# Next page table at 0x80012000 for gigapage at 0x80000000
+.align 12
+    .8byte 0x0000000020004C01  # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages)
+    .8byte 0x0000000020014C0F  # for VA starting at 80200000 (misaligned megapage)
+    .8byte 0x0000000020005001  # for VA starting at 80400000 (bad PBMT pages)
+    .8byte 0x4000000020004C01  # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
+    .8byte 0x0000000020005401  # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz)
+    .8byte 0x0000000020005801  # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000)
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+    .8byte 0x0000000020004C01
+
+# Leaf page table at 0x80013000 with NAPOT pages
+.align 12
+    #80000000
+    .8byte 0x00000000200020CF
+    .8byte 0x00000000200020CF
+    .8byte 0x0000000000000000 # this is in invalid so that the second half of the access causes a fault
+    .8byte 0x00000000200020CF
+
+    .8byte 0x00000000200020CF
+    .8byte 0x00000000200020CF
+    .8byte 0x00000000200020CF
+    .8byte 0x00000000200020CF
+
+    .8byte 0x00000000200020CF
+    .8byte 0x00000000200020CF
+    .8byte 0x00000000200020CF
+    .8byte 0x00000000200020CF
+
+    .8byte 0x00000000200020CF
+    .8byte 0x00000000200020CF
+    .8byte 0x00000000200020CF
+    .8byte 0x00000000200020CF
+
+    .8byte 0x80000000200060CF
+    .8byte 0x80000000200060CF
+    .8byte 0x80000000200060CF
+    .8byte 0x80000000200060CF
+
+    .8byte 0x80000000200060CF    # A
+    .8byte 0x80000000200060CF
+    .8byte 0x80000000200060CF
+    .8byte 0x80000000200060CF
+
+    .8byte 0x80000000200060CF
+    .8byte 0x80000000200060CF
+    .8byte 0x80000000200060CF
+    .8byte 0x80000000200060CF
+
+    .8byte 0x80000000200060CF   # e0
+    .8byte 0x00000000200060CF   # e8
+    .8byte 0x80000000200060CF
+    .8byte 0x80000000200060CF
+
+    .8byte 0x800000002000A0CF
+    .8byte 0x800000002000A0CF
+    .8byte 0x800000002000A0CF
+    .8byte 0x800000002000A0CF
+
+    .8byte 0x800000002000A0CF
+    .8byte 0x800000002000A0CF
+    .8byte 0x800000002000A0CF
+    .8byte 0x800000002000A0CF
+
+    .8byte 0x800000002000A0CF
+    .8byte 0x800000002000A0CF
+    .8byte 0x800000002000A0CF
+    .8byte 0x800000002000A0CF
+
+    .8byte 0x800000002000A0CF
+    .8byte 0x800000002000A0CF
+    .8byte 0x800000002000A0CF
+    .8byte 0x800000002000A0CF
+
+    .8byte 0x800000002000E0CF
+    .8byte 0x800000002000E0CF
+    .8byte 0x800000002000E0CF
+    .8byte 0x800000002000E0CF
+
+    .8byte 0x800000002000E0CF
+    .8byte 0x800000002000E0CF
+
+# Leaf page table at 0x80014000 with PBMT pages
+.align 12
+    #80400000
+    .8byte 0x60000000200020CF   # reserved entry
+
+# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ
+.align 12
+    #80800000
+    .8byte 0x00000000200000CF   # valid rwx for VA 80800000
+    .8byte 0x00000000200000CB   # valid r x for VA 80801000
+    .8byte 0x00000000200000C3   # valid r   for VA 80802000
+    .8byte 0x00000000200000C9   # valid   x for VA 80803000
+    .8byte 0x00000000200000CD   # valid  wx for VA 80804000 (illegal combination, but used to test tlbcontrol)
+    .8byte 0x000000002000000F   # valid rwx for VA 80805000  for covering ITLB translate and UpdateDA
+    .8byte 0x20000000200000CF   # PBMT=1    for VA 80806000  for covering ITLB BadPBMT
+
+# Leaf page table at 0x80016000 with NAPOT pages
+.align 12
+    .8byte 0xA0000000200020CF
+    .8byte 0xA0000000200020CF
+    .8byte 0xA0000000200020CF
+    .8byte 0xA0000000200020CF