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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev

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This commit is contained in:
David Harris 2023-06-06 08:46:54 -07:00
commit 25fef1c38c
19 changed files with 59 additions and 48 deletions
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2
benchmarks/coremark/Makefile
View file

@ -4,7 +4,7 @@
PORT_DIR = $(CURDIR)/riscv64-baremetal
cmbase=../../addins/coremark
work_dir= ../benchmarks/coremark/work
work_dir= work
XLEN ?=64
sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
$(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \

2
config/shared/BranchPredictorType.vh
View file

@ -1,3 +1,3 @@
typedef enum {BP_TWOBIT, BP_GSHARE, BP_GLOBAL, BP_GSHARE_BASIC,
typedef enum logic[3:0] {BP_TWOBIT, BP_GSHARE, BP_GLOBAL, BP_GSHARE_BASIC,
BP_GLOBAL_BASIC, BP_LOCAL_BASIC, BP_LOCAL_AHEAD, BP_LOCAL_REPAIR} BranchPredictorType;

4
config/shared/parameter-defs.vh
View file

@ -72,7 +72,11 @@ parameter cvw_t P = '{
PLIC_GPIO_ID : PLIC_GPIO_ID,
PLIC_UART_ID : PLIC_UART_ID,
BPRED_SUPPORTED : BPRED_SUPPORTED,
/* verilator lint_off ENUMVALUE */
// *** definitely need to fix this.
// it thinks we are casting from the enum type to BPRED_TYPE.
BPRED_TYPE : BPRED_TYPE,
/* verilator lint_off ENUMVALUE */
BPRED_SIZE : BPRED_SIZE,
BPRED_NUM_LHR : BPRED_NUM_LHR,
BTB_SIZE : BTB_SIZE,

2
sim/lint-wally
View file

@ -8,7 +8,7 @@ basepath=$(dirname $0)/..
for config in rv32e rv64gc rv32gc rv32imc rv32i rv64i rv64fpquad; do
#for config in rv64gc; do
echo "$config linting..."
if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
if !($verilator --no-timing --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/wally/cvw.sv $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then
echo "Exiting after $config lint due to errors or warnings"
exit 1
fi

55
src/fpu/fcvt.sv
View file

@ -28,20 +28,20 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module fcvt import cvw::*; #(parameter cvw_t P) (
input logic Xs, // input's sign
input logic [P.NE-1:0] Xe, // input's exponent
input logic [P.NF:0] Xm, // input's fraction
input logic [P.XLEN-1:0] Int, // integer input - from IEU
input logic [2:0] OpCtrl, // choose which opperation (look below for values)
input logic ToInt, // is fp->int (since it's writting to the integer register)
input logic XZero, // is the input zero
input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half)
output logic [P.NE:0] Ce, // the calculated expoent
output logic [P.LOGCVTLEN-1:0] ShiftAmt, // how much to shift by
output logic ResSubnormUf,// does the result underflow or is subnormal
output logic Cs, // the result's sign
output logic IntZero, // is the integer zero?
output logic [P.CVTLEN-1:0] LzcIn // input to the Leading Zero Counter (priority encoder)
input logic Xs, // input's sign
input logic [P.NE-1:0] Xe, // input's exponent
input logic [P.NF:0] Xm, // input's fraction
input logic [P.XLEN-1:0] Int, // integer input - from IEU
input logic [2:0] OpCtrl, // choose which opperation (look below for values)
input logic ToInt, // is fp->int (since it's writting to the integer register)
input logic XZero, // is the input zero
input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half)
output logic [P.NE:0] Ce, // the calculated expoent
output logic [P.LOGCVTLEN-1:0] ShiftAmt, // how much to shift by
output logic ResSubnormUf, // does the result underflow or is subnormal
output logic Cs, // the result's sign
output logic IntZero, // is the integer zero?
output logic [P.CVTLEN-1:0] LzcIn // input to the Leading Zero Counter (priority encoder)
);
// OpCtrls:
@ -54,17 +54,16 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
// bit 2 bit 1 bit 0
// for example: signed long -> single floating point has the OpCode 101
logic [P.FMTBITS-1:0] OutFmt; // format of the output
logic [P.XLEN-1:0] PosInt; // the positive integer input
logic [P.XLEN-1:0] TrimInt; // integer trimmed to the correct size
logic [P.NE-2:0] NewBias; // the bias of the final result
logic [P.NE-1:0] OldExp; // the old exponent
logic Signed; // is the opperation with a signed integer?
logic Int64; // is the integer 64 bits?
logic IntToFp; // is the opperation an int->fp conversion?
logic [P.CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder)
logic [P.LOGCVTLEN-1:0] LeadingZeros; // output from the LZC
logic [P.FMTBITS-1:0] OutFmt; // format of the output
logic [P.XLEN-1:0] PosInt; // the positive integer input
logic [P.XLEN-1:0] TrimInt; // integer trimmed to the correct size
logic [P.NE-2:0] NewBias; // the bias of the final result
logic [P.NE-1:0] OldExp; // the old exponent
logic Signed; // is the opperation with a signed integer?
logic Int64; // is the integer 64 bits?
logic IntToFp; // is the opperation an int->fp conversion?
logic [P.CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder)
logic [P.LOGCVTLEN-1:0] LeadingZeros; // output from the LZC
// seperate OpCtrl for code readability
assign Signed = OpCtrl[0];
@ -79,7 +78,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
else if (P.FPSIZES == 3 | P.FPSIZES == 4)
assign OutFmt = IntToFp ? Fmt : OpCtrl[1:0];
///////////////////////////////////////////////////////////////////////////
// negation
///////////////////////////////////////////////////////////////////////////
@ -143,7 +141,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp;
end
// select the old exponent
// int -> fp : largest bias + XLEN-1
// fp -> ??? : XExp
@ -185,13 +182,11 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
// oldexp - biasold - LeadingZeros + newbias
assign Ce = {1'b0, OldExp} - (P.NE+1)'(P.BIAS) - {{P.NE-P.LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias};
// find if the result is dnormal or underflows
// - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0)
// - can't underflow an integer to Fp conversion
assign ResSubnormUf = (~|Ce | Ce[P.NE])&~XZero&~IntToFp;
///////////////////////////////////////////////////////////////////////////
// shifter
///////////////////////////////////////////////////////////////////////////
@ -212,7 +207,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
if(ToInt) ShiftAmt = Ce[P.LOGCVTLEN-1:0]&{P.LOGCVTLEN{~Ce[P.NE]}};
else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0];
else ShiftAmt = LeadingZeros;
///////////////////////////////////////////////////////////////////////////
// sign
@ -230,4 +224,3 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
else Cs = Xs;
endmodule

3
src/ifu/bpred/RASPredictor.sv
View file

@ -27,7 +27,8 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module RASPredictor import cvw::*; #(parameter cvw_t P, StackSize = 16 )(
module RASPredictor import cvw::*; #(parameter cvw_t P,
parameter StackSize = 16 )(
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,

3
src/ifu/bpred/btb.sv
View file

@ -28,7 +28,8 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module btb import cvw::*; #(parameter cvw_t P, Depth = 10 ) (
module btb import cvw::*; #(parameter cvw_t P,
parameter Depth = 10 ) (
input logic clk,
input logic reset,
input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,

3
src/ifu/bpred/icpred.sv
View file

@ -26,7 +26,8 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module icpred import cvw::*; #(parameter cvw_t P, INSTR_CLASS_PRED = 1)(
module icpred import cvw::*; #(parameter cvw_t P,
parameter INSTR_CLASS_PRED = 1)(
input logic clk, reset,
input logic StallF, StallD, StallE, StallM, StallW,
input logic FlushD, FlushE, FlushM, FlushW,

3
src/mmu/tlb/tlbcam.sv
View file

@ -29,7 +29,8 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module tlbcam import cvw::*; #(parameter cvw_t P, TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) (
module tlbcam import cvw::*; #(parameter cvw_t P,
parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) (
input logic clk, reset,
input logic [P.VPN_BITS-1:0] VPN,
input logic [1:0] PageTypeWriteVal,

3
src/mmu/tlb/tlbcamline.sv
View file

@ -29,7 +29,8 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module tlbcamline import cvw::*; #(parameter cvw_t P, KEY_BITS = 20, SEGMENT_BITS = 10) (
module tlbcamline import cvw::*; #(parameter cvw_t P,
parameter KEY_BITS = 20, SEGMENT_BITS = 10) (
input logic clk, reset,
input logic [P.VPN_BITS-1:0] VPN, // The requested page number to compare against the key
input logic [P.ASID_BITS-1:0] SATP_ASID,

3
src/mmu/tlb/tlbram.sv
View file

@ -29,7 +29,8 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module tlbram import cvw::*; #(parameter cvw_t P, TLB_ENTRIES = 8) (
module tlbram import cvw::*; #(parameter cvw_t P,
parameter TLB_ENTRIES = 8) (
input logic clk, reset,
input logic [P.XLEN-1:0] PTE,
input logic [TLB_ENTRIES-1:0] Matches, WriteEnables,

5
src/privileged/csr.sv
View file

@ -28,7 +28,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module csr import cvw::*; #(parameter cvw_t P, MIP = 12'h344, SIP = 12'h144) (
module csr import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic FlushM, FlushW,
input logic StallE, StallM, StallW,
@ -91,6 +91,9 @@ module csr import cvw::*; #(parameter cvw_t P, MIP = 12'h344, SIP = 12'h144) (
output logic BigEndianM // memory access is big-endian based on privilege mode and STATUS register endian fields
);
localparam MIP = 12'h344;
localparam SIP = 12'h144;
logic [P.XLEN-1:0] CSRMReadValM, CSRSReadValM, CSRUReadValM, CSRCReadValM;
logic [P.XLEN-1:0] CSRReadValM;
logic [P.XLEN-1:0] CSRSrcM;

2
src/privileged/csrc.sv
View file

@ -98,7 +98,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
assign CounterEvent[3] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction
assign CounterEvent[4] = InstrClassM[1] & ~InstrClassM[2] & InstrValidNotFlushedM; // jump and not return instructions
assign CounterEvent[5] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions
assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong
assign CounterEvent[6] = BPWrongM & InstrValidNotFlushedM; // branch predictor wrong
assign CounterEvent[7] = BPDirPredWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction
assign CounterEvent[8] = BTAWrongM & InstrValidNotFlushedM; // branch predictor wrong target
assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address

3
src/uncore/ahbapbbridge.sv
View file

@ -25,7 +25,8 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module ahbapbbridge import cvw::*; #(parameter cvw_t P, PERIPHS = 2) (
module ahbapbbridge import cvw::*; #(parameter cvw_t P,
parameter PERIPHS = 2) (
input logic HCLK, HRESETn,
input logic [PERIPHS-1:0] HSEL,
input logic [P.PA_BITS-1:0] HADDR,

3
src/uncore/ram_ahb.sv
View file

@ -28,7 +28,8 @@
`define RAM_LATENCY 0
module ram_ahb import cvw::*; #(parameter cvw_t P, BASE=0, RANGE = 65535) (
module ram_ahb import cvw::*; #(parameter cvw_t P,
parameter BASE=0, RANGE = 65535) (
input logic HCLK, HRESETn,
input logic HSELRam,
input logic [P.PA_BITS-1:0] HADDR,

3
src/uncore/rom_ahb.sv
View file

@ -26,7 +26,8 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module rom_ahb import cvw::*; #(parameter cvw_t P, BASE=0, RANGE = 65535) (
module rom_ahb import cvw::*; #(parameter cvw_t P,
parameter BASE=0, RANGE = 65535) (
input logic HCLK, HRESETn,
input logic HSELRom,
input logic [P.PA_BITS-1:0] HADDR,

1
src/wally/wallypipelinedsoc.sv
View file

@ -28,7 +28,6 @@
`include "config.vh"
//import cvw::*; // global CORE-V-Wally parameters
`include "wally-config.vh"
module wallypipelinedsoc import cvw::*; (
input logic clk,

2
testbench/testbench.sv
View file

@ -554,7 +554,7 @@ module testbench;
always @(*) begin
if(reset) begin
for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
end
for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;

5
tests/coverage/fpu.S
View file

@ -94,7 +94,10 @@ main:
fcvt.wu.q a0, ft3
fcvt.l.q a0, ft3
fcvt.lu.q a0, ft3
fcvt.l.s a0, ft0
fcvt.lu.s a0, ft0
fcvt.s.l ft0, t0
fcvt.s.lu ft0, t0
// Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc
# fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124