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Merge pull request #1351 from coreyqh/ccov
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Full csru code coverage
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David Harris 2025-04-09 11:05:35 -07:00 • committed by GitHub
commit 2ad4f20900
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6
sim/questa/coverage-exclusions-rv64gc.do
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@ -439,6 +439,12 @@ coverage exclude -scope /dut/core/hzu -linerange [GetLineNum ${SRC}/hazard/hazar
# Instruction Misaligned never asserted because compresssed instructions are accepted
coverage exclude -scope /dut/core/priv/priv/trap -linerange [GetLineNum ${SRC}/privileged/trap.sv "assign ExceptionM"] -item e 1 -fecexprrow 2
# Attempting to access fflags, frm, fcsr with mstatus.FS = 0 traps, so checking for (STATUS_FS != 2'b00)
# before enabling writes to these CSRs is redundant and uncoverable
coverage exclude -scope /dut/core/priv/priv/csr/csru/csru -linerange [GetLineNum ${SRC}/privileged/csru.sv "assign WriteFRMM"] -item e 1 -fecexprrow 3
coverage exclude -scope /dut/core/priv/priv/csr/csru/csru -linerange [GetLineNum ${SRC}/privileged/csru.sv "assign WriteFFLAGSM"] -item e 1 -fecexprrow 3
####################
# EBU
####################

2
src/privileged/csru.sv
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@ -51,6 +51,8 @@ module csru import cvw::*; #(parameter cvw_t P) (
logic WriteFFLAGSM;
// Write enables
// Explicitly checking STATUS_FS != 0 is redundant since the instruction traps otherwise,
// causing CSRWriteM to go low, but it is left here for safety
assign WriteFRMM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FRM | CSRAdrM == FCSR);
assign WriteFFLAGSM = CSRUWriteM & (STATUS_FS != 2'b00) & (CSRAdrM == FFLAGS | CSRAdrM == FCSR);