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Enable lots of rv64 wally-riscv-arch-test tests to run in Sail

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Jordan Carlin 2025-05-10 16:48:50 -07:00
parent 4f1e602c7c
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204
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-cboz-01.reference_output
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@ -1,204 +0,0 @@
deadbeef # begin_signature
deadbeef
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00000000 # destination 1
00000000
00000000
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00000000 # destination 2
00000000
00000000
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00000000
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00000000
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00000000
00000000
00000000
00000000
00000000
ffffffff # signature The test writes -1 for correct answers and the a positive integer for incorrect copies.
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
0bad0bad
0bad0bad
0bad0bad
0bad0bad

592
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-csr-permission-s-01.reference_output
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@ -1,592 +0,0 @@
0000000b # Test 5.2.3.6: ecall from going to S mode from M mode
00000000
00000002 # S mode write to mvendorid with illegal instruction
00000000
00000002 # S mode read from mvendorid with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to marchid with illegal instruction
00000000
00000002 # S mode read from marchid with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mimpid with illegal instruction
00000000
00000002 # S mode read from mimpid with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhartid with illegal instruction
00000000
00000002 # S mode read from mhartid with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mconfigptr with illegal instruction
00000000
00000002 # S mode read from mconfigptr with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mstatus with illegal instruction
00000000
00000002 # S mode read from mstatus with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to misa with illegal instruction
00000000
00000002 # S mode read from misa with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to medeleg with illegal instruction
00000000
00000002 # S mode read from medeleg with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mideleg with illegal instruction
00000000
00000002 # S mode read from mideleg with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mie with illegal instruction
00000000
00000002 # S mode read from mie with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mtvec with illegal instruction
00000000
00000002 # S mode read from mtvec with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mcounteren with illegal instruction
00000000
00000002 # S mode read from mcounteren with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mscratch with illegal instruction
00000000
00000002 # S mode read from mscratch with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mepc with illegal instruction
00000000
00000002 # S mode read from mepc with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mcause with illegal instruction
00000000
00000002 # S mode read from mcause with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mtval with illegal instruction
00000000
00000002 # S mode read from mtval with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mip with illegal instruction
00000000
00000002 # S mode read from mip with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to menvcfg with illegal instruction
00000000
00000002 # S mode read from menvcfg with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mseccfg with illegal instruction
00000000
00000002 # S mode read from mseccfg with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpcfg0 with illegal instruction
00000000
00000002 # S mode read from pmpcfg0 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpcfg2 with illegal instruction
00000000
00000002 # S mode read from pmpcfg2 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr0 with illegal instruction
00000000
00000002 # S mode read from pmpaddr0 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr1 with illegal instruction
00000000
00000002 # S mode read from pmpaddr1 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr2 with illegal instruction
00000000
00000002 # S mode read from pmpaddr2 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr3 with illegal instruction
00000000
00000002 # S mode read from pmpaddr3 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr4 with illegal instruction
00000000
00000002 # S mode read from pmpaddr4 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr5 with illegal instruction
00000000
00000002 # S mode read from pmpaddr5 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr6 with illegal instruction
00000000
00000002 # S mode read from pmpaddr6 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr7 with illegal instruction
00000000
00000002 # S mode read from pmpaddr7 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr8 with illegal instruction
00000000
00000002 # S mode read from pmpaddr8 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr9 with illegal instruction
00000000
00000002 # S mode read from pmpaddr9 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr10 with illegal instruction
00000000
00000002 # S mode read from pmpaddr10 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr11 with illegal instruction
00000000
00000002 # S mode read from pmpaddr11 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr12 with illegal instruction
00000000
00000002 # S mode read from pmpaddr12 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr13 with illegal instruction
00000000
00000002 # S mode read from pmpaddr13 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr14 with illegal instruction
00000000
00000002 # S mode read from pmpaddr14 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to pmpaddr15 with illegal instruction
00000000
00000002 # S mode read from pmpaddr15 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mcycle with illegal instruction
00000000
00000002 # S mode read from mcycle with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to minstret with illegal instruction
00000000
00000002 # S mode read from minstret with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter3 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter3 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter4 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter4 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter5 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter5 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter6 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter6 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter7 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter7 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter8 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter8 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter9 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter9 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter10 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter10 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter11 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter11 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter12 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter12 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter13 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter13 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter14 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter14 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter15 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter15 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter16 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter16 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter17 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter17 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter18 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter18 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter19 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter19 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter20 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter20 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter21 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter21 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter22 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter22 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter23 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter23 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter24 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter24 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter25 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter25 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter26 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter26 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter27 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter27 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter28 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter28 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter29 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter29 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter30 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter30 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmcounter31 with illegal instruction
00000000
00000002 # S mode read from mhpmcounter31 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mcountinhibit with illegal instruction
00000000
00000002 # S mode read from mcountinhibit with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent3 with illegal instruction
00000000
00000002 # S mode read from mhpmevent3 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent4 with illegal instruction
00000000
00000002 # S mode read from mhpmevent4 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent5 with illegal instruction
00000000
00000002 # S mode read from mhpmevent5 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent6 with illegal instruction
00000000
00000002 # S mode read from mhpmevent6 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent7 with illegal instruction
00000000
00000002 # S mode read from mhpmevent7 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent8 with illegal instruction
00000000
00000002 # S mode read from mhpmevent8 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent9 with illegal instruction
00000000
00000002 # S mode read from mhpmevent9 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent10 with illegal instruction
00000000
00000002 # S mode read from mhpmevent10 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent11 with illegal instruction
00000000
00000002 # S mode read from mhpmevent11 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent12 with illegal instruction
00000000
00000002 # S mode read from mhpmevent12 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent13 with illegal instruction
00000000
00000002 # S mode read from mhpmevent13 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent14 with illegal instruction
00000000
00000002 # S mode read from mhpmevent14 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent15 with illegal instruction
00000000
00000002 # S mode read from mhpmevent15 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent16 with illegal instruction
00000000
00000002 # S mode read from mhpmevent16 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent17 with illegal instruction
00000000
00000002 # S mode read from mhpmevent17 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent18 with illegal instruction
00000000
00000002 # S mode read from mhpmevent18 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent19 with illegal instruction
00000000
00000002 # S mode read from mhpmevent19 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent20 with illegal instruction
00000000
00000002 # S mode read from mhpmevent20 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent21 with illegal instruction
00000000
00000002 # S mode read from mhpmevent21 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent22 with illegal instruction
00000000
00000002 # S mode read from mhpmevent22 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent23 with illegal instruction
00000000
00000002 # S mode read from mhpmevent23 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent24 with illegal instruction
00000000
00000002 # S mode read from mhpmevent24 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent25 with illegal instruction
00000000
00000002 # S mode read from mhpmevent25 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent26 with illegal instruction
00000000
00000002 # S mode read from mhpmevent26 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent27 with illegal instruction
00000000
00000002 # S mode read from mhpmevent27 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent28 with illegal instruction
00000000
00000002 # S mode read from mhpmevent28 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent29 with illegal instruction
00000000
00000002 # S mode read from mhpmevent29 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent30 with illegal instruction
00000000
00000002 # S mode read from mhpmevent30 with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mhpmevent31 with illegal instruction
00000000
00000002 # S mode read from mhpmevent31 with illegal instruction
00000000
00000bad
00000000
00000009 # ecall from terminating tess from S mode
00000000

652
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-csr-permission-u-01.reference_output
View file

@ -1,652 +0,0 @@
0000000b # Test 5.2.3.6: ecall from going to U mode from M mode
00000000
00000002 # U mode write to sstatus with illegal instruction
00000000
00000002 # U mode read from sstatus with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to sie with illegal instruction
00000000
00000002 # U mode read from sie with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to stvec with illegal instruction
00000000
00000002 # U mode read from stvec with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to scounteren with illegal instruction
00000000
00000002 # U mode read from scounteren with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to sscratch with illegal instruction
00000000
00000002 # U mode read from sscratch with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to sepc with illegal instruction
00000000
00000002 # U mode read from sepc with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to scause with illegal instruction
00000000
00000002 # U mode read from scause with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to stval with illegal instruction
00000000
00000002 # U mode read from stval with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to sip with illegal instruction
00000000
00000002 # U mode read from sip with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to satp with illegal instruction
00000000
00000002 # U mode read from satp with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mvendorid with illegal instruction
00000000
00000002 # U mode read from mvendorid with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to marchid with illegal instruction
00000000
00000002 # U mode read from marchid with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mimpid with illegal instruction
00000000
00000002 # U mode read from mimpid with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhartid with illegal instruction
00000000
00000002 # U mode read from mhartid with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mconfigptr with illegal instruction
00000000
00000002 # S mode read from mconfigptr with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mstatus with illegal instruction
00000000
00000002 # U mode read from mstatus with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to misa with illegal instruction
00000000
00000002 # U mode read from misa with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to medeleg with illegal instruction
00000000
00000002 # U mode read from medeleg with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mideleg with illegal instruction
00000000
00000002 # U mode read from mideleg with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mie with illegal instruction
00000000
00000002 # U mode read from mie with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mtvec with illegal instruction
00000000
00000002 # U mode read from mtvec with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mcounteren with illegal instruction
00000000
00000002 # U mode read from mcounteren with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mscratch with illegal instruction
00000000
00000002 # U mode read from mscratch with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mepc with illegal instruction
00000000
00000002 # U mode read from mepc with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mcause with illegal instruction
00000000
00000002 # U mode read from mcause with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mtval with illegal instruction
00000000
00000002 # U mode read from mtval with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mip with illegal instruction
00000000
00000002 # U mode read from mip with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to menvcfg with illegal instruction
00000000
00000002 # S mode read from menvcfg with illegal instruction
00000000
00000bad
00000000
00000002 # S mode write to mseccfg with illegal instruction
00000000
00000002 # S mode read from mseccfg with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpcfg0 with illegal instruction
00000000
00000002 # U mode read from pmpcfg0 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpcfg2 with illegal instruction
00000000
00000002 # U mode read from pmpcfg2 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr0 with illegal instruction
00000000
00000002 # U mode read from pmpaddr0 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr1 with illegal instruction
00000000
00000002 # U mode read from pmpaddr1 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr2 with illegal instruction
00000000
00000002 # U mode read from pmpaddr2 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr3 with illegal instruction
00000000
00000002 # U mode read from pmpaddr3 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr4 with illegal instruction
00000000
00000002 # U mode read from pmpaddr4 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr5 with illegal instruction
00000000
00000002 # U mode read from pmpaddr5 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr6 with illegal instruction
00000000
00000002 # U mode read from pmpaddr6 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr7 with illegal instruction
00000000
00000002 # U mode read from pmpaddr7 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr8 with illegal instruction
00000000
00000002 # U mode read from pmpaddr8 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr9 with illegal instruction
00000000
00000002 # U mode read from pmpaddr9 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr10 with illegal instruction
00000000
00000002 # U mode read from pmpaddr10 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr11 with illegal instruction
00000000
00000002 # U mode read from pmpaddr11 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr12 with illegal instruction
00000000
00000002 # U mode read from pmpaddr12 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr13 with illegal instruction
00000000
00000002 # U mode read from pmpaddr13 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr14 with illegal instruction
00000000
00000002 # U mode read from pmpaddr14 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to pmpaddr15 with illegal instruction
00000000
00000002 # U mode read from pmpaddr15 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mcycle with illegal instruction
00000000
00000002 # U mode read from mcycle with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to minstret with illegal instruction
00000000
00000002 # U mode read from minstret with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter3 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter3 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter4 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter4 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter5 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter5 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter6 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter6 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter7 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter7 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter8 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter8 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter9 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter9 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter10 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter10 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter11 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter11 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter12 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter12 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter13 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter13 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter14 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter14 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter15 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter15 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter16 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter16 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter17 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter17 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter18 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter18 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter19 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter19 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter20 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter20 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter21 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter21 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter22 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter22 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter23 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter23 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter24 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter24 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter25 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter25 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter26 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter26 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter27 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter27 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter28 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter28 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter29 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter29 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter30 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter30 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmcounter31 with illegal instruction
00000000
00000002 # U mode read from mhpmcounter31 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mcountinhibit with illegal instruction
00000000
00000002 # U mode read from mcountinhibit with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent3 with illegal instruction
00000000
00000002 # U mode read from mhpmevent3 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent4 with illegal instruction
00000000
00000002 # U mode read from mhpmevent4 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent5 with illegal instruction
00000000
00000002 # U mode read from mhpmevent5 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent6 with illegal instruction
00000000
00000002 # U mode read from mhpmevent6 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent7 with illegal instruction
00000000
00000002 # U mode read from mhpmevent7 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent8 with illegal instruction
00000000
00000002 # U mode read from mhpmevent8 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent9 with illegal instruction
00000000
00000002 # U mode read from mhpmevent9 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent10 with illegal instruction
00000000
00000002 # U mode read from mhpmevent10 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent11 with illegal instruction
00000000
00000002 # U mode read from mhpmevent11 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent12 with illegal instruction
00000000
00000002 # U mode read from mhpmevent12 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent13 with illegal instruction
00000000
00000002 # U mode read from mhpmevent13 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent14 with illegal instruction
00000000
00000002 # U mode read from mhpmevent14 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent15 with illegal instruction
00000000
00000002 # U mode read from mhpmevent15 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent16 with illegal instruction
00000000
00000002 # U mode read from mhpmevent16 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent17 with illegal instruction
00000000
00000002 # U mode read from mhpmevent17 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent18 with illegal instruction
00000000
00000002 # U mode read from mhpmevent18 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent19 with illegal instruction
00000000
00000002 # U mode read from mhpmevent19 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent20 with illegal instruction
00000000
00000002 # U mode read from mhpmevent20 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent21 with illegal instruction
00000000
00000002 # U mode read from mhpmevent21 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent22 with illegal instruction
00000000
00000002 # U mode read from mhpmevent22 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent23 with illegal instruction
00000000
00000002 # U mode read from mhpmevent23 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent24 with illegal instruction
00000000
00000002 # U mode read from mhpmevent24 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent25 with illegal instruction
00000000
00000002 # U mode read from mhpmevent25 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent26 with illegal instruction
00000000
00000002 # U mode read from mhpmevent26 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent27 with illegal instruction
00000000
00000002 # U mode read from mhpmevent27 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent28 with illegal instruction
00000000
00000002 # U mode read from mhpmevent28 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent29 with illegal instruction
00000000
00000002 # U mode read from mhpmevent29 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent30 with illegal instruction
00000000
00000002 # U mode read from mhpmevent30 with illegal instruction
00000000
00000bad
00000000
00000002 # U mode write to mhpmevent31 with illegal instruction
00000000
00000002 # U mode read from mhpmevent31 with illegal instruction
00000000
00000bad
00000000
00000008 # ecall from terminating tests in U mode
00000000

22
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-minfo-01.reference_output
View file

@ -1,22 +0,0 @@
00000002 # Test 5.2.3.1: write to read-only CSR failed with illegal instruction
00000000
00000011 # confirm read-only permissions of mvendorid
00000000
00000002 # write to read-only CSR failed with illegal instruction
00000000
00000011 # confirm read-only permissions of marchid
00000000
00000002 # write to read-only CSR failed with illegal instruction
00000000
00000011 # confirm read-only permissions of mimpid
00000000
00000002 # write to read-only CSR failed with illegal instruction
00000000
00000011 # confirm read-only permissions of mhartid
00000000
00000002 # write to read-only CSR failed with illegal instruction
00000000
00000011 # confirm read-only permissions of mconfigptr
00000000
0000000b # ecall from terminating tests in M mode
00000000

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misa-01.reference_output
View file

@ -1,4 +0,0 @@
00000111 # Test 5.3.2.2: successful read of nonzero misa
00000000
0000000b # ecall from terminating tests in machine mode
00000000

560
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-misaligned-access-01.reference_output
View file

@ -1,560 +0,0 @@
03020100 # ByteDstData
07060504
0b0a0908
0f0e0d0c
13021110
17161514
1b1a1918
1f1e1d1c
23222120
27262524
2b2a2928
2f2e2d2c
33023130
37363534
3b3a3938
3f3e3d3c
43424140
47464544
4b4a4948
4f4e4d4c
53025150
57565554
5b5a5958
5f5e5d5c
63626160
67666564
6b6a6968
6f6e6d6c
73027170
77767574
7b7a7978
7f7e7d7c
03020100 # Half0DstData
07060504
0b0a0908
0f0e0d0c
13021110
17161514
1b1a1918
1f1e1d1c
23222120
27262524
2b2a2928
2f2e2d2c
33023130
37363534
3b3a3938
3f3e3d3c
43424140
47464544
4b4a4948
4f4e4d4c
53025150
57565554
5b5a5958
5f5e5d5c
63626160
67666564
6b6a6968
6f6e6d6c
73027170
77767574
7b7a7978
7f7e7d7c
020100ef # Half1DstData
06050403
0a090807
0e0d0c0b
0211100f
16151413
1a191817
1e1d1c1b
2221201f
26252423
2a292827
2e2d2c2b
0231302f
36353433
3a393837
3e3d3c3b
4241403f
46454443
4a494847
4e4d4c4b
0251504f
56555453
5a595857
5e5d5c5b
6261605f
66656463
6a696867
6e6d6c6b
0271706f
76757473
7a797877
7e7d7c7b
deadbe7f
deadbeef
03020100 # Word0DstData
07060504
0b0a0908
0f0e0d0c
13021110
17161514
1b1a1918
1f1e1d1c
23222120
27262524
2b2a2928
2f2e2d2c
33023130
37363534
3b3a3938
3f3e3d3c
43424140
47464544
4b4a4948
4f4e4d4c
53025150
57565554
5b5a5958
5f5e5d5c
63626160
67666564
6b6a6968
6f6e6d6c
73027170
77767574
7b7a7978
7f7e7d7c
020100ef # Word1DstData
06050403
0a090807
0e0d0c0b
0211100f
16151413
1a191817
1e1d1c1b
2221201f
26252423
2a292827
2e2d2c2b
0231302f
36353433
3a393837
3e3d3c3b
4241403f
46454443
4a494847
4e4d4c4b
0251504f
56555453
5a595857
5e5d5c5b
6261605f
66656463
6a696867
6e6d6c6b
0271706f
76757473
7a797877
7e7d7c7b
deadbe7f
deadbeef
0100beef # Word2DstData
05040302
09080706
0d0c0b0a
11100f0e
15141302
19181716
1d1c1b1a
21201f1e
25242322
29282726
2d2c2b2a
31302f2e
35343302
39383736
3d3c3b3a
41403f3e
45444342
49484746
4d4c4b4a
51504f4e
55545302
59585756
5d5c5b5a
61605f5e
65646362
69686766
6d6c6b6a
71706f6e
75747302
79787776
7d7c7b7a
dead7f7e
deadbeef
00adbeef # Word3DstData
04030201
08070605
0c0b0a09
100f0e0d
14130211
18171615
1c1b1a19
201f1e1d
24232221
28272625
2c2b2a29
302f2e2d
34330231
38373635
3c3b3a39
403f3e3d
44434241
48474645
4c4b4a49
504f4e4d
54530251
58575655
5c5b5a59
605f5e5d
64636261
68676665
6c6b6a69
706f6e6d
74730271
78777675
7c7b7a79
de7f7e7d
deadbeef
03020100 # Double0DstData
07060504
0b0a0908
0f0e0d0c
13021110
17161514
1b1a1918
1f1e1d1c
23222120
27262524
2b2a2928
2f2e2d2c
33023130
37363534
3b3a3938
3f3e3d3c
43424140
47464544
4b4a4948
4f4e4d4c
53025150
57565554
5b5a5958
5f5e5d5c
63626160
67666564
6b6a6968
6f6e6d6c
73027170
77767574
7b7a7978
7f7e7d7c
020100ef # Double1DstData
06050403
0a090807
0e0d0c0b
0211100f
16151413
1a191817
1e1d1c1b
2221201f
26252423
2a292827
2e2d2c2b
0231302f
36353433
3a393837
3e3d3c3b
4241403f
46454443
4a494847
4e4d4c4b
0251504f
56555453
5a595857
5e5d5c5b
6261605f
66656463
6a696867
6e6d6c6b
0271706f
76757473
7a797877
7e7d7c7b
deadbe7f
deadbeef
0100beef # Double2DstData
05040302
09080706
0d0c0b0a
11100f0e
15141302
19181716
1d1c1b1a
21201f1e
25242322
29282726
2d2c2b2a
31302f2e
35343302
39383736
3d3c3b3a
41403f3e
45444342
49484746
4d4c4b4a
51504f4e
55545302
59585756
5d5c5b5a
61605f5e
65646362
69686766
6d6c6b6a
71706f6e
75747302
79787776
7d7c7b7a
dead7f7e
deadbeef
00adbeef # Double3DstData
04030201
08070605
0c0b0a09
100f0e0d
14130211
18171615
1c1b1a19
201f1e1d
24232221
28272625
2c2b2a29
302f2e2d
34330231
38373635
3c3b3a39
403f3e3d
44434241
48474645
4c4b4a49
504f4e4d
54530251
58575655
5c5b5a59
605f5e5d
64636261
68676665
6c6b6a69
706f6e6d
74730271
78777675
7c7b7a79
de7f7e7d
deadbeef
deadbeef # Double4DstData
03020100
07060504
0b0a0908
0f0e0d0c
13021110
17161514
1b1a1918
1f1e1d1c
23222120
27262524
2b2a2928
2f2e2d2c
33023130
37363534
3b3a3938
3f3e3d3c
43424140
47464544
4b4a4948
4f4e4d4c
53025150
57565554
5b5a5958
5f5e5d5c
63626160
67666564
6b6a6968
6f6e6d6c
73027170
77767574
7b7a7978
7f7e7d7c
deadbeef
deadbeef # Double5DstData
020100ef
06050403
0a090807
0e0d0c0b
0211100f
16151413
1a191817
1e1d1c1b
2221201f
26252423
2a292827
2e2d2c2b
0231302f
36353433
3a393837
3e3d3c3b
4241403f
46454443
4a494847
4e4d4c4b
0251504f
56555453
5a595857
5e5d5c5b
6261605f
66656463
6a696867
6e6d6c6b
0271706f
76757473
7a797877
7e7d7c7b
deadbe7f
deadbeef # Double6DstData
0100beef
05040302
09080706
0d0c0b0a
11100f0e
15141302
19181716
1d1c1b1a
21201f1e
25242322
29282726
2d2c2b2a
31302f2e
35343302
39383736
3d3c3b3a
41403f3e
45444342
49484746
4d4c4b4a
51504f4e
55545302
59585756
5d5c5b5a
61605f5e
65646362
69686766
6d6c6b6a
71706f6e
75747302
79787776
7d7c7b7a
dead7f7e
deadbeef # Double7DstData
00adbeef
04030201
08070605
0c0b0a09
100f0e0d
14130211
18171615
1c1b1a19
201f1e1d
24232221
28272625
2c2b2a29
302f2e2d
34330231
38373635
3c3b3a39
403f3e3d
44434241
48474645
4c4b4a49
504f4e4d
54530251
58575655
5c5b5a59
605f5e5d
64636261
68676665
6c6b6a69
706f6e6d
74730271
78777675
7c7b7a79
de7f7e7d
ffffffff #signature
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
ffffffff
000000ff
00000000

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-satp-invalid-01.reference_output
View file

@ -1,6 +0,0 @@
0000000b # Test *** Number: Ecall from going from M mode to S mode
00000000
00000001 # Instruction access fault from turning on virtual memory with invalid satp address
00000000
00000009 # ecall from ending tests in S mode.
00000000

12
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-fp-enabled-01.reference_output
View file

@ -1,12 +0,0 @@
00002000 # read SD = 0, FS = 01
00000000
00006000 # read SD = 1, FS = 11
80000000
00004000 # read written SD = 1, FS = 10
00000000
00006000 # read SD = 1, FS = 11
80000000
00000002 # mcause from attempting fmv with status.FS cleared
00000000
0000000b # mcause from M mode ecall from test termination
00000000

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-status-xlen-01.reference_output
View file

@ -1,4 +0,0 @@
00000000 # Test *** Number : Read out SXL, UXL of mstatus as 2 and 2 for 64 bit systems
0000000a
0000000b # ecall from ending tests in M mode
00000000

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-cboz-01.S
View file

@ -31,7 +31,7 @@ rvtest_entry_point:
RVMODEL_BOOT RVMODEL_BOOT
RVTEST_CODE_BEGIN RVTEST_CODE_BEGIN
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",cbo.zero) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",cbo.zero)
RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n") RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-s-01.S
View file

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-s) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-s)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-csr-permission-u-01.S
View file

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",csr-permission-u) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",csr-permission-u)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S
View file

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",minfo) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",minfo)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S
View file

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",misa) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",misa)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misaligned-access-01.S
View file

@ -27,7 +27,7 @@ rvtest_entry_point:
RVMODEL_BOOT RVMODEL_BOOT
RVTEST_CODE_BEGIN RVTEST_CODE_BEGIN
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",ld) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",ld)
# This test checks the misaligned load and stores work correctly and across D$ line spills. # This test checks the misaligned load and stores work correctly and across D$ line spills.
# The general approach is to # The general approach is to

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-satp-invalid-01.S
View file

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;def NO_SAIL=True;",satp-invalid) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); def Drvtest_mtrap_routine=True; def TEST_CASE_1=True;",satp-invalid)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S
View file

@ -23,7 +23,7 @@
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64IAF_Zicsr") RVTEST_ISA("RV64IAF_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*F.*);def TEST_CASE_1=True;def NO_SAIL=True;",status-fp-enabled) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*A.*F.*);def TEST_CASE_1=True;",status-fp-enabled)
INIT_TESTS INIT_TESTS

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-status-xlen-01.S
View file

@ -24,7 +24,7 @@
#include "WALLY-TEST-LIB-64.h" #include "WALLY-TEST-LIB-64.h"
RVTEST_ISA("RV64I_Zicsr") RVTEST_ISA("RV64I_Zicsr")
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;def NO_SAIL=True;",xlen) RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",xlen)
INIT_TESTS INIT_TESTS