mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-20 03:47:20 -04:00
Well on the way to a fully automated FPGA build process which
correctly sets the clocks and memory locations.
This commit is contained in:
Rose Thompson
parent
f1d9e18dee
commit
2e55f1cecc
6 changed files with 24 additions and 108 deletions
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@ -8,19 +8,22 @@ ArtyA7: export XILINX_PART := xc7a100tcsg324-1
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ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
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ArtyA7: export board := ArtyA7
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ArtyA7: FPGA_Arty
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ArtyA7: CLOCK := 20000000
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vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e
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vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
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vcu118: export board := vcu118
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vcu118: FPGA_VCU
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vcu118: CLOCK := 71000000
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vcu108: export XILINX_PART := xcvu095-ffva2104-2-e
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vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
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vcu108: export board := vcu108
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vcu108: FPGA_VCU
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vcu108: CLOCK := 50000000
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.PHONY: FPGA_Arty FPGA_VCU
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FPGA_Arty: PreProcessFiles IP_Arty
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FPGA_Arty: PreProcessFiles IP_Arty zsbl
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vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
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FPGA_VCU: PreProcessFiles IP_VCU
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vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
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@ -60,6 +63,11 @@ PreProcessFiles:
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sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
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sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
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# build the Zero stage boot loader (ZSBL)
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.PHONE: zsbl
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zsbl:
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CLOCK = CLOCK $(MAKE) -C ../zsbl
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# Generate Individual IP Blocks
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$(dst)/%.log: %.tcl
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mkdir -p IP
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@ -1,6 +1,7 @@
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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set CPUClock $::env(CLOCK)
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#set partNumber xcvu9p-flga2104-2L-e
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#set boardName xilinx.com:vcu118:part0:2.4
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@ -38,7 +39,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
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CONFIG.C0.DDR4_AxiNarrowBurst {false} \
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CONFIG.Reference_Clock {Differential} \
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CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \
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CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {$CPUClock} \
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CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
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CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
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@ -1,6 +1,7 @@
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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set CPUClock $::env(CLOCK)
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#set partNumber xcvu9p-flga2104-2L-e
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#set boardName xilinx.com:vcu118:part0:2.4
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@ -38,7 +39,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
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CONFIG.C0.DDR4_AxiNarrowBurst {false} \
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CONFIG.Reference_Clock {Differential} \
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CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {71} \
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CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {$CPUClock} \
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CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
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CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
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CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
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@ -27,11 +27,16 @@ MABI :=-mabi=lp64d
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LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -L $(RISCV)/riscv64-unknown-elf/lib
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LINKER :=linker1000.x
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# FGPA parameters
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CLOCK ?= 20000000
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MEMSTART ?= 0x80000000
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MEMSIZE ?= 0x10000000
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AFLAGS =$(MARCH) $(MABI) -W
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# Override directive allows us to prepend other options on the command line
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# e.g. $ make CFLAGS=-g
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override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g
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override CFLAGS +=$(MARCH) $(MABI) -mcmodel=medany -O2 -g -DSYSTEMCLOCK=${CLOCK} -DMEMSTART=${MEMSTART} -DMEMSIZE=${MEMSIZE}
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AS=riscv64-unknown-elf-as
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CC=riscv64-unknown-elf-gcc
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AR=riscv64-unknown-elf-ar
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101
fpga/zsbl/bios.s
101
fpga/zsbl/bios.s
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@ -1,101 +0,0 @@
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PERIOD = 11000000
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#PERIOD = 20
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.section .init
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.global _start
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.type _start, @function
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_start:
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# Initialize global pointer
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.option push
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.option norelax
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1:auipc gp, %pcrel_hi(__global_pointer$)
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addi gp, gp, %pcrel_lo(1b)
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.option pop
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li x1, 0
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li x2, 0
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li x4, 0
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li x5, 0
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li x6, 0
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li x7, 0
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li x8, 0
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li x9, 0
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li x10, 0
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li x11, 0
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li x12, 0
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li x13, 0
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li x14, 0
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li x15, 0
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li x16, 0
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li x17, 0
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li x18, 0
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li x19, 0
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li x20, 0
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li x21, 0
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li x22, 0
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li x23, 0
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li x24, 0
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li x25, 0
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li x26, 0
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li x27, 0
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li x28, 0
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li x29, 0
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li x30, 0
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li x31, 0
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# set the stack pointer to the top of memory - 8 bytes (pointer size)
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li sp, 0x87FFFFF8
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li a0, 0x00000000
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li a1, 0x80000000
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#li a2, 128*1024*1024/512 # copy 128MB
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li a2, 127*1024*1024/512 # copy 127MB upper 1MB contains the return address (ra)
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#li a2, 800 # copy 400KB
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jal ra, copyFlash
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fence.i
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# now toggle led so we know the copy completed.
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# write to gpio
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li t2, 0xFF
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la t3, 0x1006000C
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li t4, 5
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loop:
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# delay
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li t0, PERIOD/2
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delay1:
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addi t0, t0, -1
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bge t0, x0, delay1
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sw t2, 0x0(t3)
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li t0, PERIOD/2
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delay2:
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addi t0, t0, -1
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bge t0, x0, delay2
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sw x0, 0x0(t3)
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addi t4, t4, -1
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bgt t4, x0, loop
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# now that the card is copied and the led toggled we
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# jump to the copied contents of the sd card.
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jumpToLinux:
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csrrs a0, 0xF14, x0 # copy hart ID to a0
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li a1, 0x87000000 # end of memory? not 100% sure on this but it's 112MB
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la a2, end_of_bios
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li t0, 0x80000000 # start of code
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jalr x0, t0, 0
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end_of_bios:
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@ -31,6 +31,7 @@
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#define WALLYBOOT 10000
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#include <stdint.h>
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#include "system.h"
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typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
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typedef unsigned char BYTE; /* char must be 8-bit */
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typedef uint16_t WORD; /* 16-bit unsigned integer */
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@ -44,7 +45,7 @@ typedef QWORD LBA_t;
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// These locations are copied from the generic configuration
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// of OpenSBI. These addresses can be found in:
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// buildroot/output/build/opensbi-0.9/platform/generic/config.mk
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#define FDT_ADDRESS 0x87000000 // FW_JUMP_FDT_ADDR
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#define FDT_ADDRESS 0xFF000000 // FW_JUMP_FDT_ADDR
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#define OPENSBI_ADDRESS 0x80000000 // FW_TEXT_START
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#define KERNEL_ADDRESS 0x80200000 // FW_JUMP_ADDR
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@ -61,11 +62,12 @@ typedef QWORD LBA_t;
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// Export disk_read
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int disk_read(BYTE * buf, LBA_t sector, UINT count);
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#define SYSTEMCLOCK 20000000
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//#define SYSTEMCLOCK 50000000
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// *** fix me: now defined in system.h
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// TODO: This line needs to change back to 20MHz when we fix the
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// timing problems.
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#define MAXSDCCLOCK 5000000
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#define MAXSDCCLOCK 12500000
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// Maximum SDC speed is either the system clock divided by 2 (because
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// of the SPI peripheral clock division) or the maximum speed an SD
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