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Well on the way to a fully automated FPGA build process which

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correctly sets the clocks and memory locations.
This commit is contained in:
Rose Thompson 2024-09-02 11:19:02 -07:00
parent f1d9e18dee
commit 2e55f1cecc
6 changed files with 24 additions and 108 deletions
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10
fpga/generator/Makefile
View file

@ -8,19 +8,22 @@ ArtyA7: export XILINX_PART := xc7a100tcsg324-1
ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
ArtyA7: export board := ArtyA7
ArtyA7: FPGA_Arty
ArtyA7: CLOCK := 20000000
vcu118: export XILINX_PART := xcvu9p-flga2104-2L-e
vcu118: export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
vcu118: export board := vcu118
vcu118: FPGA_VCU
vcu118: CLOCK := 71000000
vcu108: export XILINX_PART := xcvu095-ffva2104-2-e
vcu108: export XILINX_BOARD := xilinx.com:vcu108:part0:1.7
vcu108: export board := vcu108
vcu108: FPGA_VCU
vcu108: CLOCK := 50000000
.PHONY: FPGA_Arty FPGA_VCU
FPGA_Arty: PreProcessFiles IP_Arty
FPGA_Arty: PreProcessFiles IP_Arty zsbl
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
FPGA_VCU: PreProcessFiles IP_VCU
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
@ -60,6 +63,11 @@ PreProcessFiles:
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
sed -i 's/$$WALLY/\.\.\/\.\.\/\.\.\//g' ../src/CopiedFiles_do_not_add_to_repo/generic/mem/ram1p1rwbe.sv
# build the Zero stage boot loader (ZSBL)
.PHONE: zsbl
zsbl:
CLOCK = CLOCK $(MAKE) -C ../zsbl
# Generate Individual IP Blocks
$(dst)/%.log: %.tcl
mkdir -p IP

3
fpga/generator/ddr4-vcu108.tcl
View file

@ -1,6 +1,7 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set CPUClock $::env(CLOCK)
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
@ -38,7 +39,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {$CPUClock} \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \

3
fpga/generator/ddr4-vcu118.tcl
View file

@ -1,6 +1,7 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set CPUClock $::env(CLOCK)
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
@ -38,7 +39,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {71} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {$CPUClock} \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \