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Well on the way to a fully automated FPGA build process which

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correctly sets the clocks and memory locations.
This commit is contained in:
Rose Thompson 2024-09-02 11:19:02 -07:00
parent f1d9e18dee
commit 2e55f1cecc
6 changed files with 24 additions and 108 deletions
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3
fpga/generator/ddr4-vcu108.tcl
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@ -1,6 +1,7 @@
set partNumber $::env(XILINX_PART)
set boardName $::env(XILINX_BOARD)
set CPUClock $::env(CLOCK)
#set partNumber xcvu9p-flga2104-2L-e
#set boardName xilinx.com:vcu118:part0:2.4
@ -38,7 +39,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
CONFIG.C0.DDR4_AxiNarrowBurst {false} \
CONFIG.Reference_Clock {Differential} \
CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {50} \
CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {$CPUClock} \
CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {300} \
CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \