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https://github.com/openhwgroup/cvw.git
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Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
This commit is contained in:
Ross Thompson
parent
d967e05c20
commit
2f8359e6cc
3 changed files with 78 additions and 55 deletions
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@ -4,6 +4,8 @@
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# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP.
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# clock comes from pin E3 and is 100Mhz
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# output of mmcm is /4 => 25Mhz
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create_clock -period 25.000 -name mmcm_clkout1 -waveform {0.000 12.500} [get_nets xlnx_ddr3_c0/ui_clk]
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create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
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@ -39,12 +41,12 @@ set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_por
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##### UART #####
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# *** IOSTANDARD is probably wrong
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set_property PACKAGE_PIN A9 [get_ports UARTSin]
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set_property PACKAGE_PIN D0 [get_ports UARTSout]
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set_property PACKAGE_PIN D10 [get_ports UARTSout]
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set_max_delay -from [get_ports UARTSin] 10.000
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set_max_delay -to [get_ports UARTSout] 10.000
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set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
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set_property IOSTANDARD LVCMOS33 [get_ports UARTSout]
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set_property DRIVE 6 [get_ports UARTSout]
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set_property DRIVE 4 [get_ports UARTSout]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]
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set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout]
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@ -53,12 +55,8 @@ set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_por
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##### reset #####
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#************** reset is inverted
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set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset]
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set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports reset]
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set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports reset]
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set_max_delay -from [get_ports reset] 15.000
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set_false_path -from [get_ports reset]
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set_property PACKAGE_PIN C2 [get_ports {reset}]
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@ -72,7 +70,7 @@ set_property PACKAGE_PIN D4 [get_ports {SDCDat[3]}]
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set_property PACKAGE_PIN D2 [get_ports {SDCDat[2]}]
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set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}]
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set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}]
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set_property PACKAGE_PIN F2 [get_ports SDCCLK]
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set_property PACKAGE_PIN F3 [get_ports SDCCLK]
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set_property PACKAGE_PIN D3 [get_ports {SDCCmd}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}]
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@ -101,59 +99,59 @@ set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_por
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set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
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# *********************************
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set_property DCI_CASCADE {64} [get_iobanks 65]
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set_property INTERNAL_VREF 0.9 [get_iobanks 65]
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#set_property DCI_CASCADE {64} [get_iobanks 65]
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#set_property INTERNAL_VREF 0.9 [get_iobanks 65]
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# ddr3
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[2]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[3]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[4]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[5]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[6]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[7]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[8]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[9]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[10]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[11]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[12]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[13]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[14]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dq[15]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_dm[1]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[1]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[2]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[3]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[4]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[5]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[6]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[7]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[8]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[9]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[10]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[11]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[12]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[13]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[14]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dq[15]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dm[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_dm[1]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[0]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[0]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_p[1]
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set_property IOSTANDARD DIFF [get_ports ddr3_dqs_n[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[13]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[12]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[11]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[10]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[9]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[8]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[7]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[6]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[5]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[4]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[3]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[2]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_addr[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[2]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[1]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ba[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[13]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[12]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[11]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[10]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[9]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[8]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[7]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[6]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[5]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[4]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[3]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[2]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[1]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_addr[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_ba[2]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_ba[1]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_ba[0]
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set_property IOSTANDARD DIFF [get_ports ddr3_ck_p[0]
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set_property IOSTANDARD DIFF [get_ports ddr3_ck_n[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n
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set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n
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set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cke[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_odt[0]
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set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n
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set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n
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set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n
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set_property IOSTANDARD SSTL15 [get_ports ddr3_reset_n
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set_property IOSTANDARD SSTL15 [get_ports ddr3_cke[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_odt[0]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_cs_n[0]
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set_properity PACKAGE_PIN K5 [get_ports ddr3_dq[0]]
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@ -57,13 +57,12 @@ synth_design -rtl -name rtl_1
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report_clocks -file reports/clocks.rpt
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# this does synthesis? wtf?
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# this does synthesis.
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launch_runs synth_1 -jobs 4
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wait_on_run synth_1
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open_run synth_1
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check_timing -verbose -file reports/check_timing.rpt
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report_timing -max_paths 10 -nworst 10 -delay_type max -sort_by slack -file reports/timing_WORST_10.rpt
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report_timing -nworst 1 -delay_type max -sort_by group -file reports/timing.rpt
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26
fpga/generator/xlnx_mmcm.tcl
Normal file
26
fpga/generator/xlnx_mmcm.tcl
Normal file
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@ -0,0 +1,26 @@
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set partNumber $::env(XILINX_PART)
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set boardName $::env(XILINX_BOARD)
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set ipName xlnx_mmcm
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create_project $ipName . -force -part $partNumber
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set_property board_part $boardName [current_project]
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create_ip -name clk_wiz -vendor xilinx.com -library ip -module_name $ipName
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set_property -dict [list CONFIG.PRIM_IN_FREQ {100.000} \
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CONFIG.NUM_OUT_CLKS {3} \
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CONFIG.CLKOUT2_USED {true} \
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CONFIG.CLKOUT3_USED {true} \
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CONFIG.CLKOUT4_USED {false} \
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CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {167} \
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CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {200} \
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CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} \
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CONFIG.CLKIN1_JITTER_PS {50.0} \
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] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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launch_run -jobs 8 ${ipName}_synth_1
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wait_on_run ${ipName}_synth_1
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