Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally

pipelined/src/fpu/flags.sv

@@ -24,6 +24,7 @@ module flags(
     input logic  [1:0]          NegResMSBS,             // the negitive integer result's most significant bits
     input logic                 ZSgnEffM, PSgnM,        // the product and modified Z signs
     input logic                 Round, UfLSBRes, Sticky, UfPlus1, // bits used to determine rounding
+    output logic                DivByZero,
     output logic                IntInvalid, Invalid, Overflow, Underflow, // flags used to select the res
     output logic [4:0]          PostProcFlgM // flags
 );
@@ -33,7 +34,6 @@ module flags(
     logic               IntInexact; // integer inexact flag
     logic               FmaInvalid; // integer invalid flag
     logic               DivInvalid; // integer invalid flag
-    logic               DivByZero;
     logic               ResExpGteMax; // is the result greater than or equal to the maximum floating point expoent
     logic               ShiftGtIntSz; // is the shift greater than the the integer size (use ResExp to account for possible roundning "shift")
 

pipelined/src/fpu/postprocess.sv

@@ -104,6 +104,7 @@ module postprocess(
     logic ResSgn;
     logic RoundSgn;
     logic NaNIn;
+    logic DivByZero;
     logic UfLSBRes;
     logic Sqrt;
     logic [`FMTBITS-1:0] OutFmt;
@@ -194,7 +195,7 @@ module postprocess(
 
     flags flags(.XSNaNM, .YSNaNM, .ZSNaNM, .XInfM, .YInfM, .ZInfM, .InfIn, .XZeroM, .YZeroM, 
                 .XSgnM, .Sqrt, .ToInt, .IntToFp, .Int64, .Signed, .OutFmt, .CvtCalcExpM,
-                .XNaNM, .YNaNM, .NaNIn, .ZSgnEffM, .PSgnM, .Round, .IntInvalid,
+                .XNaNM, .YNaNM, .NaNIn, .ZSgnEffM, .PSgnM, .Round, .IntInvalid, .DivByZero,
                 .UfLSBRes, .Sticky, .UfPlus1, .CvtOp, .DivOp, .FmaOp, .FullResExp, .Plus1,
                 .RoundExp, .NegResMSBS, .Invalid, .Overflow, .Underflow, .PostProcFlgM);
 
@@ -205,6 +206,6 @@ module postprocess(
     resultselect resultselect(.XSgnM, .ZExpM, .XManM, .YManM, .ZManM, .ZDenormM, .ZZeroM, .XZeroM, .IntInvalid,
         .IntZeroM, .FrmM, .OutFmt, .AddendStickyM, .KillProdM, .XNaNM, .YNaNM, .ZNaNM, .RoundAdd, .CvtResUf, 
         .NaNIn, .IntToFp, .Int64, .Signed, .CvtOp, .FmaOp, .Plus1, .Invalid, .Overflow, .InfIn, .NegResMSBS,
-        .FullResExp, .Shifted, .CvtCalcExpM, .ResSgn, .ResExp, .ResFrac, .PostProcResM, .FCvtIntResM);
+        .DivByZero, .FullResExp, .Shifted, .CvtCalcExpM, .ResSgn, .ResExp, .ResFrac, .PostProcResM, .FCvtIntResM);
 
 endmodule

pipelined/src/fpu/resultselect.sv

@@ -17,6 +17,7 @@ module resultselect(
     input logic [`NORMSHIFTSZ-1:0]             Shifted,        // is the sum zero
     input logic                     FmaOp,
     input logic                     Plus1,
+    input logic                     DivByZero,
     input logic [`NE:0]             CvtCalcExpM,    // the calculated expoent
     input logic                     AddendStickyM,  // sticky bit that is calculated during alignment
     input logic                     KillProdM,      // set the product to zero before addition if the product is too small to matter
@@ -218,18 +219,19 @@ module resultselect(
     //      - dont set to zero if int input is zero but not using the int input
     assign KillRes = CvtOp ? (CvtResUf|(XZeroM&~IntToFp)|(IntZeroM&IntToFp)) : FullResExp[`NE+1];//Underflow & ~ResDenorm & (ResExp!=1);
 
+    // output infinity with result sign if divide by zero
     if(`IEEE754) begin
         assign PostProcResM = XNaNM&~(IntToFp&CvtOp) ? XNaNRes :
                          YNaNM&~CvtOp ? YNaNRes :
                          ZNaNM&FmaOp ? ZNaNRes :
                          Invalid ? InvalidRes : 
-                         Overflow|InfIn ? OfRes :
+                         Overflow|DivByZero|InfIn ? OfRes :
                          KillProdM&FmaOp ? KillProdRes : 
                          KillRes ? UfRes :  
                          NormRes;
     end else begin
         assign PostProcResM = NaNIn|Invalid ? InvalidRes :
-                         Overflow|InfIn ? OfRes :
+                         Overflow|DivByZero|InfIn ? OfRes :
                          KillProdM&FmaOp ? KillProdRes :  
                          KillRes ? UfRes :  
                          NormRes;