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modified synth script to take config from outputdir

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This commit is contained in:
Shreya Sanghai 2022-03-07 17:12:43 +00:00
parent 4d8e0ecf29
commit 31f17d2bf3
2 changed files with 3 additions and 3 deletions
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2
synthDC/Makefile
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@ -39,7 +39,7 @@ rv%.log: rv%
echo $<
DIRS = rv32e rv32gc rv64ic rv64gc rv32ic
DIRS = rv32e #rv32gc rv64ic rv64gc rv32ic
# DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic
# CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig

4
synthDC/scripts/synth.tcl
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@ -22,7 +22,7 @@ set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh"
set saifpower $::env(SAIFPOWER)
set maxopt $::env(MAXOPT)
eval file copy -force ${cfg} {hdl/}
# eval file copy -force ${cfg} {hdl/}
eval file copy -force ${cfg} $outputDir
eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/}
@ -34,7 +34,7 @@ if { $saifpower == 1 } {
}
# Verilog files
set my_verilog_files [glob hdl/*]
set my_verilog_files [glob hdl/* outputDir/wally-config.vh]
# Set toplevel
set my_toplevel $::env(DESIGN)