github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-06-27 17:01:20 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Creating separate test for instruction misaligned page fault.

Browse source
This commit is contained in:
Rose Thompson 2025-05-07 16:26:26 -05:00
parent 03653f0336
commit 33a10fd017
1 changed files with 7 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

14
tests/coverage/misalignedStoreSpill.S
View file

@ -52,14 +52,15 @@ main:
.align 6 # start on multiple of 64 bytes / 16 instruction cache line
label1:
# test 1
li t0, 0xdeadbeef01234567
sfence.vma # flush tlb
sd t0, 0x0(a0) # load to get an entry in the DTLB accessing top-level PTE
# test 2
li a1, 4096
add a0, a0, a1
sd t0, 0(a0) # cause a store page fault to the second half of the access. mtval should be updated to the address of the second half.
# wrap up
li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
@ -67,7 +68,6 @@ label1:
j done
.data
.align 16
@ -80,7 +80,7 @@ pagetable:
.align 12
.8byte 0x000000000000100F # misaligned gigapage at 0x00000000
.8byte 0x0000000020005801 # PTE for pages at 0x40000000
.8byte 0x0000000020004801 # gigapage at 0x80000000 pointing to 0x80120000
.8byte 0x0000000020004801 #
# Next page table at 0x80012000 for gigapage at 0x80000000
@ -152,7 +152,7 @@ pagetable:
.8byte 0x80000000200060CF
.8byte 0x80000000200060CF
.8byte 0x80000000200060CF
.8byte 0x80000000200060CF # A
.8byte 0x80000000200060CF
.8byte 0x80000000200060CF
.8byte 0x80000000200060CF
@ -162,8 +162,8 @@ pagetable:
.8byte 0x80000000200060CF
.8byte 0x80000000200060CF
.8byte 0x80000000200060CF
.8byte 0x80000000200060CF
.8byte 0x80000000200060CF # e0
.8byte 0x00000000200060CF # e8
.8byte 0x80000000200060CF
.8byte 0x80000000200060CF