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https://github.com/openhwgroup/cvw.git
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
This commit is contained in:
David Harris
commit
35cd4e1d6c
1 changed files with 92 additions and 112 deletions
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@ -83,7 +83,7 @@ module testbenchfp;
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logic [P.LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
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logic [P.DIVb:0] Quot;
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logic CvtResSubnormUfE;
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logic DivStart;
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logic DivStart=0;
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logic FDivBusyE;
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logic OldFDivBusyE;
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logic reset = 1'b0;
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@ -120,7 +120,11 @@ module testbenchfp;
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logic ResMatch; // Check if result match
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logic FlagMatch; // Check if IEEE flags match
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logic CheckNow; // Final check
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logic FMAop; // Is this a FMA operation?
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logic FMAop; // Is this a FMA operation?
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// FSM for testing each item per clock
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typedef enum logic [2:0] {S0, Start, S2, Done} statetype;
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statetype state, nextstate;
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///////////////////////////////////////////////////////////////////////////////////////////////
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@ -676,7 +680,7 @@ module testbenchfp;
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.VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA,
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.Xs, .Ys, .Zs, .Unit(UnitVal),
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.Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
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.Xm, .Ym, .Zm, .DivStart,
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.Xm, .Ym, .Zm,
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.XNaN, .YNaN, .ZNaN,
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.XSNaN, .YSNaN, .ZSNaN,
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.XSubnorm, .ZSubnorm,
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@ -748,16 +752,6 @@ module testbenchfp;
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clk = 1; #5; clk = 0; #5;
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end
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// Provide reset for divsqrt to reset state to IDLE
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// Previous version did not initiate a divide due to missing state
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// information. This starts the FSM by putting the fdivsqrt into
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// the IDLE state.
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initial
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begin
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#0 reset = 1'b1;
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#25 reset = 1'b0;
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end
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///////////////////////////////////////////////////////////////////////////////////////////////
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// ||||| ||| |||||||||| ||||| |||
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@ -835,45 +829,64 @@ module testbenchfp;
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`CMPUNIT: ResFlg = CmpFlg;
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`CVTINTUNIT: ResFlg = Flg;
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`CVTFPUNIT: ResFlg = Flg;
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endcase
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end
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endcase
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// Use four state test sequence to handle div properly.
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// Four states should allow other operations to finish
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// properly and within time.
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case (state)
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S0: begin
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DivStart = 1'b0;
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nextstate = Start;
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end
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Start: begin
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if (UnitVal == `DIVUNIT)
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DivStart = 1'b1;
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else
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DivStart = 1'b0;
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nextstate = S2;
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end
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S2: begin
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DivStart = 1'b0;
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if ((FDivBusyE)|(~DivDone))
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nextstate = S2;
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else
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nextstate = Done;
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end
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Done: begin
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DivStart = 1'b0;
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nextstate = S0;
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end
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endcase // case (state)
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end
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// Provide reset for divsqrt to reset state
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initial
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begin
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#0 reset = 1'b1;
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#25 reset = 1'b0;
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end
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// Left-over from before - will remove soon
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always @(posedge clk)
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OldFDivBusyE = FDivDoneE;
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// For FP division this adds extra clock cycles to make sure the
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// computation completes.
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// state machine to handle timing for testing due
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// various cycle counts for different fp/int operations
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// Adds vector at start of clock
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always @(posedge clk) begin
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// Add extra clock cycles in beginning for fdivsqrt to adequate reset state
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if (~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin
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// This allows specific number of clocks to allow each vector
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// to complete for division or square root. It is an
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// arbitrary value and can be changed, if needed.
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case (FmtVal)
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// QP
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2'b11: begin
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repeat (20)
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@(posedge clk);
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end
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// HP
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2'b10: begin
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repeat (14)
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@(posedge clk);
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end
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// DP
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2'b01: begin
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repeat (18)
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@(posedge clk);
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end
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// SP
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2'b00: begin
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repeat (16)
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@(posedge clk);
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end
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endcase // case (FmtVal)
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if (reset != 1'b1)
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VectorNum += 1; // increment the vector
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end
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// state machine element for testing
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if (reset)
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state <= S0;
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else
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state <= nextstate;
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// Increment the vector when Done with each test
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if (state == Done)
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VectorNum += 1; // increment the vector
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end
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// check results on falling edge of clk
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@ -904,7 +917,7 @@ module testbenchfp;
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(YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) |
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(ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]})));
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endcase
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else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
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else if (UnitVal === `CVTFPUNIT) // if converting from FP to FP OpCtrl contains the final FP format
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case (OpCtrlVal[1:0])
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2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
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(AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
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@ -941,29 +954,22 @@ module testbenchfp;
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///////////////////////////////////////////////////////////////////////////////////////////////
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// check if result is correct
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// wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
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assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx));
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assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
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assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
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assign FMAop = (OpCtrlVal == `FMAUNIT);
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assign DivDone = OldFDivBusyE & ~FDivBusyE;
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// Maybe change OpCtrl but for now just look at TEST for fma test
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assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT);
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if (~(ResMatch & FlagMatch) & CheckNow) begin
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assign CheckNow = ((DivDone | ~divsqrtop) |
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(TEST == "all" | TEST == "add" | TEST == "fma" | TEST == "sub"))
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& (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT);
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if (~(ResMatch & FlagMatch) & CheckNow & (Ans[0] !== 1'bx)) begin
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errors += 1;
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$display("\nError in %s", Tests[TestNum]);
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$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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$stop;
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end else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) &
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~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin // Check for conversion and comparisons
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errors += 1;
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$display("\nError in %s", Tests[TestNum]);
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$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
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$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
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$stop;
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end
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end
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if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof
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// increment the test
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@ -979,11 +985,12 @@ module testbenchfp;
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// increment the rounding mode or loop back to rne
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if (FrmNum < 4) FrmNum += 1;
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else begin
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FrmNum = 0;
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FrmNum = 0;
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// Add some time as a buffer between tests at the end of each test
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repeat (10)
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@(posedge clk);
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end
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// (to be removed)
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repeat (10)
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@(posedge clk);
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end
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// if no more Tests - finish
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if (Tests[TestNum] === "") begin
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$display("\nAll Tests completed with %d errors\n", errors);
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@ -996,28 +1003,27 @@ endmodule
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module readvectors import cvw::*; #(parameter cvw_t P) (
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input logic clk,
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input logic [P.FLEN*4+7:0] TestVector,
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input logic clk,
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input logic [P.FLEN*4+7:0] TestVector,
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input logic [P.FMTBITS-1:0] ModFmt,
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input logic [1:0] Fmt,
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input logic [2:0] Unit,
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input logic [31:0] VectorNum,
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input logic [31:0] TestNum,
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input logic [2:0] OpCtrl,
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output logic [P.FLEN-1:0] Ans,
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output logic [P.XLEN-1:0] SrcA,
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output logic [4:0] AnsFlg,
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output logic Xs, Ys, Zs, // sign bits of XYZ
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output logic [P.NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
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output logic [P.NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
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output logic XNaN, YNaN, ZNaN, // is XYZ a NaN
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output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
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output logic XSubnorm, ZSubnorm, // is XYZ denormalized
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output logic XZero, YZero, ZZero, // is XYZ zero
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output logic XInf, YInf, ZInf, // is XYZ infinity
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output logic XExpMax,
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output logic DivStart,
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output logic [P.FLEN-1:0] X, Y, Z, XPostBox
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input logic [1:0] Fmt,
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input logic [2:0] Unit,
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input logic [31:0] VectorNum,
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input logic [31:0] TestNum,
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input logic [2:0] OpCtrl,
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output logic [P.FLEN-1:0] Ans,
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output logic [P.XLEN-1:0] SrcA,
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output logic [4:0] AnsFlg,
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output logic Xs, Ys, Zs, // sign bits of XYZ
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output logic [P.NE-1:0] Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
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output logic [P.NF:0] Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
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output logic XNaN, YNaN, ZNaN, // is XYZ a NaN
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output logic XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
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output logic XSubnorm, ZSubnorm, // is XYZ denormalized
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output logic XZero, YZero, ZZero, // is XYZ zero
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output logic XInf, YInf, ZInf, // is XYZ infinity
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output logic XExpMax,
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output logic [P.FLEN-1:0] X, Y, Z, XPostBox
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);
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localparam Q_LEN = 32'd128;
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@ -1030,8 +1036,6 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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// apply test vectors on rising edge of clk
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// Format of vectors Inputs(1/2/3)_AnsFlg
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always @(VectorNum) begin
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DivStart = 1'b0;
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#1;
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AnsFlg = TestVector[4:0];
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case (Unit)
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`FMAUNIT:
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@ -1101,30 +1105,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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2'b11: begin // quad
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X = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
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Ans = TestVector[8+(P.Q_LEN-1):8];
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if (~clk) #5;
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DivStart = 1'b1; #10 // one clk cycle
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DivStart = 1'b0;
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end
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2'b01: if (P.D_SUPPORTED) begin // double
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X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
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Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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if (~clk) #5;
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DivStart = 1'b1; #10
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DivStart = 1'b0;
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
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Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
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if (~clk) #5;
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DivStart = 1'b1; #10
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DivStart = 1'b0;
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end
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2'b10: begin // half
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X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
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Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
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if (~clk) #5;
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DivStart = 1'b1; #10
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DivStart = 1'b0;
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end
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endcase
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else
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@ -1133,33 +1125,21 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
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X = TestVector[8+3*(P.Q_LEN)-1:8+2*(P.Q_LEN)];
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Y = TestVector[8+2*(P.Q_LEN)-1:8+(P.Q_LEN)];
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Ans = TestVector[8+(P.Q_LEN-1):8];
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if (~clk) #5;
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DivStart = 1'b1; #10 // one clk cycle
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DivStart = 1'b0;
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end
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2'b01: if (P.D_SUPPORTED) begin // double
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X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+3*(P.D_LEN)-1:8+2*(P.D_LEN)]};
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Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+2*(P.D_LEN)-1:8+(P.D_LEN)]};
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Ans = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+(P.D_LEN-1):8]};
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if (~clk) #5;
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DivStart = 1'b1; #10
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DivStart = 1'b0;
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end
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2'b00: if (P.S_SUPPORTED) begin // single
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X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+3*(P.S_LEN)-1:8+2*(P.S_LEN)]};
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Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+2*(P.S_LEN)-1:8+1*(P.S_LEN)]};
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Ans = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+(P.S_LEN-1):8]};
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if (~clk) #5;
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DivStart = 1'b1; #10
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DivStart = 1'b0;
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end
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2'b10: begin // half
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X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+3*(P.H_LEN)-1:8+2*(P.H_LEN)]};
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Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+2*(P.H_LEN)-1:8+(P.H_LEN)]};
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Ans = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+(P.H_LEN-1):8]};
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if (~clk) #5;
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DivStart = 1'b1; #10
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DivStart = 1'b0;
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end
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endcase
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`CMPUNIT:
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