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Merged AES changes

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This commit is contained in:
David Harris 2024-03-10 19:17:01 -07:00
commit 39ca7093bf
81 changed files with 3459 additions and 137 deletions
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1
.gitignore vendored
View file

@ -42,6 +42,7 @@ tests/linux-testgen/buildroot-image-output
tests/linux-testgen/buildroot-config-src/main.config.old
tests/linux-testgen/buildroot-config-src/linux.config.old
tests/linux-testgen/buildroot-config-src/busybox.config.old
linux/buildroot
linux/testvector-generation/boottrace.S
linux/testvector-generation/boottrace_disasm.log
sim/slack-notifier/slack-webhook-url.txt

9
config/rv32e/config.vh
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@ -179,6 +179,15 @@ localparam ZCA_SUPPORTED = 0;
localparam ZCF_SUPPORTED = 0;
localparam ZCD_SUPPORTED = 0;
// K extension instructions
localparam ZBKB_SUPPORTED = 0;
localparam ZBKC_SUPPORTED = 0;
localparam ZBKX_SUPPORTED = 0;
localparam ZKNE_SUPPORTED = 0;
localparam ZKND_SUPPORTED = 0;
localparam ZK_SUPPORTED = 0;
localparam ZKNH_SUPPORTED = 0;
// Memory synthesis configuration
localparam USE_SRAM = 0;

9
config/rv32gc/config.vh
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@ -180,6 +180,15 @@ localparam ZCA_SUPPORTED = 0;
localparam ZCF_SUPPORTED = 0;
localparam ZCD_SUPPORTED = 0;
// K extension instructions
localparam ZBKB_SUPPORTED = 1;
localparam ZBKC_SUPPORTED = 1;
localparam ZBKX_SUPPORTED = 1;
localparam ZKND_SUPPORTED = 1;
localparam ZKNE_SUPPORTED = 1;
localparam ZKNH_SUPPORTED = 1;
localparam ZK_SUPPORTED = 1;
// Memory synthesis configuration
localparam USE_SRAM = 0;

9
config/rv32i/config.vh
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@ -180,6 +180,15 @@ localparam ZCA_SUPPORTED = 0;
localparam ZCF_SUPPORTED = 0;
localparam ZCD_SUPPORTED = 0;
// K extension instructions
localparam ZBKB_SUPPORTED = 0;
localparam ZBKC_SUPPORTED = 0;
localparam ZBKX_SUPPORTED = 0;
localparam ZKNE_SUPPORTED = 0;
localparam ZKND_SUPPORTED = 0;
localparam ZK_SUPPORTED = 0;
localparam ZKNH_SUPPORTED = 0;
// Memory synthesis configuration
localparam USE_SRAM = 0;

9
config/rv32imc/config.vh
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@ -178,6 +178,15 @@ localparam ZCA_SUPPORTED = 0;
localparam ZCF_SUPPORTED = 0;
localparam ZCD_SUPPORTED = 0;
// K extension instructions
localparam ZBKB_SUPPORTED = 0;
localparam ZBKC_SUPPORTED = 0;
localparam ZBKX_SUPPORTED = 0;
localparam ZKNE_SUPPORTED = 0;
localparam ZKND_SUPPORTED = 0;
localparam ZK_SUPPORTED = 0;
localparam ZKNH_SUPPORTED = 0;
// Memory synthesis configuration
localparam USE_SRAM = 0;

9
config/rv64gc/config.vh
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@ -181,6 +181,15 @@ localparam ZCA_SUPPORTED = 0;
localparam ZCF_SUPPORTED = 0;
localparam ZCD_SUPPORTED = 0;
// K extension instructions
localparam ZBKB_SUPPORTED = 1;
localparam ZBKC_SUPPORTED = 1;
localparam ZBKX_SUPPORTED = 1;
localparam ZKND_SUPPORTED = 1;
localparam ZKNE_SUPPORTED = 1;
localparam ZKNH_SUPPORTED = 1;
localparam ZK_SUPPORTED = 1;
// Memory synthesis configuration
localparam USE_SRAM = 0;

9
config/rv64i/config.vh
View file

@ -181,6 +181,15 @@ localparam ZCA_SUPPORTED = 0;
localparam ZCF_SUPPORTED = 0;
localparam ZCD_SUPPORTED = 0;
// K extension instructions
localparam ZBKB_SUPPORTED = 0;
localparam ZBKC_SUPPORTED = 0;
localparam ZBKX_SUPPORTED = 0;
localparam ZKNE_SUPPORTED = 0;
localparam ZKND_SUPPORTED = 0;
localparam ZK_SUPPORTED = 0;
localparam ZKNH_SUPPORTED = 0;
// Memory synthesis configuration
localparam USE_SRAM = 0;

1
config/shared/config-shared.vh
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@ -29,6 +29,7 @@ localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1);
localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1);
localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1);
localparam I_SUPPORTED = ((MISA >> 8) % 2 == 1);
localparam K_SUPPORTED = ((ZBKB_SUPPORTED | ZBKC_SUPPORTED | ZBKX_SUPPORTED | ZKND_SUPPORTED | ZKNE_SUPPORTED | ZKNH_SUPPORTED));
localparam M_SUPPORTED = ((MISA >> 12) % 2 == 1);
localparam Q_SUPPORTED = ((MISA >> 16) % 2 == 1);
localparam S_SUPPORTED = ((MISA >> 18) % 2 == 1);

8
config/shared/parameter-defs.vh
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@ -113,6 +113,13 @@ localparam cvw_t P = '{
ZCB_SUPPORTED : ZCB_SUPPORTED,
ZCD_SUPPORTED : ZCD_SUPPORTED,
ZCF_SUPPORTED : ZCF_SUPPORTED,
ZBKB_SUPPORTED: ZBKB_SUPPORTED,
ZBKC_SUPPORTED: ZBKC_SUPPORTED,
ZBKX_SUPPORTED: ZBKX_SUPPORTED,
ZKND_SUPPORTED: ZKND_SUPPORTED,
ZKNE_SUPPORTED: ZKNE_SUPPORTED,
ZKNH_SUPPORTED: ZKNH_SUPPORTED,
ZK_SUPPORTED : ZK_SUPPORTED,
USE_SRAM : USE_SRAM,
M_MODE : M_MODE,
S_MODE : S_MODE,
@ -136,6 +143,7 @@ localparam cvw_t P = '{
E_SUPPORTED : E_SUPPORTED,
F_SUPPORTED : F_SUPPORTED,
I_SUPPORTED : I_SUPPORTED,
K_SUPPORTED : K_SUPPORTED,
M_SUPPORTED : M_SUPPORTED,
Q_SUPPORTED : Q_SUPPORTED,
S_SUPPORTED : S_SUPPORTED,

6
sim/regression-wally
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@ -89,7 +89,7 @@ for test in tests64i:
configs.append(tc)
tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph"] # "arch32zbc", "arch32zfad",
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma", "arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph", "arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"] # "arch32zbc", "arch32zfad",
#tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"]
for test in tests32gc:
tc = TestCase(
@ -128,7 +128,7 @@ for test in tests32e:
grepstr="All tests ran without failures")
configs.append(tc)
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad",
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
"arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working
#tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
# "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"]
@ -278,7 +278,7 @@ if (nightly):
["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed
["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i"]],
["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i"]],
["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "wally64q"]],
]

10
src/cvw.sv
View file

@ -180,6 +180,15 @@ typedef struct packed {
logic ZCD_SUPPORTED;
logic ZCF_SUPPORTED;
// Cryptography
logic ZBKB_SUPPORTED;
logic ZBKC_SUPPORTED;
logic ZBKX_SUPPORTED;
logic ZKND_SUPPORTED;
logic ZKNE_SUPPORTED;
logic ZKNH_SUPPORTED;
logic ZK_SUPPORTED;
// Memory synthesis configuration
logic USE_SRAM;
@ -214,6 +223,7 @@ typedef struct packed {
logic E_SUPPORTED;
logic F_SUPPORTED;
logic I_SUPPORTED;
logic K_SUPPORTED;
logic M_SUPPORTED;
logic Q_SUPPORTED;
logic S_SUPPORTED;

9
src/generic/mux.sv
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@ -65,6 +65,15 @@ module mux6 #(parameter WIDTH = 8) (
output logic [WIDTH-1:0] y);
assign y = s[2] ? (s[0] ? d5 : d4) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
endmodule // mux6
module mux7 #(parameter WIDTH = 8) (
input logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6,
input logic [2:0] s,
output logic [WIDTH-1:0] y);
assign y = s[2] ? (s[1] ? d6 : (s[0] ? d5 : d4)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0));
endmodule
/* verilator lint_on DECLFILENAME */

46
src/ieu/aes_common/aesinvmixcolumns.sv Normal file
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@ -0,0 +1,46 @@
///////////////////////////////////////////
// aesinvmixcolumns.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 05 March 2024
//
// Purpose: AES Inverted Mix Column Function for use with AES
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvmixcolumns(input logic [31:0] in, output logic [31:0] out);
logic [7:0] in0, in1, in2, in3, temp;
logic [10:0] xor0, xor1, xor2, xor3;
assign {in0, in1, in2, in3} = in;
assign temp = in0 ^ in1 ^ in2 ^ in3;
assign xor0 = {temp, 3'b0} ^ {1'b0, in3^in1, 2'b0} ^ {2'b0, in3^in2, 1'b0} ^ {3'b0, temp} ^ {3'b0, in3};
assign xor1 = {temp, 3'b0} ^ {1'b0, in2^in0, 2'b0} ^ {2'b0, in2^in1, 1'b0} ^ {3'b0, temp} ^ {3'b0, in2};
assign xor2 = {temp, 3'b0} ^ {1'b0, in1^in3, 2'b0} ^ {2'b0, in1^in0, 1'b0} ^ {3'b0, temp} ^ {3'b0, in1};
assign xor3 = {temp, 3'b0} ^ {1'b0, in0^in2, 2'b0} ^ {2'b0, in0^in3, 1'b0} ^ {3'b0, temp} ^ {3'b0, in0};
galoismultinverse gm0 (xor0, out[7:0]);
galoismultinverse gm1 (xor1, out[15:8]);
galoismultinverse gm2 (xor2, out[23:16]);
galoismultinverse gm3 (xor3, out[31:24]);
endmodule

292
src/ieu/aes_common/aesinvsbox.sv Normal file
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@ -0,0 +1,292 @@
///////////////////////////////////////////
// aesinvsbox.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: Rinjdael Inverted S-BOX in form of a LUT
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvsbox(input logic [7:0] in, output logic [7:0] out);
always_comb
begin
case(in)
8'h00 : out = 8'h52;
8'h01 : out = 8'h09;
8'h02 : out = 8'h6A;
8'h03 : out = 8'hD5;
8'h04 : out = 8'h30;
8'h05 : out = 8'h36;
8'h06 : out = 8'hA5;
8'h07 : out = 8'h38;
8'h08 : out = 8'hBF;
8'h09 : out = 8'h40;
8'h0A : out = 8'hA3;
8'h0B : out = 8'h9E;
8'h0C : out = 8'h81;
8'h0D : out = 8'hF3;
8'h0E : out = 8'hD7;
8'h0F : out = 8'hFB;
8'h10 : out = 8'h7C;
8'h11 : out = 8'hE3;
8'h12 : out = 8'h39;
8'h13 : out = 8'h82;
8'h14 : out = 8'h9B;
8'h15 : out = 8'h2F;
8'h16 : out = 8'hFF;
8'h17 : out = 8'h87;
8'h18 : out = 8'h34;
8'h19 : out = 8'h8E;
8'h1A : out = 8'h43;
8'h1B : out = 8'h44;
8'h1C : out = 8'hC4;
8'h1D : out = 8'hDE;
8'h1E : out = 8'hE9;
8'h1F : out = 8'hCB;
8'h20 : out = 8'h54;
8'h21 : out = 8'h7B;
8'h22 : out = 8'h94;
8'h23 : out = 8'h32;
8'h24 : out = 8'hA6;
8'h25 : out = 8'hC2;
8'h26 : out = 8'h23;
8'h27 : out = 8'h3D;
8'h28 : out = 8'hEE;
8'h29 : out = 8'h4C;
8'h2A : out = 8'h95;
8'h2B : out = 8'h0B;
8'h2C : out = 8'h42;
8'h2D : out = 8'hFA;
8'h2E : out = 8'hC3;
8'h2F : out = 8'h4E;
8'h30 : out = 8'h08;
8'h31 : out = 8'h2E;
8'h32 : out = 8'hA1;
8'h33 : out = 8'h66;
8'h34 : out = 8'h28;
8'h35 : out = 8'hD9;
8'h36 : out = 8'h24;
8'h37 : out = 8'hB2;
8'h38 : out = 8'h76;
8'h39 : out = 8'h5B;
8'h3A : out = 8'hA2;
8'h3B : out = 8'h49;
8'h3C : out = 8'h6D;
8'h3D : out = 8'h8B;
8'h3E : out = 8'hD1;
8'h3F : out = 8'h25;
8'h40 : out = 8'h72;
8'h41 : out = 8'hF8;
8'h42 : out = 8'hF6;
8'h43 : out = 8'h64;
8'h44 : out = 8'h86;
8'h45 : out = 8'h68;
8'h46 : out = 8'h98;
8'h47 : out = 8'h16;
8'h48 : out = 8'hD4;
8'h49 : out = 8'hA4;
8'h4A : out = 8'h5C;
8'h4B : out = 8'hCC;
8'h4C : out = 8'h5D;
8'h4D : out = 8'h65;
8'h4E : out = 8'hB6;
8'h4F : out = 8'h92;
8'h50 : out = 8'h6C;
8'h51 : out = 8'h70;
8'h52 : out = 8'h48;
8'h53 : out = 8'h50;
8'h54 : out = 8'hFD;
8'h55 : out = 8'hED;
8'h56 : out = 8'hB9;
8'h57 : out = 8'hDA;
8'h58 : out = 8'h5E;
8'h59 : out = 8'h15;
8'h5A : out = 8'h46;
8'h5B : out = 8'h57;
8'h5C : out = 8'hA7;
8'h5D : out = 8'h8D;
8'h5E : out = 8'h9D;
8'h5F : out = 8'h84;
8'h60 : out = 8'h90;
8'h61 : out = 8'hD8;
8'h62 : out = 8'hAB;
8'h63 : out = 8'h00;
8'h64 : out = 8'h8C;
8'h65 : out = 8'hBC;
8'h66 : out = 8'hD3;
8'h67 : out = 8'h0A;
8'h68 : out = 8'hF7;
8'h69 : out = 8'hE4;
8'h6A : out = 8'h58;
8'h6B : out = 8'h05;
8'h6C : out = 8'hB8;
8'h6D : out = 8'hB3;
8'h6E : out = 8'h45;
8'h6F : out = 8'h06;
8'h70 : out = 8'hD0;
8'h71 : out = 8'h2C;
8'h72 : out = 8'h1E;
8'h73 : out = 8'h8F;
8'h74 : out = 8'hCA;
8'h75 : out = 8'h3F;
8'h76 : out = 8'h0F;
8'h77 : out = 8'h02;
8'h78 : out = 8'hC1;
8'h79 : out = 8'hAF;
8'h7A : out = 8'hBD;
8'h7B : out = 8'h03;
8'h7C : out = 8'h01;
8'h7D : out = 8'h13;
8'h7E : out = 8'h8A;
8'h7F : out = 8'h6B;
8'h80 : out = 8'h3A;
8'h81 : out = 8'h91;
8'h82 : out = 8'h11;
8'h83 : out = 8'h41;
8'h84 : out = 8'h4F;
8'h85 : out = 8'h67;
8'h86 : out = 8'hDC;
8'h87 : out = 8'hEA;
8'h88 : out = 8'h97;
8'h89 : out = 8'hF2;
8'h8A : out = 8'hCF;
8'h8B : out = 8'hCE;
8'h8C : out = 8'hF0;
8'h8D : out = 8'hB4;
8'h8E : out = 8'hE6;
8'h8F : out = 8'h73;
8'h90 : out = 8'h96;
8'h91 : out = 8'hAC;
8'h92 : out = 8'h74;
8'h93 : out = 8'h22;
8'h94 : out = 8'hE7;
8'h95 : out = 8'hAD;
8'h96 : out = 8'h35;
8'h97 : out = 8'h85;
8'h98 : out = 8'hE2;
8'h99 : out = 8'hF9;
8'h9A : out = 8'h37;
8'h9B : out = 8'hE8;
8'h9C : out = 8'h1C;
8'h9D : out = 8'h75;
8'h9E : out = 8'hDF;
8'h9F : out = 8'h6E;
8'hA0 : out = 8'h47;
8'hA1 : out = 8'hF1;
8'hA2 : out = 8'h1A;
8'hA3 : out = 8'h71;
8'hA4 : out = 8'h1D;
8'hA5 : out = 8'h29;
8'hA6 : out = 8'hC5;
8'hA7 : out = 8'h89;
8'hA8 : out = 8'h6F;
8'hA9 : out = 8'hB7;
8'hAA : out = 8'h62;
8'hAB : out = 8'h0E;
8'hAC : out = 8'hAA;
8'hAD : out = 8'h18;
8'hAE : out = 8'hBE;
8'hAF : out = 8'h1B;
8'hB0 : out = 8'hFC;
8'hB1 : out = 8'h56;
8'hB2 : out = 8'h3E;
8'hB3 : out = 8'h4B;
8'hB4 : out = 8'hC6;
8'hB5 : out = 8'hD2;
8'hB6 : out = 8'h79;
8'hB7 : out = 8'h20;
8'hB8 : out = 8'h9A;
8'hB9 : out = 8'hDB;
8'hBA : out = 8'hC0;
8'hBB : out = 8'hFE;
8'hBC : out = 8'h78;
8'hBD : out = 8'hCD;
8'hBE : out = 8'h5A;
8'hBF : out = 8'hF4;
8'hC0 : out = 8'h1F;
8'hC1 : out = 8'hDD;
8'hC2 : out = 8'hA8;
8'hC3 : out = 8'h33;
8'hC4 : out = 8'h88;
8'hC5 : out = 8'h07;
8'hC6 : out = 8'hC7;
8'hC7 : out = 8'h31;
8'hC8 : out = 8'hB1;
8'hC9 : out = 8'h12;
8'hCA : out = 8'h10;
8'hCB : out = 8'h59;
8'hCC : out = 8'h27;
8'hCD : out = 8'h80;
8'hCE : out = 8'hEC;
8'hCF : out = 8'h5F;
8'hD0 : out = 8'h60;
8'hD1 : out = 8'h51;
8'hD2 : out = 8'h7F;
8'hD3 : out = 8'hA9;
8'hD4 : out = 8'h19;
8'hD5 : out = 8'hB5;
8'hD6 : out = 8'h4A;
8'hD7 : out = 8'h0D;
8'hD8 : out = 8'h2D;
8'hD9 : out = 8'hE5;
8'hDA : out = 8'h7A;
8'hDB : out = 8'h9F;
8'hDC : out = 8'h93;
8'hDD : out = 8'hC9;
8'hDE : out = 8'h9C;
8'hDF : out = 8'hEF;
8'hE0 : out = 8'hA0;
8'hE1 : out = 8'hE0;
8'hE2 : out = 8'h3B;
8'hE3 : out = 8'h4D;
8'hE4 : out = 8'hAE;
8'hE5 : out = 8'h2A;
8'hE6 : out = 8'hF5;
8'hE7 : out = 8'hB0;
8'hE8 : out = 8'hC8;
8'hE9 : out = 8'hEB;
8'hEA : out = 8'hBB;
8'hEB : out = 8'h3C;
8'hEC : out = 8'h83;
8'hED : out = 8'h53;
8'hEE : out = 8'h99;
8'hEF : out = 8'h61;
8'hF0 : out = 8'h17;
8'hF1 : out = 8'h2B;
8'hF2 : out = 8'h04;
8'hF3 : out = 8'h7E;
8'hF4 : out = 8'hBA;
8'hF5 : out = 8'h77;
8'hF6 : out = 8'hD6;
8'hF7 : out = 8'h26;
8'hF8 : out = 8'hE1;
8'hF9 : out = 8'h69;
8'hFA : out = 8'h14;
8'hFB : out = 8'h63;
8'hFC : out = 8'h55;
8'hFD : out = 8'h21;
8'hFE : out = 8'h0C;
8'hFF : out = 8'h7D;
endcase
end
endmodule

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///////////////////////////////////////////
// aesinvsboxword.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: 4 sets of Rinjdael Inverse S-BOX for whole word look up
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvsboxword(input logic [31:0] in, output logic [31:0] out);
// Declare the SBOX for (least significant) byte 0 of the input
aesinvsbox sboxb0(.in(in[7:0]), .out(out[7:0]));
// Declare the SBOX for byte 1 of the input
aesinvsbox sboxb1(.in(in[15:8]), .out(out[15:8]));
// Declare the SBOX for byte 2 of the input
aesinvsbox sboxb2(.in(in[23:16]), .out(out[23:16]));
// Declare the SBOX for byte 3 of the input
aesinvsbox sboxb3(.in(in[31:24]), .out(out[31:24]));
endmodule

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///////////////////////////////////////////
// aesinvshiftrow.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: AES Shiftrow
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesinvshiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut);
assign DataOut = {DataIn[31:24], DataIn[55:48], DataIn[79:72], DataIn[103:96],
DataIn[127:120], DataIn[23:16], DataIn[47:40], DataIn[71:64],
DataIn[95:88], DataIn[119:112], DataIn[15:8], DataIn[39:32],
DataIn[63:56], DataIn[87:80], DataIn[111:104], DataIn[7:0]};
endmodule

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///////////////////////////////////////////
// aesmixcolumns.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu
// Created: 20 February 2024
//
// Purpose: Galois field operation to an individual 32-bit word
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesmixcolumns(input logic [31:0] in, output logic [31:0] out);
logic [7:0] in0, in1, in2, in3, out0, out1, out2, out3, t0, t1, t2, t3, temp;
assign {in0, in1, in2, in3} = in;
assign temp = in0 ^ in1 ^ in2 ^ in3;
galoismultforward gm0 (in0^in1, t0);
galoismultforward gm1 (in1^in2, t1);
galoismultforward gm2 (in2^in3, t2);
galoismultforward gm3 (in3^in0, t3);
assign out0 = in0 ^ temp ^ t3;
assign out1 = in1 ^ temp ^ t0;
assign out2 = in2 ^ temp ^ t1;
assign out3 = in3 ^ temp ^ t2;
assign out = {out0, out1, out2, out3};
endmodule

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///////////////////////////////////////////
// aessbox.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: Rinjdael forward S-BOX in the form of a LUT
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aessbox(input logic [7:0] in, output logic [7:0] out);
// case statement to lookup the value in the rijndael table
always_comb
begin
case(in)
8'h00 : out = 8'h63;
8'h01 : out = 8'h7C;
8'h02 : out = 8'h77;
8'h03 : out = 8'h7B;
8'h04 : out = 8'hF2;
8'h05 : out = 8'h6B;
8'h06 : out = 8'h6F;
8'h07 : out = 8'hC5;
8'h08 : out = 8'h30;
8'h09 : out = 8'h01;
8'h0A : out = 8'h67;
8'h0B : out = 8'h2B;
8'h0C : out = 8'hFE;
8'h0D : out = 8'hD7;
8'h0E : out = 8'hAB;
8'h0F : out = 8'h76;
8'h10 : out = 8'hCA;
8'h11 : out = 8'h82;
8'h12 : out = 8'hC9;
8'h13 : out = 8'h7D;
8'h14 : out = 8'hFA;
8'h15 : out = 8'h59;
8'h16 : out = 8'h47;
8'h17 : out = 8'hF0;
8'h18 : out = 8'hAD;
8'h19 : out = 8'hD4;
8'h1A : out = 8'hA2;
8'h1B : out = 8'hAF;
8'h1C : out = 8'h9C;
8'h1D : out = 8'hA4;
8'h1E : out = 8'h72;
8'h1F : out = 8'hC0;
8'h20 : out = 8'hB7;
8'h21 : out = 8'hFD;
8'h22 : out = 8'h93;
8'h23 : out = 8'h26;
8'h24 : out = 8'h36;
8'h25 : out = 8'h3F;
8'h26 : out = 8'hF7;
8'h27 : out = 8'hCC;
8'h28 : out = 8'h34;
8'h29 : out = 8'hA5;
8'h2A : out = 8'hE5;
8'h2B : out = 8'hF1;
8'h2C : out = 8'h71;
8'h2D : out = 8'hD8;
8'h2E : out = 8'h31;
8'h2F : out = 8'h15;
8'h30 : out = 8'h04;
8'h31 : out = 8'hC7;
8'h32 : out = 8'h23;
8'h33 : out = 8'hC3;
8'h34 : out = 8'h18;
8'h35 : out = 8'h96;
8'h36 : out = 8'h05;
8'h37 : out = 8'h9A;
8'h38 : out = 8'h07;
8'h39 : out = 8'h12;
8'h3A : out = 8'h80;
8'h3B : out = 8'hE2;
8'h3C : out = 8'hEB;
8'h3D : out = 8'h27;
8'h3E : out = 8'hB2;
8'h3F : out = 8'h75;
8'h40 : out = 8'h09;
8'h41 : out = 8'h83;
8'h42 : out = 8'h2C;
8'h43 : out = 8'h1A;
8'h44 : out = 8'h1B;
8'h45 : out = 8'h6E;
8'h46 : out = 8'h5A;
8'h47 : out = 8'hA0;
8'h48 : out = 8'h52;
8'h49 : out = 8'h3B;
8'h4A : out = 8'hD6;
8'h4B : out = 8'hB3;
8'h4C : out = 8'h29;
8'h4D : out = 8'hE3;
8'h4E : out = 8'h2F;
8'h4F : out = 8'h84;
8'h50 : out = 8'h53;
8'h51 : out = 8'hD1;
8'h52 : out = 8'h00;
8'h53 : out = 8'hED;
8'h54 : out = 8'h20;
8'h55 : out = 8'hFC;
8'h56 : out = 8'hB1;
8'h57 : out = 8'h5B;
8'h58 : out = 8'h6A;
8'h59 : out = 8'hCB;
8'h5A : out = 8'hBE;
8'h5B : out = 8'h39;
8'h5C : out = 8'h4A;
8'h5D : out = 8'h4C;
8'h5E : out = 8'h58;
8'h5F : out = 8'hCF;
8'h60 : out = 8'hD0;
8'h61 : out = 8'hEF;
8'h62 : out = 8'hAA;
8'h63 : out = 8'hFB;
8'h64 : out = 8'h43;
8'h65 : out = 8'h4D;
8'h66 : out = 8'h33;
8'h67 : out = 8'h85;
8'h68 : out = 8'h45;
8'h69 : out = 8'hF9;
8'h6A : out = 8'h02;
8'h6B : out = 8'h7F;
8'h6C : out = 8'h50;
8'h6D : out = 8'h3C;
8'h6E : out = 8'h9F;
8'h6F : out = 8'hA8;
8'h70 : out = 8'h51;
8'h71 : out = 8'hA3;
8'h72 : out = 8'h40;
8'h73 : out = 8'h8F;
8'h74 : out = 8'h92;
8'h75 : out = 8'h9D;
8'h76 : out = 8'h38;
8'h77 : out = 8'hF5;
8'h78 : out = 8'hBC;
8'h79 : out = 8'hB6;
8'h7A : out = 8'hDA;
8'h7B : out = 8'h21;
8'h7C : out = 8'h10;
8'h7D : out = 8'hFF;
8'h7E : out = 8'hF3;
8'h7F : out = 8'hD2;
8'h80 : out = 8'hCD;
8'h81 : out = 8'h0C;
8'h82 : out = 8'h13;
8'h83 : out = 8'hEC;
8'h84 : out = 8'h5F;
8'h85 : out = 8'h97;
8'h86 : out = 8'h44;
8'h87 : out = 8'h17;
8'h88 : out = 8'hC4;
8'h89 : out = 8'hA7;
8'h8A : out = 8'h7E;
8'h8B : out = 8'h3D;
8'h8C : out = 8'h64;
8'h8D : out = 8'h5D;
8'h8E : out = 8'h19;
8'h8F : out = 8'h73;
8'h90 : out = 8'h60;
8'h91 : out = 8'h81;
8'h92 : out = 8'h4F;
8'h93 : out = 8'hDC;
8'h94 : out = 8'h22;
8'h95 : out = 8'h2A;
8'h96 : out = 8'h90;
8'h97 : out = 8'h88;
8'h98 : out = 8'h46;
8'h99 : out = 8'hEE;
8'h9A : out = 8'hB8;
8'h9B : out = 8'h14;
8'h9C : out = 8'hDE;
8'h9D : out = 8'h5E;
8'h9E : out = 8'h0B;
8'h9F : out = 8'hDB;
8'hA0 : out = 8'hE0;
8'hA1 : out = 8'h32;
8'hA2 : out = 8'h3A;
8'hA3 : out = 8'h0A;
8'hA4 : out = 8'h49;
8'hA5 : out = 8'h06;
8'hA6 : out = 8'h24;
8'hA7 : out = 8'h5C;
8'hA8 : out = 8'hC2;
8'hA9 : out = 8'hD3;
8'hAA : out = 8'hAC;
8'hAB : out = 8'h62;
8'hAC : out = 8'h91;
8'hAD : out = 8'h95;
8'hAE : out = 8'hE4;
8'hAF : out = 8'h79;
8'hB0 : out = 8'hE7;
8'hB1 : out = 8'hC8;
8'hB2 : out = 8'h37;
8'hB3 : out = 8'h6D;
8'hB4 : out = 8'h8D;
8'hB5 : out = 8'hD5;
8'hB6 : out = 8'h4E;
8'hB7 : out = 8'hA9;
8'hB8 : out = 8'h6C;
8'hB9 : out = 8'h56;
8'hBA : out = 8'hF4;
8'hBB : out = 8'hEA;
8'hBC : out = 8'h65;
8'hBD : out = 8'h7A;
8'hBE : out = 8'hAE;
8'hBF : out = 8'h08;
8'hC0 : out = 8'hBA;
8'hC1 : out = 8'h78;
8'hC2 : out = 8'h25;
8'hC3 : out = 8'h2E;
8'hC4 : out = 8'h1C;
8'hC5 : out = 8'hA6;
8'hC6 : out = 8'hB4;
8'hC7 : out = 8'hC6;
8'hC8 : out = 8'hE8;
8'hC9 : out = 8'hDD;
8'hCA : out = 8'h74;
8'hCB : out = 8'h1F;
8'hCC : out = 8'h4B;
8'hCD : out = 8'hBD;
8'hCE : out = 8'h8B;
8'hCF : out = 8'h8A;
8'hD0 : out = 8'h70;
8'hD1 : out = 8'h3E;
8'hD2 : out = 8'hB5;
8'hD3 : out = 8'h66;
8'hD4 : out = 8'h48;
8'hD5 : out = 8'h03;
8'hD6 : out = 8'hF6;
8'hD7 : out = 8'h0E;
8'hD8 : out = 8'h61;
8'hD9 : out = 8'h35;
8'hDA : out = 8'h57;
8'hDB : out = 8'hB9;
8'hDC : out = 8'h86;
8'hDD : out = 8'hC1;
8'hDE : out = 8'h1D;
8'hDF : out = 8'h9E;
8'hE0 : out = 8'hE1;
8'hE1 : out = 8'hF8;
8'hE2 : out = 8'h98;
8'hE3 : out = 8'h11;
8'hE4 : out = 8'h69;
8'hE5 : out = 8'hD9;
8'hE6 : out = 8'h8E;
8'hE7 : out = 8'h94;
8'hE8 : out = 8'h9B;
8'hE9 : out = 8'h1E;
8'hEA : out = 8'h87;
8'hEB : out = 8'hE9;
8'hEC : out = 8'hCE;
8'hED : out = 8'h55;
8'hEE : out = 8'h28;
8'hEF : out = 8'hDF;
8'hF0 : out = 8'h8C;
8'hF1 : out = 8'hA1;
8'hF2 : out = 8'h89;
8'hF3 : out = 8'h0D;
8'hF4 : out = 8'hBF;
8'hF5 : out = 8'hE6;
8'hF6 : out = 8'h42;
8'hF7 : out = 8'h68;
8'hF8 : out = 8'h41;
8'hF9 : out = 8'h99;
8'hFA : out = 8'h2D;
8'hFB : out = 8'h0F;
8'hFC : out = 8'hB0;
8'hFD : out = 8'h54;
8'hFE : out = 8'hBB;
8'hFF : out = 8'h16;
endcase
end
endmodule

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///////////////////////////////////////////
// aessboxword.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: 4 sets of Rijndael S-BOX so whole word can be looked up simultaneously.
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aessboxword(input logic [31:0] in, output logic [31:0] out);
// Declare the SBOX for (least significant) byte 0 of the input
aessbox sboxb0(.in(in[7:0]), .out(out[7:0]));
// Declare the SBOX for byte 1 of the input
aessbox sboxb1(.in(in[15:8]), .out(out[15:8]));
// Declare the SBOX for byte 2 of the input
aessbox sboxb2(.in(in[23:16]), .out(out[23:16]));
// Declare the SBOX for byte 3 of the input
aessbox sboxb3(.in(in[31:24]), .out(out[31:24]));
endmodule

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///////////////////////////////////////////
// aesshiftrow.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aesshiftrow for taking in first Data line
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aesshiftrow(input logic [127:0] DataIn, output logic [127:0] DataOut);
assign DataOut = {DataIn[95:88], DataIn[55:48], DataIn[15:8], DataIn[103:96],
DataIn[63:56], DataIn[23:16], DataIn[111:104], DataIn[71:64],
DataIn[31:24], DataIn[119:112], DataIn[79:72], DataIn[39:32],
DataIn[127:120], DataIn[87:80], DataIn[47:40], DataIn[7:0]};
endmodule

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///////////////////////////////////////////
// galoismultforward.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu, David_Harris@hmc.edu
// Created: 20 February 2024
//
// Purpose: Galois field operations for mix columns operation
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module galoismultforward(input logic [7:0] in, output logic [7:0] out);
logic [7:0] leftshift;
assign leftshift = {in[6:0], 1'b0};
assign out = in[7] ? (leftshift ^ 8'b00011011) : leftshift;
endmodule

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///////////////////////////////////////////
// galoismultinverse.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: Galois field operations for mix columns operation
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module galoismultinverse(input logic [10:0] in, output logic [7:0] out);
logic [7:0] temp0, temp1;
assign temp0 = in[8] ? (in[7:0] ^ 8'b00011011) : in[7:0];
assign temp1 = in[9] ? (temp0 ^ 8'b00110110) : temp0;
assign out = in[10] ? (temp1 ^ 8'b01101100) : temp1;
endmodule

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///////////////////////////////////////////
// aes32dsi.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes32dsi instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes32dsi(input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut);
// Declare Intermediary logic
logic [4:0] shamt;
logic [31:0] SboxIn32;
logic [7:0] SboxIn;
logic [7:0] SboxOut;
logic [31:0] so;
logic [31:0] sorotate;
// shamt = bs * 8
assign shamt = {bs, 3'b0};
// Shift rs2 right by shamt and take the lower byte
assign SboxIn32 = (rs2 >> shamt);
assign SboxIn = SboxIn32[7:0];
// Apply inverse sbox to si
aesinvsbox inv_sbox(.in(SboxIn), .out(SboxOut));
// Pad output of inverse substitution box
assign so = {24'h0, SboxOut};
// Rotate the substitution box output left by shamt (bs * 8)
assign sorotate = (so << shamt) | (so >> (32 - shamt));
// Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));"
assign DataOut = rs1 ^ sorotate;
endmodule

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///////////////////////////////////////////
// aes32dsmi.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes32dsmi instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes32dsmi(input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut);
// Declare Intermediary logic
logic [4:0] shamt;
logic [31:0] SboxIn32;
logic [7:0] SboxIn;
logic [7:0] SboxOut;
logic [31:0] so;
logic [31:0] mixed;
logic [31:0] mixedrotate;
// shamt = bs * 8
assign shamt = {bs, 3'b0};
// Shift rs2 right by shamt and take the lower byte
assign SboxIn32 = (rs2 >> shamt);
assign SboxIn = SboxIn32[7:0];
// Apply inverse sbox to si
aesinvsbox inv_sbox(.in(SboxIn), .out(SboxOut));
// Pad output of inverse substitution box
assign so = {24'h0, SboxOut};
// Run so through the mixword AES function
aesinvmixcolumns mix(.in(so), .out(mixed));
// Rotate the substitution box output left by shamt (bs * 8)
assign mixedrotate = (mixed << shamt) | (mixed >> (32 - shamt));
// Set result to "X(rs1)[31..0] ^ rol32(so, unsigned(shamt));"
assign DataOut = rs1 ^ mixedrotate;
endmodule

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///////////////////////////////////////////
// aes32esi.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes32esi instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes32esi(input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut);
// Declare Intermediary logic
logic [4:0] shamt;
logic [31:0] SboxIn32;
logic [7:0] SboxIn;
logic [7:0] SboxOut;
logic [31:0] so;
logic [31:0] sorotate;
// Shift bs by 3 to get shamt
assign shamt = {bs, 3'b0};
// Shift rs2 right by shamt to get sbox input
assign SboxIn32 = (rs2 >> shamt);
// Take the bottom byte as an input to the substitution box
assign SboxIn = SboxIn32[7:0];
// Substitute
aessbox subbox(.in(SboxIn), .out(SboxOut));
// Pad sbox output
assign so = {24'h0, SboxOut};
// Rotate so left by shamt
assign sorotate = (so << shamt) | (so >> (32 - shamt));
// Set result X(rs1)[31..0] ^ rol32(so, unsigned(shamt));
assign DataOut = rs1 ^ sorotate;
endmodule

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///////////////////////////////////////////
// aes32esmi.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes32esmi instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes32esmi(input logic [1:0] bs,
input logic [31:0] rs1,
input logic [31:0] rs2,
output logic [31:0] DataOut);
// Declare Intermediary logic
logic [4:0] shamt;
logic [31:0] SboxIn32;
logic [7:0] SboxIn;
logic [7:0] SboxOut;
logic [31:0] so;
logic [31:0] mixed;
logic [31:0] mixedrotate;
// Shift bs by 3 to get shamt
assign shamt = {bs, 3'b0};
// Shift rs2 right by shamt to get sbox input
assign SboxIn32 = (rs2 >> shamt);
// Take the bottom byte as an input to the substitution box
assign SboxIn = SboxIn32[7:0];
// Substitute
aessbox sbox(.in(SboxIn), .out(SboxOut));
// Pad sbox output
assign so = {24'h0, SboxOut};
// Mix Word using aesmixword component
aesmixcolumns mwd(.in(so), .out(mixed));
// Rotate so left by shamt
assign mixedrotate = (mixed << shamt) | (mixed >> (32 - shamt));
// Set result X(rs1)[31..0] ^ rol32(mixed, unsigned(shamt));
assign DataOut = rs1 ^ mixedrotate;
endmodule

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///////////////////////////////////////////
// aes64ds.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes64ds instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes64ds(input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] DataOut);
// Intermediary Logic
logic [127:0] ShiftRowOut;
logic [31:0] SboxOut0;
logic [31:0] SboxOut1;
// Apply inverse shiftrows to rs2 and rs1
aesinvshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut));
// Apply full word inverse substitution to lower 2 words of shiftrow out
aesinvsboxword inv_sbox_0(.in(ShiftRowOut[31:0]), .out(SboxOut0));
aesinvsboxword inv_sbox_1(.in(ShiftRowOut[63:32]), .out(SboxOut1));
// Concatenate the two substitution outputs to get result
assign DataOut = {SboxOut1, SboxOut0};
endmodule

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///////////////////////////////////////////
// aes64dsm.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes64dsm instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes64dsm(input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] DataOut);
// Intermediary Logic
logic [127:0] ShiftRowOut;
logic [31:0] SboxOut0;
logic [31:0] SboxOut1;
logic [31:0] MixcolOut0;
logic [31:0] MixcolOut1;
// Apply inverse shiftrows to rs2 and rs1
aesinvshiftrow srow(.DataIn({rs2, rs1}), .DataOut(ShiftRowOut));
// Apply full word inverse substitution to lower 2 words of shiftrow out
aesinvsboxword invsbox0(.in(ShiftRowOut[31:0]), .out(SboxOut0));
aesinvsboxword invsbox1(.in(ShiftRowOut[63:32]), .out(SboxOut1));
// Apply inverse mixword to sbox outputs
aesinvmixcolumns invmw0(.in(SboxOut0), .out(MixcolOut0));
aesinvmixcolumns invmw1(.in(SboxOut1), .out(MixcolOut1));
// Concatenate mixed words for output
assign DataOut = {MixcolOut1, MixcolOut0};
endmodule

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///////////////////////////////////////////
// aes64es.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes64es instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes64es(input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] DataOut);
// Intermediary Signals
logic [127:0] ShiftRowOut;
// AES shiftrow unit
aesshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut));
// Apply substitution box to 2 lower words
aessboxword sbox0(.in(ShiftRowOut[31:0]), .out(DataOut[31:0]));
aessboxword sbox1(.in(ShiftRowOut[63:32]), .out(DataOut[63:32]));
endmodule

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///////////////////////////////////////////
// aes64esm.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes64esm instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes64esm(input logic [63:0] rs1,
input logic [63:0] rs2,
output logic [63:0] DataOut);
// Intermediary Signals
logic [127:0] ShiftRowOut;
logic [63:0] SboxOut;
// AES shiftrow unit
aesshiftrow srow(.DataIn({rs2,rs1}), .DataOut(ShiftRowOut));
// Apply substitution box to 2 lower words
aessboxword sbox0(.in(ShiftRowOut[31:0]), .out(SboxOut[31:0]));
aessboxword sbox1(.in(ShiftRowOut[63:32]), .out(SboxOut[63:32]));
// Apply mix columns operations
aesmixcolumns mw0(.in(SboxOut[31:0]), .out(DataOut[31:0]));
aesmixcolumns mw1(.in(SboxOut[63:32]), .out(DataOut[63:32]));
endmodule

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///////////////////////////////////////////
// aes64im.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes64im instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes64im(input logic [63:0] rs1,
output logic [63:0] DataOut);
aesinvmixcolumns inv_mw_0(.in(rs1[31:0]), .out(DataOut[31:0]));
aesinvmixcolumns inv_mw_1(.in(rs1[63:32]), .out(DataOut[63:32]));
endmodule

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///////////////////////////////////////////
// aes64ks1i.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes64ks1i instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes64ks1i(input logic [3:0] roundnum,
input logic [63:0] rs1,
output logic [63:0] rd);
// Instantiate intermediary logic signals
logic [7:0] rconPreShift;
logic [31:0] rcon;
logic lastRoundFlag;
logic [31:0] rs1Rotate;
logic [31:0] tmp2;
logic [31:0] SboxOut;
// Get rcon value from table
rconlut128 rc(.RD(roundnum), .rconOut(rconPreShift));
// Shift RCON value
assign rcon = {24'b0, rconPreShift};
// Flag will be set if roundnum = 0xA = 0b1010
assign lastRoundFlag = roundnum[3] & ~roundnum[2] & roundnum[1] & ~roundnum[0];
// Get rotated value fo ruse in tmp2
assign rs1Rotate = {rs1[39:32], rs1[63:40]};
// Assign tmp2 to a mux based on lastRoundFlag
assign tmp2 = lastRoundFlag ? rs1[63:32] : rs1Rotate;
// Substitute bytes of value obtained for tmp2 using Rijndael sbox
aessboxword sbox(.in(tmp2),.out(SboxOut));
assign rd[31:0] = SboxOut ^ rcon;
assign rd[63:32] = SboxOut ^ rcon;
endmodule

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///////////////////////////////////////////
// aes64ks2.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes64ks2 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module aes64ks2(input logic [63:0] rs2,
input logic [63:0] rs1,
output logic [63:0] rd);
// Instantiate Intermediary logic
logic [31:0] w0;
logic [31:0] w1;
assign w0 = rs1[63:32] ^ rs2[31:0];
assign w1 = rs1[63:32] ^ rs2[31:0] ^ rs2[63:32];
assign rd = {w1, w0};
endmodule

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///////////////////////////////////////////
// rconlut128.sv
//
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: aes64ks1i instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module rconlut128(input logic [3:0] RD,
output logic [7:0] rconOut);
always_comb
begin
case(RD)
4'h0 : rconOut = 8'h01;
4'h1 : rconOut = 8'h02;
4'h2 : rconOut = 8'h04;
4'h3 : rconOut = 8'h08;
4'h4 : rconOut = 8'h10;
4'h5 : rconOut = 8'h20;
4'h6 : rconOut = 8'h40;
4'h7 : rconOut = 8'h80;
4'h8 : rconOut = 8'h1b;
4'h9 : rconOut = 8'h36;
4'hA : rconOut = 8'h00;
default : rconOut = 8'h00;
endcase
end
endmodule

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src/ieu/alu.sv
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@ -33,9 +33,11 @@ module alu import cvw::*; #(parameter cvw_t P) (
input logic W64, // W64-type instruction
input logic SubArith, // Subtraction or arithmetic shift
input logic [2:0] ALUSelect, // ALU mux select signal
input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
input logic [2:0] ZBBSelect, // ZBB mux select signal
input logic [3:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
input logic [3:0] ZBBSelect, // ZBB mux select signal
input logic [2:0] Funct3, // For BMU decoding
input logic [6:0] Funct7, // For ZKNE and ZKND computation
input logic [4:0] Rs2E, // For ZKNE and ZKND computation
input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
input logic BMUActive, // Bit manipulation instruction being executed
input logic [1:0] CZero, // {czero.nez, czero.eqz} instructions active
@ -89,10 +91,10 @@ module alu import cvw::*; #(parameter cvw_t P) (
else assign PreALUResult = FullResult;
// Bit manipulation muxing
if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED) begin : bitmanipalu
if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu
bitmanipalu #(P) balu(
.A, .B, .W64, .BSelect, .ZBBSelect, .BMUActive,
.Funct3, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult,
.Funct3, .Funct7, .Rs2E, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult,
.CondMaskB, .CondShiftA, .ALUResult);
end else begin
assign ALUResult = PreALUResult;

119
src/ieu/bmu/bitmanipalu.sv
View file

@ -1,18 +1,18 @@
///////////////////////////////////////////
// bitmanipalu.sv
//
// Written: Kevin Kim <kekim@hmc.edu>
// Written: Kevin Kim <kekim@hmc.edu>, kelvin.tran@okstate.edu
// Created: 23 March 2023
// Modified: 23 March 2023
// Modified: 9 March 2024
//
// Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension
// Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension and K extension
//
// Documentation: RISC-V System on Chip Design Chapter 15
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
@ -29,29 +29,39 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module bitmanipalu import cvw::*; #(parameter cvw_t P) (
input logic [P.XLEN-1:0] A, B, // Operands
input logic W64, // W64-type instruction
input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
input logic [2:0] ZBBSelect, // ZBB mux select signal
input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform
input logic LT, // less than flag
input logic LTU, // less than unsigned flag
input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
input logic BMUActive, // Bit manipulation instruction being executed
input logic [P.XLEN-1:0] PreALUResult, FullResult,// PreALUResult, FullResult signals
input logic [P.XLEN-1:0] A, B, // Operands
input logic W64, // W64-type instruction
input logic [3:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
input logic [3:0] ZBBSelect, // ZBB mux select signal
input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform
input logic [6:0] Funct7, // Funct7 field for ZKND and ZKNE operations
input logic [4:0] Rs2E, // Register source2 for RNUM of ZKNE/ZKND
input logic LT, // less than flag
input logic LTU, // less than unsigned flag
input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
input logic BMUActive, // Bit manipulation instruction being executed
input logic [P.XLEN-1:0] PreALUResult, // PreALUResult signals
input logic [P.XLEN-1:0] FullResult, // FullResult signals
output logic [P.XLEN-1:0] CondMaskB, // B is conditionally masked for ZBS instructions
output logic [P.XLEN-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions
output logic [P.XLEN-1:0] ALUResult); // Result
logic [P.XLEN-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result
logic [P.XLEN-1:0] MaskB; // BitMask of B
logic [P.XLEN-1:0] RevA; // Bit-reversed A
logic Rotate; // Indicates if it is Rotate instruction
logic Mask; // Indicates if it is ZBS instruction
logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction
logic [1:0] PreShiftAmt; // Amount to Pre-Shift A
logic [P.XLEN-1:0] CondZextA; // A Conditional Extend Intermediary Signal
logic [P.XLEN-1:0] ABMU, BBMU; // Gated data inputs to reduce BMU activity
logic [P.XLEN-1:0] ZBBResult; // ZBB Result
logic [P.XLEN-1:0] ZBCResult; // ZBC Result
logic [P.XLEN-1:0] ZBKBResult; // ZBKB Result
logic [P.XLEN-1:0] ZBKCResult; // ZBKC Result
logic [P.XLEN-1:0] ZBKXResult; // ZBKX Result
logic [P.XLEN-1:0] ZKNDResult; // ZKND Result
logic [P.XLEN-1:0] ZKNEResult; // ZKNE Result
logic [P.XLEN-1:0] ZKNHResult; // ZKNH Result
logic [P.XLEN-1:0] MaskB; // BitMask of B
logic [P.XLEN-1:0] RevA; // Bit-reversed A
logic Rotate; // Indicates if it is Rotate instruction
logic Mask; // Indicates if it is ZBS instruction
logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction
logic [1:0] PreShiftAmt; // Amount to Pre-Shift A
logic [P.XLEN-1:0] CondZextA; // A Conditional Extend Intermediary Signal
logic [P.XLEN-1:0] ABMU, BBMU; // Gated data inputs to reduce BMU activity
// gate data inputs to BMU to only operate when BMU is active
assign ABMU = A & {P.XLEN{BMUActive}};
@ -83,23 +93,70 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
bitreverse #(P.XLEN) brA(.A(ABMU), .RevA);
end
// ZBC Unit
if (P.ZBC_SUPPORTED) begin: zbc
// ZBC and ZBKCUnit
if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED) begin: zbc
zbc #(P.XLEN) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult);
end else assign ZBCResult = 0;
// ZBB Unit
if (P.ZBB_SUPPORTED) begin: zbb
zbb #(P.XLEN) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult);
zbb #(P.XLEN) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect(ZBBSelect[2:0]), .ZBBResult);
end else assign ZBBResult = 0;
// ZBKB Unit
if (P.ZBKB_SUPPORTED) begin: zbkb
zbkb #(P.XLEN) ZBKB(.A(ABMU), .B(BBMU), .RevA, .W64, .Funct3, .ZBKBSelect(ZBBSelect[2:0]), .ZBKBResult);
end else assign ZBKBResult = 0;
// ZBKX Unit
if (P.ZBKX_SUPPORTED) begin: zbkx
zbkx #(P.XLEN) ZBKX(.A(ABMU), .B(BBMU), .ZBKXSelect(ZBBSelect[2:0]), .ZBKXResult);
end else assign ZBKXResult = 0;
// ZKND Unit
if (P.ZKND_SUPPORTED) begin: zknd
if (P.XLEN == 32) begin
zknd32 #(P.XLEN) ZKND32(.A(ABMU), .B(BBMU), .Funct7, .ZKNDSelect(ZBBSelect[2:0]), .ZKNDResult);
end
else begin
zknd64 #(P.XLEN) ZKND64(.A(ABMU), .B(BBMU), .Funct7, .RNUM(Rs2E[3:0]), .ZKNDSelect(ZBBSelect[2:0]), .ZKNDResult);
end
end else assign ZKNDResult = 0;
// ZKNE Unit
if (P.ZKNE_SUPPORTED) begin: zkne
if (P.XLEN == 32) begin
zkne32 #(P.XLEN) ZKNE32(.A(ABMU), .B(BBMU), .Funct7, .ZKNESelect(ZBBSelect[2:0]), .ZKNEResult);
end
else begin
zkne64 #(P.XLEN) ZKNE64(.A(ABMU), .B(BBMU), .Funct7, .RNUM(Rs2E[3:0]), .ZKNESelect(ZBBSelect[2:0]), .ZKNEResult);
end
end else assign ZKNEResult = 0;
// ZKNH Unit
if (P.ZKNH_SUPPORTED) begin: zknh
if (P.XLEN == 32) begin
zknh32 ZKNH32(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult));
end
else begin
zknh64 ZKNH64(.A(ABMU), .B(BBMU), .ZKNHSelect(ZBBSelect), .ZKNHResult(ZKNHResult));
end
end else assign ZKNHResult = 0;
// Result Select Mux
always_comb
case (BSelect)
// 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC
2'b00: ALUResult = PreALUResult;
2'b01: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word.
2'b10: ALUResult = ZBBResult;
2'b11: ALUResult = ZBCResult;
// 0000: ALU, 0001: ZBA/ZBS, 0010: ZBB, 0011: ZBC/ZBKC, 0100: ZBKB, 0110: ZBKX
// 0111: ZKND, 1000: ZKNE, 1001: ZKNH, 1010: ZKSED, 1011: ZKSH...
4'b0000: ALUResult = PreALUResult;
4'b0001: ALUResult = FullResult; // NOTE: don't use ALUResult since ZBA/ZBS doesnt sext the MSB of RH word
4'b0010: ALUResult = ZBBResult;
4'b0011: ALUResult = ZBCResult;
4'b0100: ALUResult = ZBKBResult;
4'b0110: ALUResult = ZBKXResult;
4'b0111: ALUResult = ZKNDResult;
4'b1000: ALUResult = ZKNEResult;
4'b1001: ALUResult = ZKNHResult;
default: ALUResult = PreALUResult;
endcase
endmodule

1
src/ieu/bmu/bitreverse.sv
View file

@ -1,4 +1,3 @@
///////////////////////////////////////////
// bitreverse.sv
//

227
src/ieu/bmu/bmuctrl.sv
View file

@ -1,9 +1,9 @@
///////////////////////////////////////////
// bmuctrl.sv
//
// Written: Kevin Kim <kekim@hmc.edu>
// Written: Kevin Kim <kekim@hmc.edu>, kelvin.tran@okstate.edu
// Created: 16 February 2023
// Modified: 6 March 2023
// Modified: 6 March 2023, 9 March 2024
//
// Purpose: Top level bit manipulation instruction decoder
//
@ -12,7 +12,7 @@
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
@ -34,8 +34,8 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
input logic StallD, FlushD, // Stall, flush Decode stage
input logic [31:0] InstrD, // Instruction in Decode stage
input logic ALUOpD, // Regular ALU Operation
output logic [1:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage
output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode?
output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage
output logic [3:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode?
output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage
output logic BALUSrcBD, // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage
output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage
@ -44,8 +44,8 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
// Execute stage control signals
input logic StallE, FlushE, // Stall, flush Execute stage
output logic [2:0] ALUSelectD, // ALU select
output logic [1:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
output logic [2:0] ZBBSelectE, // ZBB mux select signal
output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
output logic [3:0] ZBBSelectE, // ZBB mux select signal
output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute
output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage
output logic BMUActiveE // Bit manipulation instruction being executed
@ -62,7 +62,7 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
logic [2:0] BALUSelectD; // ALU Mux select signal in Decode Stage for BMU operations
logic BALUOpD; // Indicates if it is an ALU B instruction in Decode Stage
`define BMUCTRLW 17
`define BMUCTRLW 20
logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals
@ -78,92 +78,207 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // default: Illegal bmu instruction;
if (P.ZBA_SUPPORTED) begin
casez({OpD, Funct7D, Funct3D})
17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add
17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add
17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add
17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_0_0_0_1_0; // sh1add
17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_0_0_0_1_0; // sh2add
17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_0_1_0_0_0_1_0; // sh3add
endcase
if (P.XLEN==64)
casez({OpD, Funct7D, Funct3D})
17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw
17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw
17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw
17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw
17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw
17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_1_0; // sh1add.uw
17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_1_0; // sh2add.uw
17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_1_0; // sh3add.uw
17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_0001_0000_1_0_1_1_0_0_0_0_0; // add.uw
17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_0001_0000_1_1_1_1_0_0_0_0_0; // slli.uw
endcase
end
if (P.ZBB_SUPPORTED) begin
casez({OpD, Funct7D, Funct3D})
17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol
17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror
17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010))
BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction
BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_1_0_0_0_0_0; // sign extend instruction
else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction
BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_0_1_0_0_0_0_0; // count instruction
// // coverage off: This case can't occur in RV64
// 17'b0110011_0000100_100: if (P.XLEN == 32)
// BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
// // coverage on
17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn
17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn
17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor
17'b0010011_011010?_101: if ((P.XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000))
BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8
17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111)
BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b
17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_1_0_0_0_0; // max
17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_1_0_0_0_0; // maxu
17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0; // min
17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_1_0_0_0_0; // minu
BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_1_0_0_0_0_0; // orc.b
17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_1_1_0_0_0_0; // max
17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_1_1_0_0_0_0; // maxu
17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0010_0011_1_0_0_1_1_0_0_0_0; // min
17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0010_0011_1_0_0_1_1_0_0_0_0; // minu
endcase
if (P.XLEN==32)
casez({OpD, Funct7D, Funct3D})
17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32)
17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
endcase
else if (P.XLEN==64)
casez({OpD, Funct7D, Funct3D})
17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64)
17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw
17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw
17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64)
17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw
17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0010_0001_1_0_0_1_0_0_0_0_0; // zexth (rv64)
17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction
BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_1_1_0_0_0_0_0; // count word instruction
endcase
end
if (P.ZBC_SUPPORTED)
casez({OpD, Funct7D, Funct3D})
17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction
17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulr
17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // ZBC instruction
endcase
if (P.ZBKC_SUPPORTED | P.ZBC_SUPPORTED) begin // ZBKC
casez({OpD, Funct7D, Funct3D})
17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // clmul
17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulh
endcase
end
if (P.ZBS_SUPPORTED) begin // ZBS
casez({OpD, Funct7D, Funct3D})
17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr
17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext
17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv
17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset
17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_0_0_1_1_0_1_0_0; // bclr
17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_0_0_1_1_0_1_0_0; // bext
17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_0_0_1_0_0_1_0_0; // binv
17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_0_0_1_0_0_1_0_0; // bset
endcase
if (P.XLEN==32) // ZBS 64-bit
casez({OpD, Funct7D, Funct3D})
17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri
17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti
17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi
17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti
17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_1_1_0_1_0_0; // bclri
17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_1_0_1_0_0; // bexti
17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_1_0_0_1_0_0; // binvi
17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_1_0_0_1_0_0; // bseti
endcase
else if (P.XLEN==64) // ZBS 64-bit
casez({OpD, Funct7D, Funct3D})
17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64)
17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64)
17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64)
17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64)
17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001_0000_1_1_0_1_1_0_1_0_0; // bclri (rv64)
17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001_0000_1_1_0_1_1_0_1_0_0; // bexti (rv64)
17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001_0000_1_1_0_1_0_0_1_0_0; // binvi (rv64)
17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001_0000_1_1_0_1_0_0_1_0_0; // bseti (rv64)
endcase
end
if (P.ZBB_SUPPORTED | P.ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used
casez({OpD, Funct7D, Funct3D})
17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll
17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli
17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw
17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw
17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_0_1_0_0_0_0_0; // sra, srl, sll
17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_0_1_0_0_0_0_0; // srai, srli, slli
17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw
17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_0000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw
endcase
if (P.ZBKB_SUPPORTED) begin // ZBKB Bitmanip
casez({OpD,Funct7D, Funct3D})
17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_1_0_0_0_0_0; // pack
17'b0110011_0000100_111: BMUControlsD = `BMUCTRLW'b000_0100_0001_1_0_0_1_0_0_0_0_0; //packh
17'b0010011_0110100_101: if (Rs2D == 5'b00111)
BMUControlsD = `BMUCTRLW'b000_0100_0000_1_1_0_1_0_0_0_0_0; //brev8
endcase
if (P.XLEN==32)
casez({OpD, Funct7D, Funct3D})
17'b0010011_0000100_001: if (Rs2D == 5'b01111)
BMUControlsD = `BMUCTRLW'b000_0100_0011_1_1_0_1_0_0_0_0_0; //zip
17'b0010011_0000100_101: if (Rs2D == 5'b01111)
BMUControlsD = `BMUCTRLW'b000_0100_0011_1_1_0_1_0_0_0_0_0; //unzip
endcase
else if (P.XLEN==64)
casez({OpD,Funct7D, Funct3D})
17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_0100_0101_1_0_1_1_0_0_0_0_0; //packw
endcase
end
if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin // ZBB and ZBKB shared instructions
casez({OpD, Funct7D, Funct3D})
17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_1_0_1_0_0_0; // rol
17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0001_0111_1_0_0_1_0_1_0_0_0; // ror
17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0001_0111_1_0_0_1_1_0_0_0_0; // andn
17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0001_0111_1_0_0_1_1_0_0_0_0; // orn
17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0001_0111_1_0_0_1_1_0_0_0_0; // xnor
17'b0010011_011010?_101: if ((P.XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000))
BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_1_0_0_0_0_0; // rev8
endcase
if (P.XLEN==32)
casez({OpD, Funct7D, Funct3D})
17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_0_1_0_1_0_0_0; // rori (rv32)
endcase
else if (P.XLEN==64)
casez({OpD, Funct7D, Funct3D})
17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_0_1_1_0_1_0_0_0; // rolw
17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_0_1_1_0_1_0_0_0; // rorw
17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_0_1_0_1_0_0_0; // rori (rv64)
17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0000_0111_1_1_1_1_0_1_0_0_0; // roriw
endcase
end
if (P.ZBKX_SUPPORTED) begin //ZBKX
casez({OpD, Funct7D, Funct3D})
17'b0110011_0010100_100: BMUControlsD = `BMUCTRLW'b000_0110_0000_1_0_0_1_0_0_0_0_0; // xperm8
17'b0110011_0010100_010: BMUControlsD = `BMUCTRLW'b000_0110_0001_1_0_0_1_0_0_0_0_0; // xperm4
endcase
end
if (P.ZKND_SUPPORTED) begin //ZKND
if (P.XLEN==32)
casez({OpD, Funct7D, Funct3D})
17'b0110011_??10101_000: BMUControlsD = `BMUCTRLW'b000_0111_0000_1_0_0_1_0_0_0_0_0; // aes32dsi - final round decrypt
17'b0110011_??10111_000: BMUControlsD = `BMUCTRLW'b000_0111_0001_1_0_0_1_0_0_0_0_0; // aes32dsmi - mid round decrypt
endcase
else if (P.XLEN==64)
casez({OpD, Funct7D, Funct3D})
17'b0110011_0011101_000: BMUControlsD = `BMUCTRLW'b000_0111_0000_1_0_0_1_0_0_0_0_0; // aes64ds - decrypt final round
17'b0110011_0011111_000: BMUControlsD = `BMUCTRLW'b000_0111_0001_1_0_0_1_0_0_0_0_0; // aes64dsm - decrypt mid round
17'b0010011_0011000_001: if (Rs2D == 5'b00000)
BMUControlsD = `BMUCTRLW'b000_0111_0010_1_1_0_1_0_0_0_0_0; // aes64im - decrypt keyschdule mixcolumns
endcase
end
if (P.ZKNE_SUPPORTED) begin //ZKNE
if (P.XLEN==32)
casez({OpD, Funct7D, Funct3D})
17'b0110011_??10001_000: BMUControlsD = `BMUCTRLW'b000_1000_0000_1_0_0_1_0_0_0_0_0; // aes32esi - final round encrypt
17'b0110011_??10011_000: BMUControlsD = `BMUCTRLW'b000_1000_0001_1_0_0_1_0_0_0_0_0; // aes32esmi - mid round encrypt
endcase
else if (P.XLEN==64)
casez({OpD, Funct7D, Funct3D})
17'b0110011_0011001_000: BMUControlsD = `BMUCTRLW'b000_1000_0000_1_0_0_1_0_0_0_0_0; // aes64es - encrypt final round
17'b0110011_0011011_000: BMUControlsD = `BMUCTRLW'b000_1000_0001_1_0_0_1_0_0_0_0_0; // aes64esm - encrypt mid round
endcase
end
if (P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED) begin // ZKND and ZKNE shared instructions
casez({OpD, Funct7D, Funct3D})
17'b0010011_0011000_001: if (Rs2D[4] == 1'b1)
BMUControlsD = `BMUCTRLW'b000_0111_0011_1_0_0_1_0_0_0_0_0; // aes64ks1i - key schedule istr1 ... Don't know why this works here only ... P.XLEN is not 64 bits?
endcase
if (P.XLEN==64)
casez({OpD, Funct7D, Funct3D})
17'b0110011_0111111_000: BMUControlsD = `BMUCTRLW'b000_0111_0100_1_0_0_1_0_0_0_0_0; // aes64ks2 - key schedule istr2
endcase
end
if (P.ZKNH_SUPPORTED) begin // ZKNH
casez({OpD, Funct7D, Funct3D})
17'b0010011_0001000_001:
if (Rs2D == 5'b00010) BMUControlsD = `BMUCTRLW'b000_1001_0000_1_0_0_1_0_0_0_0_0; // sha256sig0
else if (Rs2D == 5'b00011) BMUControlsD = `BMUCTRLW'b000_1001_0001_1_0_0_1_0_0_0_0_0; // sha256sig1
else if (Rs2D == 5'b00000) BMUControlsD = `BMUCTRLW'b000_1001_0010_1_0_0_1_0_0_0_0_0; // sha256sum0
else if (Rs2D == 5'b00001) BMUControlsD = `BMUCTRLW'b000_1001_0011_1_0_0_1_0_0_0_0_0; // sha256sum1
endcase
if (P.XLEN==32)
casez({OpD, Funct7D, Funct3D})
17'b0110011_0101110_000: BMUControlsD = `BMUCTRLW'b000_1001_0100_1_0_0_1_0_0_0_0_0; // sha512sig0h
17'b0110011_0101010_000: BMUControlsD = `BMUCTRLW'b000_1001_0101_1_0_0_1_0_0_0_0_0; // sha512sig0l
17'b0110011_0101111_000: BMUControlsD = `BMUCTRLW'b000_1001_0110_1_0_0_1_0_0_0_0_0; // sha512sig1h
17'b0110011_0101011_000: BMUControlsD = `BMUCTRLW'b000_1001_0111_1_0_0_1_0_0_0_0_0; // sha512sig1l
17'b0110011_0101000_000: BMUControlsD = `BMUCTRLW'b000_1001_1000_1_0_0_1_0_0_0_0_0; // sha512sum0r
17'b0110011_0101001_000: BMUControlsD = `BMUCTRLW'b000_1001_1001_1_0_0_1_0_0_0_0_0; // sha512sum1r
endcase
else if (P.XLEN==64)
casez({OpD, Funct7D, Funct3D})
17'b0010011_0001000_001:
if (Rs2D == 5'b00110) BMUControlsD = `BMUCTRLW'b000_1001_1010_1_0_0_1_0_0_0_0_0; // sha512sig0
else if (Rs2D == 5'b00111) BMUControlsD = `BMUCTRLW'b000_1001_1011_1_0_0_1_0_0_0_0_0; // sha512sig1
else if (Rs2D == 5'b00100) BMUControlsD = `BMUCTRLW'b000_1001_1100_1_0_0_1_0_0_0_0_0; // sha512sum0
else if (Rs2D == 5'b00101) BMUControlsD = `BMUCTRLW'b000_1001_1101_1_0_0_1_0_0_0_0_0; // sha512sum1
endcase
end
end
// Unpack Control Signals
@ -176,5 +291,5 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000);
// BMU Execute stage pipieline control register
flopenrc #(10) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE, BMUActiveE});
flopenrc #(13) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BALUControlD, ~IllegalBitmanipInstrD}, {BSelectE, ZBBSelectE, BRegWriteE, BALUControlE, BMUActiveE});
endmodule

20
src/ieu/bmu/byteop.sv
View file

@ -1,9 +1,9 @@
///////////////////////////////////////////
// byteop.sv
//
// Written: Kevin Kim <kekim@hmc.edu>
// Written: Kevin Kim <kekim@hmc.edu>, kelvin.tran@okstate.edu
// Created: 1 February 2023
// Modified: 6 March 2023
// Modified: 29 February 2024
//
// Purpose: RISCV bitmanip byte-wise operation unit
//
@ -12,7 +12,7 @@
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
@ -30,16 +30,24 @@
module byteop #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, // Operands
input logic ByteSelect, // LSB of Immediate
input logic [WIDTH-1:0] RevA, // Reversed A
input logic [1:0] ByteSelect, // LSB of Immediate
output logic [WIDTH-1:0] ByteResult); // rev8, orcb result
logic [WIDTH-1:0] OrcBResult, Rev8Result;
logic [WIDTH-1:0] OrcBResult, Rev8Result, Brev8Result;
genvar i;
for (i=0;i<WIDTH;i+=8) begin:loop
assign OrcBResult[i+7:i] = {8{|A[i+7:i]}};
assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i];
assign Brev8Result[i+7:i] = RevA[WIDTH-1-i:WIDTH-i-8];
end
mux2 #(WIDTH) bytemux(Rev8Result, OrcBResult, ByteSelect, ByteResult);
// ByteOp Result Mux
always_comb begin
if (ByteSelect[0] == 1'b0) ByteResult = Rev8Result;
else if (ByteSelect[1] == 1'b0) ByteResult = OrcBResult;
else ByteResult = Brev8Result;
end
endmodule

1
src/ieu/bmu/cnt.sv
View file

@ -1,4 +1,3 @@
///////////////////////////////////////////
// cnt.sv
//

1
src/ieu/bmu/ext.sv
View file

@ -1,4 +1,3 @@
///////////////////////////////////////////
// ext.sv
//

1
src/ieu/bmu/popcnt.sv
View file

@ -1,4 +1,3 @@
///////////////////////////////////////////
// popccnt.sv
// Written: Kevin Kim <kekim@hmc.edu>

3
src/ieu/bmu/zbb.sv
View file

@ -1,4 +1,3 @@
///////////////////////////////////////////
// zbb.sv
//
@ -46,7 +45,7 @@ module zbb #(parameter WIDTH=32) (
mux2 #(1) ltmux(LT, LTU, BUnsigned , lt);
cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult);
byteop #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult);
byteop #(WIDTH) bu(.A, .RevA, .ByteSelect({B[10], B[0]}), .ByteResult);
ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult);
// ZBBSelect[2] differentiates between min(u) vs max(u) instruction

25
src/ieu/controller.sv
View file

@ -43,7 +43,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
output logic StructuralStallD, // Structural stalls detected by controller
output logic LoadStallD, // Structural stalls for load, sent to performance counters
output logic StoreStallD, // load after store hazard
output logic [4:0] Rs1D, Rs2D, // Register sources to read in Decode or Execute stage
output logic [4:0] Rs1D, Rs2D, Rs2E, // Register sources to read in Decode or Execute stage
// Execute stage control signals
input logic StallE, FlushE, // Stall, flush Execute stage
input logic [1:0] FlagsE, // Comparison flags ({eq, lt})
@ -55,6 +55,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
output logic [2:0] ALUSelectE, // ALU mux select signal
output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit)
output logic [2:0] Funct3E, // Instruction's funct3 field
output logic [6:0] Funct7E, // Instruction's funct7 field
output logic IntDivE, // Integer divide
output logic MDUE, // MDU (multiply/divide) operatio
output logic W64E, // RV64 W-type operation
@ -63,8 +64,8 @@ module controller import cvw::*; #(parameter cvw_t P) (
output logic BranchE, // Branch instruction
output logic SCE, // Store Conditional instruction
output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch)
output logic [1:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction
output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage
output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction
output logic [3:0] ZBBSelectE, // ZBB mux select signal in Execute stage
output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage
output logic BMUActiveE, // Bit manipulation instruction being executed
output logic [1:0] CZeroE, // {czero.nez, czero.eqz} instructions active
@ -95,7 +96,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
output logic [4:0] RdW // Register destinations in Execute, Memory, or Writeback stage
);
logic [4:0] Rs1E, Rs2E; // pipelined register sources
logic [4:0] Rs1E; // pipelined register sources
logic [6:0] OpD; // Opcode in Decode stage
logic [2:0] Funct3D; // Funct3 field in Decode stage
logic [6:0] Funct7D; // Funct7 field in Decode stage
@ -138,8 +139,8 @@ module controller import cvw::*; #(parameter cvw_t P) (
logic FenceD, FenceE; // Fence instruction
logic SFenceVmaD; // sfence.vma instruction
logic IntDivM; // Integer divide instruction
logic [1:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage
logic [2:0] ZBBSelectD; // ZBB Mux Select Signal
logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage
logic [3:0] ZBBSelectD; // ZBB Mux Select Signal
logic [1:0] CZeroD;
logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions
logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions
@ -351,9 +352,9 @@ module controller import cvw::*; #(parameter cvw_t P) (
assign SubArithD = BaseSubArithD; // TRUE If B-type or R-type instruction involves inverted operand
// tie off unused bit manipulation signals
assign BSelectE = 2'b00;
assign BSelectD = 2'b00;
assign ZBBSelectE = 3'b000;
assign BSelectE = 4'b0000;
assign BSelectD = 4'b0000;
assign ZBBSelectE = 4'b0000;
assign BALUControlE = 3'b0;
assign BMUActiveE = 1'b0;
end
@ -417,9 +418,9 @@ module controller import cvw::*; #(parameter cvw_t P) (
flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
// Execute stage pipeline control register and logic
flopenrc #(37) controlregE(clk, reset, FlushE, ~StallE,
{ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, CZeroD, InstrValidD},
{ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, CZeroE, InstrValidE});
flopenrc #(44) controlregE(clk, reset, FlushE, ~StallE,
{ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, CZeroD, InstrValidD},
{ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, CZeroE, InstrValidE});
flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);

9
src/ieu/datapath.sv
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@ -33,11 +33,12 @@ module datapath import cvw::*; #(parameter cvw_t P) (
// Decode stage signals
input logic [2:0] ImmSrcD, // Selects type of immediate extension
input logic [31:0] InstrD, // Instruction in Decode stage
input logic [4:0] Rs1D, Rs2D, // Source registers
input logic [4:0] Rs1D, Rs2D, Rs2E, // Source registers
// Execute stage signals
input logic [P.XLEN-1:0] PCE, // PC in Execute stage
input logic [P.XLEN-1:0] PCLinkE, // PC + 4 (of instruction in Execute stage)
input logic [2:0] Funct3E, // Funct3 field of instruction in Execute stage
input logic [6:0] Funct7E, // Funct7 field of instruction in Execute stage
input logic StallE, FlushE, // Stall, flush Execute stage
input logic [1:0] ForwardAE, ForwardBE, // Forward ALU operands from later stages
input logic W64E, // W64-type instruction
@ -47,8 +48,8 @@ module datapath import cvw::*; #(parameter cvw_t P) (
input logic [2:0] ALUSelectE, // ALU mux select signal
input logic JumpE, // Is a jump (j) instruction
input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch)
input logic [1:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction
input logic [2:0] ZBBSelectE, // ZBB mux select signal
input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction
input logic [3:0] ZBBSelectE, // ZBB mux select signal
input logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage
input logic BMUActiveE, // Bit manipulation instruction being executed
input logic [1:0] CZeroE, // {czero.nez, czero.eqz} instructions active
@ -109,7 +110,7 @@ module datapath import cvw::*; #(parameter cvw_t P) (
comparator #(P.XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
mux2 #(P.XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
mux2 #(P.XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
alu #(P) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, BMUActiveE, CZeroE, ALUResultE, IEUAdrE);
alu #(P) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, Funct7E, Rs2E, BALUControlE, BMUActiveE, CZeroE, ALUResultE, IEUAdrE);
mux2 #(P.XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
mux2 #(P.XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);

17
src/ieu/ieu.sv
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@ -90,13 +90,16 @@ module ieu import cvw::*; #(parameter cvw_t P) (
logic SCE; // Store Conditional instruction
logic FWriteIntM; // FPU writing to integer register file
logic IntDivW; // Integer divide instruction
logic [1:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
logic [2:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage
logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding
logic [3:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage
logic [2:0] BALUControlE; // ALU Control signals for B instructions in Execute Stage
logic SubArithE; // Subtraction or arithmetic shift
logic [6:0] Funct7E;
// Forwarding signals
logic [4:0] Rs1D, Rs2D; // Source registers
logic [4:0] Rs1D, Rs2D;
logic [4:0] Rs2E; // Source registers
logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers
logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages
logic MemReadE, CSRReadE; // Load, CSRRead instruction
@ -108,10 +111,10 @@ module ieu import cvw::*; #(parameter cvw_t P) (
controller #(P) c(
.clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,
.IllegalIEUFPUInstrD, .IllegalBaseInstrD,
.StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D,
.StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D, .Rs2E,
.StallE, .FlushE, .FlagsE, .FWriteIntE,
.PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE,
.Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE,
.Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE,
.BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE, .MDUActiveE,
.FCvtIntE, .ForwardAE, .ForwardBE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
.StallM, .FlushM, .MemRWE, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
@ -120,8 +123,8 @@ module ieu import cvw::*; #(parameter cvw_t P) (
.RdW, .RdE, .RdM);
datapath #(P) dp(
.clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE,
.Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE,
.clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .Rs2E, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE,
.Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE,
.PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .CZeroE,
.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
.StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,

58
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@ -0,0 +1,58 @@
///////////////////////////////////////////
// packer.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 5 October 2023
//
// Purpose: RISCV kbitmanip pack operation unit
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module packer #(parameter WIDTH=32) (
input logic [WIDTH-1:0] A, B,
input logic [2:0] PackSelect,
output logic [WIDTH-1:0] PackResult);
logic [WIDTH/2-1:0] lowhalf, highhalf;
logic [7:0] lowhalfh, highhalfh;
logic [15:0] lowhalfw, highhalfw;
logic [WIDTH-1:0] Pack;
logic [WIDTH-1:0] PackH;
logic [WIDTH-1:0] PackW;
assign lowhalf = A[WIDTH/2-1:0];
assign highhalf = B[WIDTH/2-1:0];
assign lowhalfh = A[7:0];
assign highhalfh = B[7:0];
assign lowhalfw = A[15:0];
assign highhalfw = B[15:0];
assign Pack = {highhalf, lowhalf};
assign PackH = {{(WIDTH-16){1'b0}}, highhalfh, lowhalfh};
assign PackW = {{(WIDTH-32){highhalfw[15]}}, highhalfw, lowhalfw};
always_comb
begin
if (PackSelect[1:0] == 2'b11) PackResult = PackH;
else if (PackSelect[2] == 1'b0) PackResult = Pack;
else PackResult = PackW;
end
endmodule

45
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@ -0,0 +1,45 @@
///////////////////////////////////////////
// zbkb.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 4 October 2023
//
// Purpose: RISC-V ZBKB top level unit
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module zbkb #(parameter WIDTH=32)
(input logic [WIDTH-1:0] A, B, RevA,
input logic W64,
input logic [2:0] Funct3,
input logic [2:0] ZBKBSelect,
output logic [WIDTH-1:0] ZBKBResult);
logic [WIDTH-1:0] ByteResult; // rev8, brev8
logic [WIDTH-1:0] PackResult; // pack, packh, packw (RB64 only)
logic [WIDTH-1:0] ZipResult; // zip, unzip
byteop #(WIDTH) rev(.A, .RevA, .ByteSelect({B[10], B[0]}), .ByteResult);
packer #(WIDTH) pack(.A, .B, .PackSelect({ZBKBSelect[2], Funct3[1:0]}), .PackResult);
zipper #(WIDTH) zip(.A, .ZipSelect(Funct3[2]), .ZipResult);
// ZBKB Result Select Mux
mux3 #(WIDTH) zbkbresultmux(ByteResult, PackResult, ZipResult, ZBKBSelect[1:0], ZBKBResult);
endmodule

50
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@ -0,0 +1,50 @@
///////////////////////////////////////////
// zbkx.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 1 February 2024
//
// Purpose: RISC-V ZBKX top level unit
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module zbkx #(parameter WIDTH=32)
(input logic [WIDTH-1:0] A, B,
input logic [2:0] ZBKXSelect,
output logic [WIDTH-1:0] ZBKXResult);
logic [WIDTH-1:0] xpermlookup;
integer i;
always_comb begin
if (ZBKXSelect[0] == 1'b0) begin
for(i=0; i<WIDTH; i=i+8) begin: xperm8
xpermlookup = A >> {B[i+:8], 3'b0};
ZBKXResult[i+:8] = xpermlookup[7:0];
end
end
else begin
for(i=0; i<WIDTH; i=i+4) begin: xperm4
xpermlookup = A >> {B[i+:4], 2'b0};
ZBKXResult[i+:4] = xpermlookup[3:0];
end
end
end
endmodule

45
src/ieu/kmu/zipper.sv Normal file
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@ -0,0 +1,45 @@
///////////////////////////////////////////
// zipper.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 9 October 2023
//
// Purpose: RISCV kbitmanip zip operation unit
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module zipper #(parameter WIDTH=64)
(input logic [WIDTH-1:0] A,
input logic ZipSelect,
output logic [WIDTH-1:0] ZipResult);
logic [WIDTH-1:0] zip;
logic [WIDTH-1:0] unzip;
genvar i;
for (i=0; i<WIDTH/2; i+=1) begin: loop
assign zip[2*i] = A[i];
assign zip [2*i+1] = A[i + WIDTH/2];
assign unzip[i] = A[2*i];
assign unzip[i+WIDTH/2] = A[2*i+1];
end
mux2 #(WIDTH) ZipMux(zip, unzip, ZipSelect, ZipResult);
endmodule

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@ -0,0 +1,43 @@
///////////////////////////////////////////
// zknd32.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 27 November 2023
// Modified: 31 January 2024
//
// Purpose: RISC-V ZKND top level unit for 32-bit instructions
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module zknd32 #(parameter WIDTH=32)
(input logic [WIDTH-1:0] A, B,
input logic [6:0] Funct7,
input logic [2:0] ZKNDSelect,
output logic [WIDTH-1:0] ZKNDResult);
logic [31:0] aes32dsiRes;
logic [31:0] aes32dsmiRes;
// RV32
aes32dsi aes32dsi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32dsiRes));
aes32dsmi aes32dsmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32dsmiRes));
mux2 #(WIDTH) zkndmux (aes32dsiRes, aes32dsmiRes, ZKNDSelect[0], ZKNDResult);
endmodule

50
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@ -0,0 +1,50 @@
///////////////////////////////////////////
// zknd64.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 27 November 2023
// Modified: 31 January 2024
//
// Purpose: RISC-V ZKND top level unit for 64-bit instructions
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module zknd64 #(parameter WIDTH=32)
(input logic [WIDTH-1:0] A, B,
input logic [6:0] Funct7,
input logic [3:0] RNUM,
input logic [2:0] ZKNDSelect,
output logic [WIDTH-1:0] ZKNDResult);
logic [63:0] aes64dsRes;
logic [63:0] aes64dsmRes;
logic [63:0] aes64imRes;
logic [63:0] aes64ks1iRes;
logic [63:0] aes64ks2Res;
// RV64
aes64ds aes64ds (.rs1(A), .rs2(B), .DataOut(aes64dsRes));
aes64dsm aes64dsm (.rs1(A), .rs2(B), .DataOut(aes64dsmRes));
aes64im aes64im (.rs1(A), .DataOut(aes64imRes));
aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res));
mux5 #(WIDTH) zkndmux (aes64dsRes, aes64dsmRes, aes64imRes, aes64ks1iRes, aes64ks2Res, ZKNDSelect, ZKNDResult);
endmodule

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@ -0,0 +1,43 @@
///////////////////////////////////////////
// zkne32.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 21 November 2023
// Modified: 31 January 2024
//
// Purpose: RISC-V ZKNE top level unit for 32-bit instructions
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module zkne32 #(parameter WIDTH=32)
(input logic [WIDTH-1:0] A, B,
input logic [6:0] Funct7,
input logic [2:0] ZKNESelect,
output logic [WIDTH-1:0] ZKNEResult);
logic [31:0] aes32esiRes;
logic [31:0] aes32esmiRes;
// RV32
aes32esi aes32esi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32esiRes));
aes32esmi aes32esmi (.bs(Funct7[6:5]), .rs1(A), .rs2(B), .DataOut(aes32esmiRes));
mux2 #(WIDTH) zknemux (aes32esiRes, aes32esmiRes, ZKNESelect[0], ZKNEResult);
endmodule

49
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@ -0,0 +1,49 @@
///////////////////////////////////////////
// zkne64.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 21 November 2023
// Modified: 31 January 2024
//
// Purpose: RISC-V ZKNE top level unit for 64-bit instructions
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module zkne64 #(parameter WIDTH=32)
(input logic [WIDTH-1:0] A, B,
input logic [6:0] Funct7,
input logic [3:0] RNUM,
input logic [2:0] ZKNESelect,
output logic [WIDTH-1:0] ZKNEResult);
logic [63:0] aes64esRes;
logic [63:0] aes64esmRes;
logic [63:0] aes64ks1iRes;
logic [63:0] aes64ks2Res;
// RV64
aes64es aes64es (.rs1(A), .rs2(B), .DataOut(aes64esRes));
aes64esm aes64esm (.rs1(A), .rs2(B), .DataOut(aes64esmRes));
aes64ks1i aes64ks1i (.roundnum(RNUM), .rs1(A), .rd(aes64ks1iRes));
aes64ks2 aes64ks2 (.rs2(B), .rs1(A), .rd(aes64ks2Res));
// 010 is a placeholder to match the select of ZKND's AES64KS1I since they share some instruction
mux5 #(WIDTH) zknemux (aes64esRes, aes64esmRes, 64'b0, aes64ks1iRes, aes64ks2Res, ZKNESelect, ZKNEResult);
endmodule

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///////////////////////////////////////////
// zknh32.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 13 February 2024
//
// Purpose: RISC-V ZKNH 32-Bit top level unit
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module zknh32 (input logic [31:0] A, B,
input logic [3:0] ZKNHSelect,
output logic [31:0] ZKNHResult);
logic [31:0] sha256sig0res;
logic [31:0] sha256sig1res;
logic [31:0] sha256sum0res;
logic [31:0] sha256sum1res;
logic [31:0] sha512sig0hres;
logic [31:0] sha512sig0lres;
logic [31:0] sha512sig1hres;
logic [31:0] sha512sig1lres;
logic [31:0] sha512sum0rres;
logic [31:0] sha512sum1rres;
sha256sig0 #(32) sha256sig0(A, sha256sig0res);
sha256sig1 #(32) sha256sig1(A, sha256sig1res);
sha256sum0 #(32) sha256sum0(A, sha256sum0res);
sha256sum1 #(32) sha256sum1(A, sha256sum1res);
sha512sig0h sha512sig0h(A, B, sha512sig0hres);
sha512sig0l sha512sig0l(A, B, sha512sig0lres);
sha512sig1h sha512sig1h(A, B, sha512sig1hres);
sha512sig1l sha512sig1l(A, B, sha512sig1lres);
sha512sum0r sha512sum0r(A, B, sha512sum0rres);
sha512sum1r sha512sum1r(A, B, sha512sum1rres);
// Result Select Mux
always_comb begin
casez(ZKNHSelect)
4'b0000: ZKNHResult = sha256sig0res;
4'b0001: ZKNHResult = sha256sig1res;
4'b0010: ZKNHResult = sha256sum0res;
4'b0011: ZKNHResult = sha256sum1res;
4'b0100: ZKNHResult = sha512sig0hres;
4'b0101: ZKNHResult = sha512sig0lres;
4'b0110: ZKNHResult = sha512sig1hres;
4'b0111: ZKNHResult = sha512sig1lres;
4'b1000: ZKNHResult = sha512sum0rres;
4'b1001: ZKNHResult = sha512sum1rres;
default ZKNHResult = 0;
endcase
end
endmodule

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///////////////////////////////////////////
// zknh64.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 13 February 2024
//
// Purpose: RISC-V ZKNH 64-Bit top level unit
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module zknh64 (input logic [63:0] A, B, input logic [3:0] ZKNHSelect,
output logic [63:0] ZKNHResult);
logic [63:0] sha256sig0res;
logic [63:0] sha256sig1res;
logic [63:0] sha256sum0res;
logic [63:0] sha256sum1res;
logic [63:0] sha512sig0res;
logic [63:0] sha512sig1res;
logic [63:0] sha512sum0res;
logic [63:0] sha512sum1res;
sha256sig0 #(64) sha256sig0(A, sha256sig0res);
sha256sig1 #(64) sha256sig1(A, sha256sig1res);
sha256sum0 #(64) sha256sum0(A, sha256sum0res);
sha256sum1 #(64) sha256sum1(A, sha256sum1res);
sha512sig0 sha512sig0(A, sha512sig0res);
sha512sig1 sha512sig1(A, sha512sig1res);
sha512sum0 sha512sum0(A, sha512sum0res);
sha512sum1 sha512sum1(A, sha512sum1res);
// Result Select Mux
always_comb begin
casez(ZKNHSelect)
4'b0000: ZKNHResult = sha256sig0res;
4'b0001: ZKNHResult = sha256sig1res;
4'b0010: ZKNHResult = sha256sum0res;
4'b0011: ZKNHResult = sha256sum1res;
4'b1010: ZKNHResult = sha512sig0res;
4'b1011: ZKNHResult = sha512sig1res;
4'b1100: ZKNHResult = sha512sum0res;
4'b1101: ZKNHResult = sha512sum1res;
default ZKNHResult = 0;
endcase
end
endmodule

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///////////////////////////////////////////
// sha256sig0.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha256sig0 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256sig0 #(parameter WIDTH=32)
(input logic [WIDTH-1:0] rs1,
output logic [WIDTH-1:0] result);
logic [31:0] ror7;
logic [31:0] ror18;
logic [31:0] sh3;
logic [31:0] exts;
assign ror7 = {rs1[6:0], rs1[31:7]};
assign ror18 = {rs1[17:0], rs1[31:18]};
assign sh3 = {3'b0, rs1[31:3]};
// Assign output to xor of 3 rotates
assign exts = ror7 ^ ror18 ^ sh3;
if (WIDTH==32)
assign result = exts;
else
assign result = {{32{exts[31]}}, exts};
endmodule

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///////////////////////////////////////////
// sha256sig1.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha256sig1 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256sig1 #(parameter WIDTH=32)
(input logic [WIDTH-1:0] rs1,
output logic [WIDTH-1:0] result);
logic [31:0] ror17;
logic [31:0] ror19;
logic [31:0] sh10;
logic [31:0] exts;
assign ror17 = {rs1[16:0], rs1[31:17]};
assign ror19 = {rs1[18:0], rs1[31:19]};
assign sh10 = {10'b0, rs1[31:10]};
// Assign output to xor of 3 rotates
assign exts = ror17 ^ ror19 ^ sh10;
if (WIDTH==32)
assign result = exts;
else
assign result = {{32{exts[31]}}, exts};
endmodule

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///////////////////////////////////////////
// sha256sum0.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha256sum0 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256sum0 #(parameter WIDTH=32)
(input logic [WIDTH-1:0] rs1,
output logic [WIDTH-1:0] result);
logic [31:0] ror2;
logic [31:0] ror13;
logic [31:0] ror22;
logic [31:0] exts;
assign ror2 = {rs1[1:0], rs1[31:2]};
assign ror13 = {rs1[12:0], rs1[31:13]};
assign ror22 = {rs1[21:0], rs1[31:22]};
// Assign output to xor of 3 rotates
assign exts = ror2 ^ ror13 ^ ror22;
if (WIDTH==32)
assign result = exts;
else
assign result = {{32{exts[31]}}, exts};
endmodule

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///////////////////////////////////////////
// sha256sum1.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha256sum1 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha256sum1 #(parameter WIDTH=32)
(input logic [WIDTH-1:0] rs1,
output logic [WIDTH-1:0] result);
logic [31:0] ror6;
logic [31:0] ror11;
logic [31:0] ror25;
logic [31:0] exts;
assign ror6 = {rs1[5:0], rs1[31:6]};
assign ror11 = {rs1[10:0], rs1[31:11]};
assign ror25 = {rs1[24:0], rs1[31:25]};
// Assign output to xor of 3 rotates
assign exts = ror6 ^ ror11 ^ ror25;
if (WIDTH==32)
assign result = exts;
else
assign result = {{32{exts[31]}}, exts};
endmodule

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///////////////////////////////////////////
// sha512sig0.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig0 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig0(input logic [63:0] rs1, output logic [63:0] result);
logic [63:0] ror1;
logic [63:0] ror8;
logic [63:0] sh7;
assign ror1 = {rs1[0], rs1[63:1]};
assign ror8 = {rs1[7:0], rs1[63:8]};
assign sh7 = rs1 >> 7;
// Assign output to xor of 3 rotates
assign result = ror1 ^ ror8 ^ sh7;
endmodule

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///////////////////////////////////////////
// sha512sig0h.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig0h instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig0h(input logic [31:0] rs1, input logic [31:0] rs2,
output logic [31:0] DataOut);
// RS1 Shifts
logic [31:0] shift1;
logic [31:0] shift7;
logic [31:0] shift8;
// RS2 Shifts
logic [31:0] shift31;
logic [31:0] shift24;
// Shift rs1
assign shift1 = rs1 >> 1;
assign shift7 = rs1 >> 7;
assign shift8 = rs1 >> 8;
// Shift rs2
assign shift31 = rs2 << 31;
assign shift24 = rs2 << 24;
// XOR to get result
assign DataOut = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift24;
endmodule

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///////////////////////////////////////////
// sha512sig0l.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig0l instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig0l(input logic [31:0] rs1, input logic [31:0] rs2,
output logic [31:0] DataOut);
// rs1 operations
logic [31:0] shift1;
logic [31:0] shift7;
logic [31:0] shift8;
// rs2 operations
logic [31:0] shift31;
logic [31:0] shift25;
logic [31:0] shift24;
// rs1 shifts
assign shift1 = rs1 >> 1;
assign shift7 = rs1 >> 7;
assign shift8 = rs1 >> 8;
// rs2 shifts
assign shift31 = rs2 << 31;
assign shift25 = rs2 << 25;
assign shift24 = rs2 << 24;
assign DataOut = shift1 ^ shift7 ^ shift8 ^ shift31 ^ shift25 ^ shift24;
endmodule

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///////////////////////////////////////////
// sha512sig1.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sig1 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig1(input logic [63:0] rs1, output logic [63:0] result);
logic [63:0] ror19;
logic [63:0] ror61;
logic [63:0] sh6;
assign ror19 = {rs1[18:0], rs1[63:19]};
assign ror61 = {rs1[60:0], rs1[63:61]};
assign sh6 = rs1 >> 6;
// Assign output to xor of 3 rotates
assign result = ror19 ^ ror61 ^ sh6;
endmodule

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///////////////////////////////////////////
// sha512sig1h.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig1h instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig1h(input logic [31:0] rs1, input logic [31:0] rs2,
output logic [31:0] DataOut);
// rs1 shifts
logic [31:0] shift3;
logic [31:0] shift6;
logic [31:0] shift19;
// rs2 shifts
logic [31:0] shift29;
logic [31:0] shift13;
// shift rs1
assign shift3 = rs1 << 3;
assign shift6 = rs1 >> 6;
assign shift19 = rs1 >> 19;
// shift rs2
assign shift29 = rs2 >> 29;
assign shift13 = rs2 << 13;
// XOR Shifted registers for output
assign DataOut = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift13;
endmodule

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///////////////////////////////////////////
// sha512sig1l.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024
//
// Purpose: sha512sig1l instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sig1l(input logic [31:0] rs1, input logic [31:0] rs2,
output logic [31:0] DataOut);
// rs1 shift logic
logic [31:0] shift3;
logic [31:0] shift6;
logic [31:0] shift19;
// rs2 shift logics
logic [31:0] shift29;
logic [31:0] shift26;
logic [31:0] shift13;
// Shift rs1
assign shift3 = rs1 << 3;
assign shift6 = rs1 >> 6;
assign shift19 = rs1 >> 19;
// Shift rs2
assign shift29 = rs2 >> 29;
assign shift26 = rs2 << 26;
assign shift13 = rs2 << 13;
assign DataOut = shift3 ^ shift6 ^ shift19 ^ shift29 ^ shift26 ^ shift13;
endmodule

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///////////////////////////////////////////
// sha512sum0.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sum0 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum0(input logic [63:0] rs1, output logic [63:0] result);
logic [63:0] ror28;
logic [63:0] ror34;
logic [63:0] ror39;
assign ror28 = {rs1[27:0], rs1[63:28]};
assign ror34 = {rs1[33:0], rs1[63:34]};
assign ror39 = {rs1[38:0], rs1[63:39]};
// Assign output to xor of 3 rotates
assign result = ror28 ^ ror34 ^ ror39;
endmodule

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///////////////////////////////////////////
// sha512sum0r.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sum0r instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum0r(input logic [31:0] rs1, input logic [31:0] rs2,
output logic [31:0] DataOut);
// RS1 shifts
logic [31:0] shift25;
logic [31:0] shift30;
logic [31:0] shift28;
// RS2 shifts
logic [31:0] shift7;
logic [31:0] shift2;
logic [31:0] shift4;
// Shift rs1
assign shift25 = rs1 << 25;
assign shift30 = rs1 << 30;
assign shift28 = rs1 >> 28;
// Shift rs2
assign shift7 = rs2 >> 7;
assign shift2 = rs2 >> 2;
assign shift4 = rs2 << 4;
// Set output to XOR of shifted values
assign DataOut = shift25 ^ shift30 ^ shift28 ^ shift7 ^ shift2 ^ shift4;
endmodule

41
src/ieu/sha_instructions/sha512sum1.sv Normal file
View file

@ -0,0 +1,41 @@
///////////////////////////////////////////
// sha512sum1.sv
//
// Written: kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sum1 instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum1(input logic [63:0] rs1, output logic [63:0] result);
logic [63:0] ror14;
logic [63:0] ror18;
logic [63:0] ror41;
assign ror14 = {rs1[13:0], rs1[63:14]};
assign ror18 = {rs1[17:0], rs1[63:18]};
assign ror41 = {rs1[40:0], rs1[63:41]};
// Assign output to xor of 3 rotates
assign result = ror14 ^ ror18 ^ ror41;
endmodule

54
src/ieu/sha_instructions/sha512sum1r.sv Normal file
View file

@ -0,0 +1,54 @@
///////////////////////////////////////////
// sha512sum1r.sv
//
// Written: ryan.swann@okstate.edu, kelvin.tran@okstate.edu, james.stine@okstate.edu
// Created: 6 February 2024
//
// Purpose: sha512sum1r instruction
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module sha512sum1r(input logic [31:0] rs1, input logic [31:0] rs2,
output logic [31:0] DataOut);
// Declare logic for rs1 shifts
logic [31:0] shift1by23;
logic [31:0] shift1by14;
logic [31:0] shift1by18;
// Declare logic for rs2 shifts
logic [31:0] shift2by9;
logic [31:0] shift2by18;
logic [31:0] shift2by14;
// Shift RS1
assign shift1by23 = rs1 << 23;
assign shift1by14 = rs1 >> 14;
assign shift1by18 = rs1 >> 18;
// Shift RS2
assign shift2by9 = rs2 >> 9;
assign shift2by18 = rs2 << 18;
assign shift2by14 = rs2 << 14;
// Assign output to xor of shifts
assign DataOut = shift1by23 ^ shift1by14 ^ shift1by18 ^ shift2by9 ^ shift2by18 ^ shift2by14;
endmodule

32
testbench/common/instrNameDecTB.sv
View file

@ -58,6 +58,17 @@ module instrNameDecTB(
else if (funct7[6:1] == 6'b010010) name = "BCLRI";
else if (funct7[6:1] == 6'b011010) name = "BINVI";
else if (funct7[6:1] == 6'b001010) name = "BSETI";
else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "ZIP";
else if (funct7 == 7'b0011000 && rs2 == 5'b00000) name = "AES64IM";
else if (funct7 == 7'b0011000 && rs2[4] == 1'b1) name = "AES64KS1I";
else if (funct7 == 7'b0001000 && rs2 == 5'b00010) name = "SHA256SIG0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00011) name = "SHA256SIG1";
else if (funct7 == 7'b0001000 && rs2 == 5'b00000) name = "SHA256SUM0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00001) name = "SHA256SUM1";
else if (funct7 == 7'b0001000 && rs2 == 5'b00110) name = "SHA512SIG0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00111) name = "SHA512SIG1";
else if (funct7 == 7'b0001000 && rs2 == 5'b00100) name = "SHA512SUM0";
else if (funct7 == 7'b0001000 && rs2 == 5'b00101) name = "SHA512SUM1";
else if (funct7 == 7'b0110000) begin
case (rs2)
5'b00000: name = "CLZ";
@ -77,6 +88,8 @@ module instrNameDecTB(
else if (funct7[6:1] == 6'b011000) name = "RORI";
else if (funct7[6:1] == 6'b010010) name = "BEXTI";
else if (funct7 == 7'b0010100 & rs2 == 5'b00111) name = "ORC.B";
else if (imm == 12'b011010000111) name = "BREV8";
else if (funct7 == 7'b0000100 && rs2 == 5'b01111) name = "UNZIP";
else name = "ILLEGAL";
10'b0010011_110: if (rd == 0 & rs2 == 0) name = "PREFETCH.I";
else if (rd == 0 & rs2 == 1) name = "PREFETCH.R";
@ -130,6 +143,21 @@ module instrNameDecTB(
10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
else if (funct7 == 7'b0000001) name = "MUL";
else if (funct7 == 7'b0100000) name = "SUB";
else if (funct7[4:0] == 5'b10101) name = "AES32DSI";
else if (funct7[4:0] == 5'b10111) name = "AES32DSMI";
else if (funct7 == 7'b0011101) name = "AES64DS";
else if (funct7 == 7'b0011111) name = "AES64DSM";
else if (funct7[4:0] == 5'b10001) name = "AES32ESI";
else if (funct7[4:0] == 5'b10011) name = "AES32ESMI";
else if (funct7 == 7'b0011001) name = "AES64ES";
else if (funct7 == 7'b0011011) name = "AES64ESM";
else if (funct7 == 7'b0111111) name = "AES64KS2";
else if (funct7 == 7'b0101110) name = "SHA512SIG0H";
else if (funct7 == 7'b0101010) name = "SHA512SIG0L";
else if (funct7 == 7'b0101111) name = "SHA512SIG1H";
else if (funct7 == 7'b0101011) name = "SHA512SIG1L";
else if (funct7 == 7'b0101000) name = "SHA512SUM0R";
else if (funct7 == 7'b0101001) name = "SHA512SUM1R";
else name = "ILLEGAL";
10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
else if (funct7 == 7'b0000001) name = "MULH";
@ -153,7 +181,9 @@ module instrNameDecTB(
else if (funct7 == 7'b0010000) name = "SH2ADD";
else if (funct7 == 7'b0000101) name = "MIN";
else if (funct7 == 7'b0100000) name = "ORN";
else if (funct7 == 7'b0000100) name = "ZEXT.H";
else if (funct7 == 7'b0000100 && rs2 == 5'b00000) name = "ZEXT.H";
else if (funct7 == 7'b0000100 && op == 7'b0110011) name = "PACK";
else if (funct7 == 7'b0000100 && op == 7'b0111011) name = "PACKW";
else name = "ILLEGAL";
10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
else if (funct7 == 7'b0000001) name = "DIVU";

7
testbench/common/wallyTracer.sv
View file

@ -63,7 +63,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic CSRWriteM, CSRWriteW;
logic [11:0] CSRAdrM, CSRAdrW;
logic wfiM;
logic InterruptM;
logic InterruptM, InterruptW;
assign clk = testbench.dut.clk;
// assign InstrValidF = testbench.dut.core.ieu.InstrValidF; // not needed yet
@ -266,6 +266,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
flopenrc #(P.XLEN)PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
flopenrc #(1) InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
flopenrc #(1) TrapWReg (clk, reset, 1'b0, ~StallW, TrapM, TrapW);
flopenrc #(1) InterruptWReg (clk, reset, 1'b0, ~StallW, InterruptM, InterruptW);
flopenrc #(1) HaltWReg (clk, reset, 1'b0, ~StallW, HaltM, HaltW);
// **** remove? are these used?
@ -287,9 +288,9 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
assign rvvi.order[0][0] = CSRArray[12'hB02]; // TODO: IMPERAS Should be event order
assign rvvi.insn[0][0] = InstrRawW;
assign rvvi.pc_rdata[0][0] = PCW;
assign rvvi.trap[0][0] = 0;
assign rvvi.trap[0][0] = TrapW;
assign rvvi.halt[0][0] = HaltW;
assign rvvi.intr[0][0] = 0;
assign rvvi.intr[0][0] = InterruptW;
assign rvvi.mode[0][0] = PrivilegeModeW;
assign rvvi.ixl[0][0] = PrivilegeModeW == 2'b11 ? 2'b10 :
PrivilegeModeW == 2'b01 ? STATUS_SXL : STATUS_UXL;

12
testbench/testbench-xcelium.sv
View file

@ -129,6 +129,12 @@ module testbench;
"arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb;
"arch64zbc": if (P.ZBC_SUPPORTED) tests = arch64zbc;
"arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs;
"arch64zbkb": if (P.ZBKB_SUPPORTED) tests = arch64zbkb;
"arch64zbkc": if (P.ZBKC_SUPPORTED) tests = arch64zbkc;
"arch64zbkx": if (P.ZBKX_SUPPORTED) tests = arch64zbkx;
"arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd;
"arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne;
"arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh;
endcase
end else begin // RV32
case (TEST)
@ -159,6 +165,12 @@ module testbench;
"arch32zbb": if (P.ZBB_SUPPORTED) tests = arch32zbb;
"arch32zbc": if (P.ZBC_SUPPORTED) tests = arch32zbc;
"arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs;
"arch32zbkb": if (P.ZBKB_SUPPORTED) tests = arch32zbkb;
"arch32zbkc": if (P.ZBKC_SUPPORTED) tests = arch32zbkc;
"arch32zbkx": if (P.ZBKX_SUPPORTED) tests = arch32zbkx;
"arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd;
"arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne;
"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
endcase
end
if (tests.size() == 0) begin

13
testbench/testbench.sv
View file

@ -124,6 +124,7 @@ module testbench;
"imperas64f": if (P.F_SUPPORTED) tests = imperas64f;
"imperas64d": if (P.D_SUPPORTED) tests = imperas64d;
"imperas64m": if (P.M_SUPPORTED) tests = imperas64m;
"wally64q": if (P.Q_SUPPORTED) tests = wally64q;
"wally64a": if (P.A_SUPPORTED) tests = wally64a;
"imperas64c": if (P.C_SUPPORTED) tests = imperas64c;
else tests = imperas64iNOc;
@ -147,6 +148,12 @@ module testbench;
"arch64zfaf": if (P.ZFA_SUPPORTED) tests = arch64zfaf;
"arch64zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch64zfad;
"buildroot": tests = buildroot;
"arch64zbkb": if (P.ZBKB_SUPPORTED) tests = arch64zbkb;
"arch64zbkc": if (P.ZBKC_SUPPORTED) tests = arch64zbkc;
"arch64zbkx": if (P.ZBKX_SUPPORTED) tests = arch64zbkx;
"arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd;
"arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne;
"arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh;
endcase
end else begin // RV32
case (TEST)
@ -189,6 +196,12 @@ module testbench;
"arch32zfh_divsqrt": if (P.ZFH_SUPPORTED) tests = arch32zfh_divsqrt;
"arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf;
"arch32zfad": if (P.ZFA_SUPPORTED & P.D_SUPPORTED) tests = arch32zfad;
"arch32zbkb": if (P.ZBKB_SUPPORTED) tests = arch32zbkb;
"arch32zbkc": if (P.ZBKC_SUPPORTED) tests = arch32zbkc;
"arch32zbkx": if (P.ZBKX_SUPPORTED) tests = arch32zbkx;
"arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd;
"arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne;
"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
endcase
end
if (tests.size() == 0) begin

100
testbench/tests.vh
View file

@ -869,6 +869,10 @@ string imperas32f[] = '{
"rv32i_m/I/XORI-01"
};
string wally64q[] = '{
`WALLYTEST,
"rv64i_m/Q/src/WALLY-q-01.S"
};
string wally64a[] = '{
`WALLYTEST,
@ -990,6 +994,53 @@ string imperas32f[] = '{
"rv32i_m/B/src/bseti-01.S"
};
string arch32zbkb[] = '{
`RISCVARCHTEST,
"rv32i_m/K/src/brev8_32-01.S",
"rv32i_m/K/src/pack-01.S",
"rv32i_m/K/src/packh-01.S",
"rv32i_m/K/src/unzip-01.S",
"rv32i_m/K/src/zip-01.S"
};
string arch32zbkc[] = '{
`RISCVARCHTEST,
"rv32i_m/B/src/clmul-01.S",
"rv32i_m/B/src/clmulh-01.S"
};
string arch32zbkx[] = '{
`RISCVARCHTEST,
"rv32i_m/K/src/xperm8-01.S",
"rv32i_m/K/src/xperm4-01.S"
};
string arch32zknd[] = '{
`RISCVARCHTEST,
"rv32i_m/K/src/aes32dsi-01.S",
"rv32i_m/K/src/aes32dsmi-01.S"
};
string arch32zkne[] = '{
`RISCVARCHTEST,
"rv32i_m/K/src/aes32esi-01.S",
"rv32i_m/K/src/aes32esmi-01.S"
};
string arch32zknh[] = '{
`RISCVARCHTEST,
"rv32i_m/K/src/sha256sig0-01.S",
"rv32i_m/K/src/sha256sig1-01.S",
"rv32i_m/K/src/sha256sum0-01.S",
"rv32i_m/K/src/sha256sum1-01.S",
"rv32i_m/K/src/sha512sig0h-01.S",
"rv32i_m/K/src/sha512sig0l-01.S",
"rv32i_m/K/src/sha512sig1h-01.S",
"rv32i_m/K/src/sha512sig1l-01.S",
"rv32i_m/K/src/sha512sum0r-01.S",
"rv32i_m/K/src/sha512sum1r-01.S"
};
string arch64m[] = '{
`RISCVARCHTEST,
"rv64i_m/M/src/div-01.S",
@ -1748,6 +1799,55 @@ string arch64zbs[] = '{
"rv64i_m/B/src/bseti-01.S"
};
string arch64zbkb[] = '{
`RISCVARCHTEST,
"rv64i_m/K/src/brev8-01.S",
"rv64i_m/K/src/pack-01.S",
"rv64i_m/K/src/packh-01.S",
"rv64i_m/K/src/packw-01.S"
};
string arch64zbkc[] = '{
`RISCVARCHTEST,
"rv64i_m/B/src/clmul-01.S",
"rv64i_m/B/src/clmulh-01.S"
};
string arch64zbkx[] = '{
`RISCVARCHTEST,
"rv64i_m/K/src/xperm8-01.S",
"rv64i_m/K/src/xperm4-01.S"
};
string arch64zknd[] = '{
`RISCVARCHTEST,
"rv64i_m/K/src/aes64ds-01.S",
"rv64i_m/K/src/aes64dsm-01.S",
"rv64i_m/K/src/aes64im-01.S",
"rv64i_m/K/src/aes64ks1i-01.S",
"rv64i_m/K/src/aes64ks2-01.S"
};
string arch64zkne[] = '{
`RISCVARCHTEST,
"rv64i_m/K/src/aes64es-01.S",
"rv64i_m/K/src/aes64esm-01.S",
"rv64i_m/K/src/aes64ks1i-01.S",
"rv64i_m/K/src/aes64ks2-01.S"
};
string arch64zknh[] = '{
`RISCVARCHTEST,
"rv64i_m/K/src/sha256sig0-01.S",
"rv64i_m/K/src/sha256sig1-01.S",
"rv64i_m/K/src/sha256sum0-01.S",
"rv64i_m/K/src/sha256sum1-01.S",
"rv64i_m/K/src/sha512sig0-01.S",
"rv64i_m/K/src/sha512sig1-01.S",
"rv64i_m/K/src/sha512sum0-01.S",
"rv64i_m/K/src/sha512sum1-01.S"
};
string arch32priv[] = '{
`RISCVARCHTEST,
"rv32i_m/privilege/src/ebreak.S",

12
tests/riscof/spike/riscof_spike.py
View file

@ -131,6 +131,18 @@ class spike(pluginTemplate):
self.isa += '_Zbc'
if "Zbs" in ispec["ISA"]:
self.isa += '_Zbs'
if "Zbkb" in ispec["ISA"]:
self.isa += '_Zbkb'
if "Zbkc" in ispec["ISA"]:
self.isa += '_Zbkc'
if "Zknd" in ispec["ISA"]:
self.isa += '_Zknd'
if "Zkne" in ispec["ISA"]:
self.isa += '_Zkne'
if "Zbkx" in ispec["ISA"]:
self.isa += '_Zbkx'
if "Zknh" in ispec["ISA"]:
self.isa += '_Zknh'
#TODO: The following assumes you are using the riscv-gcc toolchain. If
# not please change appropriately

2
tests/riscof/spike/spike_rv32e_isa.yaml
View file

@ -1,6 +1,6 @@
hart_ids: [0]
hart0:
ISA: RV32EMCZicsr_Zifencei
ISA: RV32EMCZicsr_Zifencei_Zbkc
physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [32]

3
tests/riscof/spike/spike_rv32gc_isa.yaml
View file

@ -1,6 +1,7 @@
hart_ids: [0]
hart0:
ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs
ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
# ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs
# ISA: RV32IMAFDCZicsr_Zicboz_Zifencei_Zca_Zba_Zbb_Zbc_Zbs # _Zbkb_Zcb
physical_addr_sz: 32
User_Spec_Version: '2.3'

4
tests/riscof/spike/spike_rv64gc_isa.yaml
View file

@ -2,12 +2,12 @@ hart_ids: [0]
hart0:
# ISA: RV64IMAFDCSUZicsr_Zicboz_Zifencei_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
# ISA: RV64IMAFDCSUZicsr_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbs # Zkbs_Zcb
ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
physical_addr_sz: 56
User_Spec_Version: '2.3'
supported_xlen: [64]
misa:
reset-val: 0x800000000014112D
reset-val: 0x800000000015112D
rv32:
accessible: false
rv64:

36
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/references/WALLY-q-01.reference_output Normal file
View file

@ -0,0 +1,36 @@
00000000 # fsq of 1
00000000
00000000
3fff0000
dead4000 # fsh of 1
deadbeef
deadbeef
deadbeef
00000000 # fsq of 3
00000000
00000000
40008000
00000000 # fsq of -1
00000000
00000000
bfff0000
00000000 # fsq of 6
00000000
00000000
40018000
00000000 # fsq of -4
00000000
00000000
C0010000
00000000 # fsq of -2
00000000
00000000
C0000000
00000000 # fsq of 4
00000000
00000000
40010000
00000000 # fsq of 2
00000000
00000000
40000000

154
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/Q/src/WALLY-q-01.S Normal file
View file

@ -0,0 +1,154 @@
///////////////////////////////////////////
// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-ADD.S
// David_Harris@hmc.edu & Rose Thompson
// Created 07 March 2024
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64IFDQZfh_Zicsr")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*Q.*);def TEST_CASE_1=True;def NO_SAIL=True",flq-align)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
#endif
# turn on the floating point unit
li x7, 1
slli x7, x7, 13
csrw mstatus, x7
li x4, 1 # 3fff 0000 0000 0000 0000 0000 0000 0000
li x2, 2 # 4000 0000 0000 0000 0000 0000 0000 0000
fcvt.q.w f2, x2
fcvt.q.w f4, x4
fcvt.h.w f5, x2 # 4000
# test quad load/store
fsq f4, 0(x3)
flq f7, 0(x3)
fsq f7, 0(x1)
# test half load/store
fsh f5, 16(x3)
flh f6, 16(x3)
fsh f6, 16(x1)
# 1 + 2 = 3 # 4000 8000 0000 0000 0000 0000 0000 0000
fadd.q f8, f2, f4
fsq f8, 32(x1)
# 1 - 2 = -1
fsub.q f9, f4, f2 # bfff 0000000000000000000000000000
fsq f9, 48(x1)
# 2 * 3 = 6
fmul.q f10, f2, f8 # 4001 8000000000000000000000000000
fsq f10, 64(x1)
# 6 * (-1) + 2 = -4
fmadd.q f11, f10, f9, f2 # C001 0000000000000000000000000000
fsq f11, 80(x1)
# -4 / 2 = -2
fdiv.q f12, f11, f2 # C000 0000000000000000000000000000
fsq f12, 96(x1)
# sign injection (-4, 1) = 4
fsgnj.q f13, f11, f4 # 4001 0000000000000000000000000000
fsq f13, 112(x1)
# sqrt(4) = 2
fsqrt.q f14, f13 # 4000 0000000000000000000000000000
fsq f14, 128(x1)
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
test_dataset_0:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_1:
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
signature_x1_1:
.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
.int 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef
rvtest_sig_end:
RVMODEL_DATA_END