github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-06-27 17:01:20 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Update to work with new version of Sail

Browse source
This commit is contained in:
Jordan Carlin 2025-05-09 15:43:31 -07:00
parent af7c219e37
commit 3b0f763674
No known key found for this signature in database
1 changed files with 1 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

5
tests/riscof/sail_cSim/riscof_sail_cSim.py
View file

@ -46,7 +46,6 @@ class sail_cSim(pluginTemplate):
ispec = utils.load_yaml(isa_yaml)['hart0']
self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
self.isa = 'rv' + self.xlen
self.sailargs = ' --pmp-count=16 --pmp-grain=0 ' # Hardcode pmp-count and pmp-grain for now. Make configurable later once Sail has easier configuration
self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ('ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '))
if "I" in ispec["ISA"]:
self.isa += 'i'
@ -62,8 +61,6 @@ class sail_cSim(pluginTemplate):
self.isa += 'f'
if "D" in ispec["ISA"]:
self.isa += 'd'
if "Zcb" in ispec["ISA"]: # for some strange reason, Sail requires a command line argument to enable Zcb
self.sailargs += "--enable-zcb"
if "Q" in ispec["ISA"]:
self.isa += 'q'
objdump = "riscv64-unknown-elf-objdump"
@ -117,7 +114,7 @@ class sail_cSim(pluginTemplate):
reference_output = re.sub("/src/","/references/", re.sub(".S",".reference_output", test))
execute += f'cut -c-{8:g} {reference_output} > {sig_file}' #use cut to remove comments when copying
else:
execute += self.sail_exe[self.xlen] + ' -z268435455 -i --trace=step ' + self.sailargs + f' --test-signature={sig_file} {elf} > {test_name}.log 2>&1;'
execute += self.sail_exe[self.xlen] + f' --trace=step --test-signature={sig_file} {elf} > {test_name}.log 2>&1;'
# Coverage
# Generate trace from sail log