Removed .* from muldiv.

.gitignore

@@ -19,27 +19,19 @@ wlft*
 /imperas-riscv-tests/FunctionRadix.addr
 /imperas-riscv-tests/ProgramMap.txt
 /imperas-riscv-tests/logs
-/wally-pipelined/linux-testgen/qemu_output.txt
-/wally-pipelined/linux-testgen/qemu_in_gdb_format.txt
 *.o
 *.d
 testsBP/*/*/*.elf*
 testsBP/*/OBJ/*
 testsBP/*/*.a
-wally-pipelined/linux-testgen/linux-testvectors/*
-wally-pipelined/linux-testgen/nohup*
-wally-pipelined/linux-testgen/x*
-!wally-pipelined/linux-testgen/linux-testvectors/tvCopier.py
-!wally-pipelined/linux-testgen/linux-testvectors/tvLinker.sh
-!wally-pipelined/linux-testgen/linux-testvectors/tvUnlinker.sh
-!wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs
-wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs/*
-!wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs/git_create_dir.txt
-wally-pipelined/linux-testgen/buildroot/
-wally-pipelined/linux-testgen/buildroot-image-output
-wally-pipelined/linux-testgen/buildroot-config-src/main.config.old
-wally-pipelined/linux-testgen/buildroot-config-src/linux.config.old
-wally-pipelined/linux-testgen/buildroot-config-src/busybox.config.old
+tests/linux-testgen/linux-testvectors/*
+!tests/linux-testgen/linux-testvectors/tvCopier.py
+!tests/linux-testgen/linux-testvectors/tvLinker.sh
+!tests/linux-testgen/linux-testvectors/tvUnlinker.sh
+tests/linux-testgen/buildroot
+tests/linux-testgen/buildroot-image-output
+tests/linux-testgen/buildroot-config-src/main.config.old
+tests/linux-testgen/buildroot-config-src/linux.config.old
+tests/linux-testgen/buildroot-config-src/busybox.config.old
 wally-pipelined/regression/slack-notifier/slack-webhook-url.txt
 wally-pipelined/regression/logs
-

README.md

@@ -8,16 +8,15 @@ To use Wally on Linux:
 ```
 git clone https://github.com/davidharrishmc/riscv-wally
 cd riscv-wally
-cd tests
-cd imperas-riscv-tests
-make
-cd ../addins
+cd addins
+*** can these clones be replaced with git submodule commands?
 git clone https://github.com/riscv-non-isa/riscv-arch-test
 git clone https://github.com/riscv-software-src/riscv-isa-sim
 cd riscv-isa-sim
+*** replace these with a copy from ../install/F and ../install/D containing the Makefile.includes already updated
 cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv32i_m/F
 <edit arch_test_target/spike/device/rv32i_m/F/Makefile.include line 35 and change --isa=rv32i to --isa=rv32if>
-cp -r arch_test_target/spike/device/rv32i_m/I arch_test_target/spike/device/rv64i_m/D
+cp -r arch_test_target/spike/device/rv64i_m/I arch_test_target/spike/device/rv64i_m/D
 <edit arch_test_target/spike/device/rv64i_m/D/Makefile.include line 35 and change --isa=rv64i to --isa=rv64id>
 mkdir build
 cd build
@@ -33,7 +32,14 @@ edit Makefile.include
 make
 make XLEN=32
 exe2memfile.pl work/*/*/*.elf  # converts ELF files to a format that can be read by Modelsim
-cd ../../wally-pipelined/linux-testgen/linux-testvectors
+cd ../../tests
+cd imperas-riscv-tests
+make
+cd ../wally-riscv-arch-test
+make
+make XLEN=32
+exe2memfile.pl work/*/*/*.elf  # converts ELF files to a format that can be read by Modelsim
+cd ../linux-testgen/linux-testvectors
 ./tvLinker.sh
 ```
 

tests/linux-testgen/linux-testvectors/tvLinker.sh

@@ -0,0 +1,3 @@
+echo "Warning: this script will only work if your repo is on Tera"
+ln -s /courses/e190ax/linux-testvectors-shared/* ./
+echo "Done!"

tests/linux-testgen/testvector-generation/Makefile

@@ -0,0 +1,13 @@
+SHELL = /bin/sh
+
+CFLAG = -Wall -g
+CC = clang
+
+all: fixBinMem
+
+fixBinMem: fixBinMem.c
+	${CC} ${CFLAGS} fixBinMem.c -o fixBinMem
+	chmod +x fixBinMem
+
+clean:
+	-rm -f fixBinMem

tests/linux-testgen/testvector-generation/checkpointSweep.sh

@@ -0,0 +1,5 @@
+for index in {0..105}
+do 
+    instrs=$(((400+$index)*1000000))
+    echo "y" | ./genCheckpoint.sh $instrs
+done

tests/linux-testgen/testvector-generation/debug.sh

@@ -5,6 +5,7 @@ tcpPort=1237
 # Run without GDB
 ($customQemu \
 -M virt \
+-m 128M \
 -nographic \
 -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
 -singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on)

tests/linux-testgen/testvector-generation/fixBinMem.c

@@ -0,0 +1,33 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdint.h>
+int main(int argc, char *argv[]) {
+    if (argc < 3){
+        fprintf(stderr, "Expected 2 arguments: <raw GDB dump> <output binary>\n");
+        exit(1);
+    }
+    char* rawGDBfilePath = argv[1];
+    FILE* rawGDBfile;
+    if ((rawGDBfile = fopen(rawGDBfilePath,"rb"))==NULL) {
+        fprintf(stderr, "File not found: %s\n",rawGDBfilePath);
+        exit(1);
+    }
+    char* outFilePath = argv[2];
+    FILE* outFile = fopen(outFilePath,"w");
+    uint64_t qemuWord;
+    uint64_t verilogWord;
+    int bytesReturned=0;
+    do {
+        bytesReturned=fread(&qemuWord, 8, 1, rawGDBfile);
+        verilogWord = (((qemuWord>>0 )&0xff)<<56 | 
+                       ((qemuWord>>8 )&0xff)<<48 | 
+                       ((qemuWord>>16)&0xff)<<40 | 
+                       ((qemuWord>>24)&0xff)<<32 | 
+                       ((qemuWord>>32)&0xff)<<24 | 
+                       ((qemuWord>>40)&0xff)<<16 | 
+                       ((qemuWord>>48)&0xff)<<8  | 
+                       ((qemuWord>>56)&0xff)<<0);
+        fwrite(&verilogWord, 8, 1, outFile);
+    } while(bytesReturned!=0);
+    return 0;
+}

tests/linux-testgen/testvector-generation/genCheckpoint.gdb

@@ -13,7 +13,7 @@ define genCheckpoint
     set $checkPC=$arg3
     set $checkPCoccurences=$arg4
     eval "set $statePath = \"%s/stateGDB.txt\"", $statePath
-    eval "set $ramPath = \"%s/ramGDB.txt\"", $ramPath
+    eval "set $ramPath = \"%s/ramGDB.bin\"", $ramPath
 
     # Connect to QEMU session
     eval "target extended-remote :%d",$tcpPort
@@ -46,10 +46,7 @@ define genCheckpoint
 
     # Log main memory to a file
     printf "GDB storing RAM to %s\n", $ramPath
-    eval "set logging file %s", $ramPath
-    set logging on
-    x/134217728xb 0x80000000
-    set logging off
+    eval "dump binary memory %s 0x80000000 0xffffffff", $ramPath
     
     kill
     q

tests/linux-testgen/testvector-generation/genCheckpoint.sh

@@ -3,36 +3,57 @@
 source  genSettings.sh
 tcpPort=1236
 
-instrs=480000000
+# Parse Commandline Arg
+if [ "$#" -ne 1 ]; then
+    echo "genCheckpoint requires 1 argument: <num instrs>" >&2
+    exit 1
+fi
+instrs=$1
+if ! [ "$instrs" -eq "$instrs" ] 2> /dev/null
+then
+    echo "Error expected integer number of instructions, got $instrs" >&2
+    exit 1
+fi
 checkOutDir="$outDir/checkpoint$instrs"
 checkIntermedDir="$checkOutDir/intermediate-outputs"
 
-
 read -p "This scripts is going to create a checkpoint at $instrs instrs.
 Is that what you wanted? (y/n) " -n 1 -r
 echo
 if [[ $REPLY =~ ^[Yy]$ ]]
 then
+    echo "Creating checkpoint at $instrs instructions!"
     mkdir -p $checkOutDir
     mkdir -p $checkIntermedDir
+    
+    # Identify instruction in trace
     instr=$(sed "${instrs}q;d" "../linux-testvectors/all.txt")
-    echo "Found ${instrs}th instr: ${instr}."
+    echo "Found ${instrs}th instr: ${instr}"
     pc=$(echo $instr | cut -d " " -f1)
     asm=$(echo $instr | cut -d " " -f2)
     occurences=$(($(head -$instrs "../linux-testvectors/all.txt" | grep -c "${pc} ${asm}")-1))
     echo "It occurs ${occurences} times before the ${instrs}th instr." 
-    # Simulate QEMU, parse QEMU trace, run GDB script which logs a bunch of data at the checkpoint
+
+    # GDB+QEMU
+    echo "Starting QEMU with attached GDB script at $(date +%H:%M:%S)"
     ($customQemu \
     -M virt \
     -nographic \
     -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \
     -singlestep -rtc clock=vm -icount shift=1,align=off,sleep=on,rr=replay,rrfile="$intermedDir/$recordFile" \
     -gdb tcp::$tcpPort -S) \
-    & riscv64-unknown-elf-gdb -x genCheckpoint.gdb -ex "genCheckpoint $tcpPort $instrs \"$checkIntermedDir\" \"$pc\" $occurences"
+    & riscv64-unknown-elf-gdb --quiet \
+    -x genCheckpoint.gdb -ex "genCheckpoint $tcpPort $instrs \"$checkIntermedDir\" \"$pc\" $occurences"
+    echo "Completed GDB script completed at $(date +%H:%M:%S)"
+
     # Post-Process GDB outputs
     ./parseState.py "$checkOutDir"
-    ./fix_mem.py "$checkIntermedDir/ramGDB.txt" "$checkOutDir/ram.txt"
-    tail -n+$($instrs+1) "$outDir/$traceFile" > "$checkOutDir/$traceFile"
+    echo "Changing Endianness at $(date +%H:%M:%S)"
+    make
+    ./fixBinMem "$checkIntermedDir/ramGDB.bin" "$checkOutDir/ram.bin"
+    echo "Creating truncated trace at $(date +%H:%M:%S)"
+    tail -n+$instrs "$outDir/$traceFile" > "$checkOutDir/$traceFile"
+    echo "Checkpoint completed at $(date +%H:%M:%S)"
 else
     echo "You can change the number of instructions by editing the \"instrs\" variable in this script."
     echo "Have a nice day!"

tests/linux-testgen/testvector-generation/genInitMem.sh

@@ -16,8 +16,8 @@ then
     & riscv64-unknown-elf-gdb -quiet -x genInitMem.gdb -ex "genInitMem $tcpPort \"$intermedDir\""
 
     echo "Translating Mem from GDB to Questa format"
-    ./fix_mem.py "$intermedDir/bootmemGDB.txt" "$outDir/bootmem.txt"
-    ./fix_mem.py "$intermedDir/ramGDB.txt"     "$outDir/ram.txt"
+    ./fixTxtMem.py "$intermedDir/bootmemGDB.txt" "$outDir/bootmem.txt"
+    ./fixTxtMem.py "$intermedDir/ramGDB.txt"     "$outDir/ram.txt"
     echo "Done"
 
     echo "Creating debugging objdump of linux image"

tests/linux-testgen/testvector-generation/genSettings.sh

@@ -4,7 +4,7 @@
 # *** on the long term we'll want to include QEMU in the addins folder
 export customQemu="/courses/e190ax/qemu_sim/rv64_initrd/qemu_experimental/qemu/build/qemu-system-riscv64"
 export imageDir="../buildroot-image-output"
-export outDir="../linux-testvectors-experimental"
+export outDir="../linux-testvectors"
 export intermedDir="$outDir/intermediate-outputs"
 export traceFile="all.txt"
 export recordFile="all.qemu"

wally-pipelined/config/buildroot/wally-config.vh

@@ -31,8 +31,7 @@
 `define BUILDROOT 1
 `define BUSYBEAR 0
 `define LINUX_FIX_READ {'h10000005}
-`define LINUX_TEST_VECTORS "../linux-testgen/linux-testvectors/"
-//`define LINUX_TEST_VECTORS "/courses/e190ax/buildroot_boot/"
+`define LINUX_TEST_VECTORS "../../tests/linux-testgen/linux-testvectors/"
 // RV32 or RV64: XLEN = 32 or 64
 `define XLEN 64
 
@@ -114,8 +113,8 @@
 `define PLIC_NUM_SRC 53
 `define PLIC_UART_ID 4
 
-`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt"
-`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt"
+`define TWO_BIT_PRELOAD "../config/buildroot/twoBitPredictor.txt"
+`define BTB_PRELOAD "../config/buildroot/BTBPredictor.txt"
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0

wally-pipelined/config/busybear/wally-config.vh

@@ -1,127 +0,0 @@
-//////////////////////////////////////////
-// busybear-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define QEMU 0
-`define BUILDROOT 0
-`define BUSYBEAR 1
-`define LINUX_FIX_READ {'h10000005}
-`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/"
-//`define LINUX_TEST_VECTORS "../../../busybear_boot/"
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 64
-
-`define MISA (32'h0014112D)
-`define ZICSR_SUPPORTED 1
-`define ZIFENCEI_SUPPORTED 1
-`define ZICOUNTERS_SUPPORTED 1
-`define COUNTERS 32
-`define DESIGN_COMPILER 0
-
-// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
-`define MEM_DTIM 1
-`define MEM_ICACHE 1
-`define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 2048
-`define DCACHE_BLOCKLENINBITS 256
-`define DCACHE_REPLBITS 3
-`define ICACHE_NUMWAYS 1
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_BLOCKLENINBITS 256
-
-// Integer Divider Configuration
-// DIV_BITSPERCYCLE must be 1, 2, or 4
-`define DIV_BITSPERCYCLE 4
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 16
-
-// Address space
-`define RESET_VECTOR 64'h0000000000001000
-
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
-`define BOOTTIM_SUPPORTED 1'b1
-//`define BOOTTIM_BASE   56'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-//`define BOOTTIM_RANGE  56'h00003FFF
-`define BOOTTIM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-`define BOOTTIM_RANGE  56'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       56'h80000000
-`define TIM_RANGE      56'h07FFFFFF
-`define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  56'h02000000
-`define CLINT_RANGE 56'h0000FFFF
-`define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   56'h10012000
-`define GPIO_RANGE  56'h000000FF
-`define UART_SUPPORTED 1'b1
-`define UART_BASE   56'h10000000
-`define UART_RANGE  56'h00000007
-`define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   56'h0C000000
-`define PLIC_RANGE  56'h03FFFFFF
-
-// Bus Interface width
-`define AHBW 64
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 0
-
-// Hardware configuration
-//`define UART_PRESCALE 1
-`define UART_PRESCALE 0
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 53
-`define PLIC_UART_ID 4
-
-`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt"
-`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt"
-`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
-`define BPRED_ENABLED 1
-
-
-

wally-pipelined/linux-testgen/WALLY-README-UPDATES.txt

@@ -1,38 +0,0 @@
-Many of the scripts to build the linux ram.txt and trace files have changed over the Summer.
-Specifically the parsed*.txt files have all been replaced by a single all.txt file which contains
-all of the changes concurrent with a specific instruction.
-Each line of all.txt is encoded in the following way.
-
-The tokens are space deliminted (limitation the parsing function in system verilog).  This could be
-improved with some effort.
-
-<Token> denotes a required token.
-
-()? is an optional set of tokens.  Exactly 0 or 1 of this pattern will occur.
-The register update, memory operation, and CSR update are all possilbe but not present on all operations.
-()+ is used to denote a variable number of this pattern with at least 1 instance of the pattern.
-All integers are in hex and not zero extended.
-
-<PC> <instruction bits> <instruction text> (<GPR> <Reg Number> <Value>)? (<MemR|MemW|MemRW> <Address> <WriteData if valid> <ReadData if valid>)? (<CSR> (<Name> <Value>)+)?
-
-Example
-
-1010 182b283 ld_t0,24(t0) GPR 5 80000000 MemR 1018 0 80000000
-
-PC = 0x1010
-Instruction encoding = 0x182_b283
-instruction pneumonic (text) = ld_t0,24(t0)
-Updating x5 to 0x8000_0000
-Memory read at address 0x8000_0000 with read data of 0x8000_0000
-
-CSR updates can occur in more than once for a single instruction.  The multiple sets will appear as pairs of regsiter name followed by value.
-
-**** This trace is generated using the CreateTrace.sh script.
-
-Generation of ram.txt has not changed.  Still use logBuildrootMem.sh
-
-Only the all.txt and ram.txt are required to run modelsim's linux simulation. However there are three additional files will aid
-in the debugging process.  logBuildrootMem.sh was modified to also create an object dump from the vmlinux image.  Using
-extractFunctionRadix.sh the objdump is converted into two files vmlinux.objdump.addr and vmlinux.objdump.lab which contain
-the addresses and labels of global functions in the linux binarary. The linux test bench is configured to uses these two files
-to tell the user which function is currently being executed in modelsim.

wally-pipelined/linux-testgen/WALLY-README.txt

@@ -1,57 +0,0 @@
-If you do not need to update the Linux image, then go to ./linux-testvectors and 
-use tvCopier.py or tvLinker.sh to copy/link premade RAMs and testvectors from Tera.
-The RAMs are needed for Wally to run the Linux code, and the testvectors are needed
-to verify Wally is executing the code correctly.
-
-If you instead wish to regenerate the RAMs and testvectors from a new Linux image,
-you'll need to build the new Linux image, simulate it, and parse its output,
-as described below.
-
-*To build a new Linux image:
-     1. Git clone the Buildroot repository to ./buildroot:
-            git clone https://github.com/buildroot/buildroot.git 
-        For reference, Wally (*** will) be proven to work on an image built using
-        Buildroot when the following was the most recent commit to the Buildroot repo:
-            commit 4047e10ed6e20492bae572d4929eaa5d67eed746
-            Author: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
-            Date:   Wed Jun 30 06:27:10 2021 +0200
-
-     2. If you wish to modify the configs, then in ./buildroot:
-        a. Run "make menuconfig" or "make linux-menuconfig" or "make busybox-menuconfig".
-        b. Use the TUI (terminal UI) to load in the existing configs.
-
-           For menuconfig, you can load in the source file from
-               "../buildroot-config-src/main.config"
-
-           For linux-menuconfig or busybox-menuconfig, load in from 
-               "../../../../buildroot-config-src/<type>.config"
-           because for linux and busybox, make traverses down to
-                ./buildroot/output/build/<linux or busybox>.
-          
-           One annoying thing about the TUI is that if it has a path already loaded,
-           then before you can enter the new path to buildroot-config-src, you need to
-           delete the existing one from the textbox. Doing so requires more than backspace.
-           Once you've deleted as much of the existing path as you can see, arrow left to 
-           check if there is more text you need to delete.
-
-        c. Likewise, when you are done editing, tell the TUI to save to the same location.
-
-     3. Finally go to ./buildroot-config-src and run make-buildroot.sh.
-        This script copies ./buildroot-config-src/main.config to ./buildroot/.config
-        and then invokes make. This is clumsy but effective because buildroot
-        sometimes does weird things to .config, like moving it to .config.old and 
-        making a new .config -- doing so can really mess up symbolic/hard links.
-
-     4. If you'd like debugging symbols, then reconfigure Buildroot to output "vmlinux"
-        and run make-buildroot again.
-
-*To generate new RAMs and testvectors from a Linux image:
-    1. sym link ./buildroot-image-output to either your new image in ./buildroot/output/image 
-       or the existing image at /courses/e190ax/buildroot-image-output on Tera. 
-       This might require first deleting the empty buildroot-image-output directory.
-    2. Then run ./testvector-generation/logBuildrootMem.sh to generate RAMs.
-    3. Then run ./testvector-generation/logAllBuildroot.sh to generate testvectors.
-
-       These latter two steps require QEMU.
-       Note that you can only have one instance of QEMU open at a time!
-       At least on Tera, it seems. Check "ps -ef" to see if anybody else is running QEMU.

wally-pipelined/linux-testgen/linux-testvectors/intermediate-outputs/git_create_dir.txt

@@ -1 +0,0 @@
-This file only exists so that git will create ./.

wally-pipelined/linux-testgen/linux-testvectors/tvLinker.sh

@@ -1,9 +0,0 @@
-echo "Warning: this script will only work if your repo is on Tera"
-ln -s /courses/e190ax/buildroot_boot/all.txt all.txt
-ln -s /courses/e190ax/buildroot_boot/bootmem.txt bootmem.txt
-ln -s /courses/e190ax/buildroot_boot/ram.txt ram.txt
-ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump vmlinux.objdump
-ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump.addr vmlinux.objdump.addr
-ln -s /courses/e190ax/buildroot_boot/vmlinux.objdump.lab vmlinux.objdump.lab
-ln -s /courses/e190ax/buildroot_boot/checkpoint8500000 ./checkpoint8500000
-echo "Done!"

wally-pipelined/regression/Makefile

@@ -0,0 +1,6 @@
+make all:
+	make ../../tests/imperas-riscv-tests/
+	make ../../tests/wally-riscv-arch-test/
+	make XLEN=32 ../../tests/wally-riscv-arch-test/
+	exe2memfile.pl ../../tests/wally-riscv-arch-test/work/*/*/*.elf
+	cd ../../tests/linux-testgen/linux-testvectors/;./tvLinker.sh

wally-pipelined/regression/regression-wally.py

@@ -32,7 +32,7 @@ configs = [
 ]
 def getBuildrootTC(short):
     INSTR_LIMIT = 100000 # multiple of 100000
-    MAX_EXPECTED = 3000000
+    MAX_EXPECTED = 14000000
     if short:
         BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do "+str(INSTR_LIMIT)+" 1 0\n!"
         BRgrepstr=str(INSTR_LIMIT)+" instructions"
@@ -87,7 +87,7 @@ def main():
     # max out at a limited number of concurrent processes to not overwhelm the system
 
     if '-all' in sys.argv:
-        TIMEOUT_DUR = 3600 
+        TIMEOUT_DUR = 4*3600 
         configs.append(getBuildrootTC(short=False))
     else:
         TIMEOUT_DUR = 300

wally-pipelined/src/ifu/CodeAligner.py

@@ -87,12 +87,26 @@ def Mod_Space_at(Ln,loc,diff):
     
     return NewString
 
-def main_filehandler(overwrite=False):
+'''def main_filehandler(overwrite=False):
     for filename in os.listdir():
-        if ".py" not in filename:
+        if ".sv" in filename:
             GiantString = read_input(filename)
             SOV = ID_start(GiantString)
             ModifiedGS = modified_logNew(GiantString,SOV)
-            Newname = write_to_output(filename,ModifiedGS,overwrite)
+            Newname = write_to_output(filename,ModifiedGS,overwrite)'''
+def root_filehandler(path,overwrite=False):
+    for f in os.listdir(path):
+        if os.path.isdir(f):
+            root_filehandler(path+"/"+f)
+        else:
+            if ".sv" in f:
+                GiantString = read_input(f)
+                SOV = ID_start(GiantString)
+                ModifiedGS = modified_logNew(GiantString,SOV)
+                Newname = write_to_output(f,ModifiedGS,overwrite)
+                
+                
+def driver(overwrite=False):
+    root_filehandler(os.getcwd())
  
-main_filehandler(True)
+driver(True)

wally-pipelined/testbench/testbench-linux.sv

@@ -275,6 +275,7 @@ module testbench();
   endgenerate
   `INIT_CHECKPOINT_VAL(PC,         [`XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(MEDELEG,    [`XLEN-1:0]);
+  `INIT_CHECKPOINT_VAL(MIDELEG,    [`XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(MIE,        [11:0]);
   `INIT_CHECKPOINT_VAL(MIP,        [11:0]);
   `INIT_CHECKPOINT_VAL(MCAUSE,     [`XLEN-1:0]);
@@ -290,7 +291,9 @@ module testbench();
   `INIT_CHECKPOINT_VAL(SATP,       [`XLEN-1:0]);
   `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
 
-  assign initPriv = (initPC[0][`XLEN-1]) ? 2'h2 : 2'h3; // *** a hacky way to detect initial privilege level
+  integer ramFile;
+  integer readResult;
+  assign initPriv = (initPC[0][`XLEN-1]) ? 2'h1 : 2'h3; // *** a hacky way to detect initial privilege level
   initial begin
     force dut.hart.priv.SwIntM = 0;
     force dut.hart.priv.TimerIntM = 0;
@@ -308,7 +311,10 @@ module testbench();
     end else begin // checkpoint
       $sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT);
       checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir};
-      $readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.RAM);
+      //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.RAM);
+      ramFile = $fopen({checkpointDir,"ram.bin"}, "rb");
+      readResult = $fread(dut.uncore.dtim.RAM,ramFile);
+      $fclose(ramFile);
       traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
       traceFileM = $fopen({checkpointDir,"all.txt"}, "r");
       InstrCountW = CHECKPOINT;