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Merge pull request #396 from kipmacsaigoren/synthfix

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Synthesis fix
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David Harris 2023-08-27 07:22:13 -07:00 • committed by GitHub
commit 3bf09aa41b
3 changed files with 59 additions and 4 deletions
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2
config/shared/parameter-defs.vh
View file

@ -3,7 +3,7 @@
`include "BranchPredictorType.vh"
parameter cvw_t P = '{
localparam cvw_t P = '{
FPGA : FPGA,
XLEN : XLEN,
IEEE754 : IEEE754,

56
src/wrappers/wallypipelinedcorewrapper.sv Normal file
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@ -0,0 +1,56 @@
///////////////////////////////////////////
// wallypipelinedcorewrapper.sv
//
// Written: Kevin Kim kekim@hmc.edu 21 August 2023
// Modified:
//
// Purpose: A wrapper to set parameters. Vivado cannot set the top level parameters because it only supports verilog,
// not system verilog.
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
//`include "BranchPredictorType.vh"
`include "config.vh"
import cvw::*;
`include "parameter-defs.vh"
module wallypipelinedcorewrapper (
input logic clk, reset,
// Privileged
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
input logic [63:0] MTIME_CLINT,
// Bus Interface
input logic [P.XLEN-1:0] HRDATA,
input logic HREADY, HRESP,
output logic HCLK, HRESETn,
output logic [P.PA_BITS-1:0] HADDR,
output logic [32-1:0] HWDATA,
output logic [32/8-1:0] HWSTRB,
output logic HWRITE,
output logic [2:0] HSIZE,
output logic [2:0] HBURST,
output logic [3:0] HPROT,
output logic [1:0] HTRANS,
output logic HMASTLOCK
);
wallypipelinedcore #(P) core(.*);
endmodule

5
synthDC/scripts/synth.tcl
View file

@ -24,10 +24,9 @@ set saifpower $::env(SAIFPOWER)
set maxopt $::env(MAXOPT)
set drive $::env(DRIVE)
eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/}
#eval file copy -force [glob ${hdl_src}/../fpga/src/wallypipelinedsocwrapper.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/}
eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
@ -76,7 +75,7 @@ if { [shell_is_in_topographical_mode] } {
#set alib_library_analysis_path ./$outputDir
define_design_lib WORK -path ./$outputDir/WORK
analyze -f sverilog -lib WORK $my_verilog_files
elaborate $my_toplevel -parameter P -lib WORK
elaborate $my_toplevel -lib WORK
# Set the current_design
current_design $my_toplevel