mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-06-28 01:32:49 -04:00
Merge remote-tracking branch 'upstream/main' into soc
This commit is contained in:
Marcus Mellor
commit
3d58865ce3
242 changed files with 1700 additions and 1480226 deletions
18
.gitignore
vendored
18
.gitignore
vendored
|
|
@ -46,7 +46,6 @@ linux/buildroot
|
|||
linux/testvector-generation/boottrace.S
|
||||
linux/testvector-generation/boottrace_disasm.log
|
||||
sim/slack-notifier/slack-webhook-url.txt
|
||||
sim/logs
|
||||
fpga/generator/IP
|
||||
fpga/generator/vivado.*
|
||||
fpga/generator/.Xil/*
|
||||
|
|
@ -61,8 +60,13 @@ examples/asm/example/example
|
|||
examples/C/sum/sum
|
||||
examples/C/fir/fir
|
||||
examples/fp/softfloat_demo/softfloat_demo
|
||||
examples/fp/softfloat_demo/softfloat_demoDP
|
||||
examples/fp/softfloat_demo/softfloat_demoQP
|
||||
examples/fp/softfloat_demo/softfloat_demoSP
|
||||
examples/fp/fpcalc/fpcalc
|
||||
examples/fp/sqrttest/sqrttest
|
||||
examples/C/inline/inline
|
||||
examples/C/mcmodel/mcmodel
|
||||
examples/C/sum_mixed/sum_mixed
|
||||
examples/asm/trap/trap
|
||||
examples/asm/etc/pause
|
||||
|
|
@ -89,7 +93,6 @@ synthDC/hdl
|
|||
sim/power.saif
|
||||
tests/fp/vectors/*.tv
|
||||
synthDC/Summary.csv
|
||||
sim/wkdir
|
||||
tests/custom/work
|
||||
tests/custom/*/*/*.list
|
||||
tests/custom/*/*/*.elf
|
||||
|
|
@ -112,8 +115,6 @@ tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/src/*.S
|
|||
tests/wally-riscv-arch-test/riscv-test-suite/rv*i_m/I/Makefrag
|
||||
sim/branch_BP_GSHARE10.log
|
||||
sim/branch_BP_GSHARE16.log
|
||||
sim/cov/
|
||||
sim/covhtmlreport/
|
||||
sim/imperas.log
|
||||
sim/results-error/
|
||||
sim/test1.rep
|
||||
|
|
@ -186,3 +187,12 @@ sim/branch/*
|
|||
sim/obj_dir
|
||||
examples/verilog/fulladder/obj_dir
|
||||
config/deriv
|
||||
sim/questa/cov
|
||||
sim/questa/covhtmlreport/
|
||||
sim/questa/logs
|
||||
sim/questa/wkdir
|
||||
sim/verilator/logs
|
||||
sim/verilator/wkdir
|
||||
sim/vcs/logs
|
||||
sim/vcs/wkdir
|
||||
benchmarks/coremark/coremark_results.csv
|
||||
|
|
|
|||
4
Makefile
4
Makefile
|
|
@ -48,10 +48,12 @@ imperasdv_cov:
|
|||
vcover report -details -html sim/riscv.ucdb
|
||||
|
||||
funcovreg:
|
||||
iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover
|
||||
#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m --cover
|
||||
#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/I --cover
|
||||
#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/privilege --cover
|
||||
#iter-elf.bash --search ${WALLY}/tests/riscof/work/wally-riscv-arch-test/rv64i_m/Q --cover
|
||||
rm -f ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/*/src/*/dut/my.elf
|
||||
iter-elf.bash --search ${WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I --cover
|
||||
vcover report -details -html sim/riscv.ucdb
|
||||
|
||||
coverage:
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Subproject commit 8a52b016dbe1e2733cc168b9d6e5c93e39059d4d
|
||||
Subproject commit 8a0cdceca9f0b91b81905eb8497f6586bf8d1c6b
|
||||
|
|
@ -28,7 +28,8 @@ PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
|
|||
all: $(work_dir)/coremark.bare.riscv.elf.memfile
|
||||
|
||||
run:
|
||||
(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
|
||||
time wsim rv$(XLEN)gc coremark 2>&1 | tee $(work_dir)/coremark.sim.log
|
||||
#(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
|
||||
|
||||
$(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
|
||||
riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@
|
|||
|
||||
## Written: Shreesh Kulkarni, kshreesh5@gmail.com
|
||||
## Created: 20 March 2024
|
||||
## Modified: 22 March 2024
|
||||
## Purpose: Wally Coremark sweep Script for both 32 and 64 bit configs.
|
||||
## Modified: 08 April 2024
|
||||
## Purpose: Wally Coremark sweep Script for both 32 and 64 bit configs with csv file extraction.
|
||||
|
||||
## Documentation:
|
||||
|
||||
|
|
@ -30,16 +30,16 @@
|
|||
|
||||
|
||||
import os
|
||||
import re
|
||||
import csv
|
||||
# list of architectures to run.
|
||||
arch32_list = [
|
||||
arch_list = [
|
||||
"rv32gc_zba_zbb_zbc",
|
||||
"rv32im_zicsr_zba_zbb_zbc",
|
||||
"rv32gc",
|
||||
"rv32imc_zicsr",
|
||||
"rv32im_zicsr",
|
||||
"rv32i_zicsr"
|
||||
]
|
||||
arch64_list = [
|
||||
"rv32i_zicsr",
|
||||
"rv64gc_zba_zbb_zbc",
|
||||
"rv64im_zicsr_zba_zbb_zbc",
|
||||
"rv64gc",
|
||||
|
|
@ -47,24 +47,61 @@ arch64_list = [
|
|||
"rv64im_zicsr",
|
||||
"rv64i_zicsr"
|
||||
]
|
||||
xlen_values = ['32','64']
|
||||
for xlen_value in xlen_values:
|
||||
if(xlen_value=='32'):
|
||||
for arch in arch32_list:
|
||||
os.system("make clean")
|
||||
make_all = f"make all XLEN={xlen_value} ARCH={arch}"
|
||||
os.system(make_all)
|
||||
make_run = f"make run XLEN={xlen_value} ARCH={arch}"
|
||||
os.system(make_run)
|
||||
else:
|
||||
for arch in arch64_list:
|
||||
os.system("make clean")
|
||||
make_all = f"make all XLEN={xlen_value} ARCH={arch}"
|
||||
os.system(make_all)
|
||||
make_run = f"make run XLEN={xlen_value} ARCH={arch}"
|
||||
os.system(make_run)
|
||||
str="32"
|
||||
# Define regular expressions to match the desired fields
|
||||
mt_regex = r"Elapsed MTIME: (\d+).*?Elapsed MINSTRET: (\d+).*?COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+).*?CPI: \d+ / \d+ = (\d+\.\d+).*?Load Stalls (\d+).*?Store Stalls (\d+).*?D-Cache Accesses (\d+).*?D-Cache Misses (\d+).*?I-Cache Accesses (\d+).*?I-Cache Misses (\d+).*?Branches (\d+).*?Branches Miss Predictions (\d+).*?BTB Misses (\d+).*?Jump and JR (\d+).*?RAS Wrong (\d+).*?Returns (\d+).*?BP Class Wrong (\d+)"
|
||||
#cpi_regex = r"CPI: \d+ / \d+ = (\d+\.\d+)"
|
||||
#cmhz_regex = r"COREMARK/MHz Score: [\d,]+ / [\d,]+ = (\d+\.\d+)"
|
||||
# Open a CSV file to write the results
|
||||
with open('coremark_results.csv', mode='w', newline='') as csvfile:
|
||||
fieldnames = ['Architecture', 'MTIME','MINSTRET','CM / MHz','CPI','Load Stalls','Store Stalls','D$ Accesses',
|
||||
'D$ Misses','I$ Accesses','I$ Misses','Branches','Branch Mispredicts','BTB Misses',
|
||||
'Jump/JR','RAS Wrong','Returns','BP Class Pred Wrong']
|
||||
writer = csv.DictWriter(csvfile, fieldnames=fieldnames)
|
||||
|
||||
writer.writeheader()
|
||||
|
||||
# Loop through each architecture and run the make commands
|
||||
for arch in arch_list:
|
||||
if(str in arch):
|
||||
xlen_value='32'
|
||||
else:
|
||||
xlen_value='64'
|
||||
os.system("make clean")
|
||||
make_all = f"make all XLEN={xlen_value} ARCH={arch}"
|
||||
os.system(make_all)
|
||||
|
||||
make_run = f"make run XLEN={xlen_value} ARCH={arch}"
|
||||
print("Running: " + make_run)
|
||||
output = os.popen(make_run).read() # Capture the output of the command
|
||||
|
||||
# Extract the Coremark values using regular expressions
|
||||
mt_match = re.search(mt_regex, output,re.DOTALL)
|
||||
#cpi_match = re.search(cpi_regex,output,re.DOTALL)
|
||||
#cmhz_match = re.search(cmhz_regex,output,re.DOTALL)
|
||||
#minstret_match = re.search(minstret_regex,output)
|
||||
|
||||
# Write the architecture and extracted values to the CSV file
|
||||
|
||||
mtime = mt_match.group(1)
|
||||
minstret= mt_match.group(2)
|
||||
cmhz= mt_match.group(3)
|
||||
cpi= mt_match.group(4)
|
||||
lstalls= mt_match.group(5)
|
||||
swtalls= mt_match.group(6)
|
||||
dacc= mt_match.group(7)
|
||||
dmiss= mt_match.group(8)
|
||||
iacc= mt_match.group(9)
|
||||
imiss= mt_match.group(10)
|
||||
br= mt_match.group(11)
|
||||
brm= mt_match.group(12)
|
||||
btb= mt_match.group(13)
|
||||
jmp= mt_match.group(14)
|
||||
ras= mt_match.group(15)
|
||||
ret= mt_match.group(16)
|
||||
bpc= mt_match.group(17)
|
||||
#minstret = mt_instret_match.group(2)
|
||||
writer.writerow({'Architecture': arch, 'MTIME': mtime,'MINSTRET':minstret,'CM / MHz':cmhz,'CPI':cpi,
|
||||
'Load Stalls':lstalls,
|
||||
'Store Stalls':swtalls,'D$ Accesses':dacc,'D$ Misses':dmiss,'I$ Accesses':iacc,'I$ Misses':imiss,
|
||||
'Branches':br,'Branch Mispredicts':brm,'BTB Misses':btb,'Jump/JR':jmp,'RAS Wrong':ras,'Returns':ret,'BP Class Pred Wrong':bpc})
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
Directory="$1"
|
||||
Files="$1/*.log"
|
||||
|
||||
for Pred in "bimodal" "gshare"
|
||||
for Pred in "bimodal" "gshare" "local4" "local8" "local10"
|
||||
do
|
||||
for Size in $(seq 6 2 16)
|
||||
do
|
||||
|
|
@ -39,6 +39,15 @@ do
|
|||
SizeString="$Size $Size 18 1"
|
||||
elif [ $Pred = "bimodal" ]; then
|
||||
SizeString="$Size 18 1"
|
||||
elif [ $Pred = "local4" ]; then
|
||||
SizeString="$Size 4 18 1"
|
||||
Pred="yehpatt"
|
||||
elif [ $Pred = "local8" ]; then
|
||||
SizeString="$Size 8 18 1"
|
||||
Pred="yehpatt"
|
||||
elif [ $Pred = "local10" ]; then
|
||||
SizeString="$Size 10 18 1"
|
||||
Pred="yehpatt"
|
||||
fi
|
||||
|
||||
Product=1.0
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@ if [ "$1" == "-nightly" ]; then
|
|||
fi
|
||||
done
|
||||
else
|
||||
configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i div_2_1i_rv64gc ) # add fdqh_rv64gc when working
|
||||
configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i ) # add fdqh_rv64gc when working
|
||||
fi
|
||||
|
||||
for config in ${configs[@]}; do
|
||||
|
|
@ -34,12 +34,12 @@ import numpy as np
|
|||
import argparse
|
||||
|
||||
|
||||
RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 10.0060297551637), ('twobitCModel8', 'twobitCModel', 256, 8.4320392215602), ('twobitCModel10', 'twobitCModel', 1024, 7.29493318805151),
|
||||
('twobitCModel12', 'twobitCModel', 4096, 6.84739616147794), ('twobitCModel14', 'twobitCModel', 16384, 5.68432926870082), ('twobitCModel16', 'twobitCModel', 65536, 5.68432926870082),
|
||||
('gshareCModel6', 'gshareCModel', 64, 11.4737703417701), ('gshareCModel8', 'gshareCModel', 256, 8.52341470761974), ('gshareCModel10', 'gshareCModel', 1024, 6.32975690693015),
|
||||
('gshareCModel12', 'gshareCModel', 4096, 4.55424632377659), ('gshareCModel14', 'gshareCModel', 16384, 3.54251547725509), ('gshareCModel16', 'gshareCModel', 65536, 1.90424999467293)]
|
||||
RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 1.51480272475844), ('BTBCModel8', 'BTBCModel', 256, 0.209057900418965), ('BTBCModel10', 'BTBCModel', 1024, 0.0117345454469572),
|
||||
('BTBCModel12', 'BTBCModel', 4096, 0.00125540990359826), ('BTBCModel14', 'BTBCModel', 16384, 0.000732471628510962), ('BTBCModel16', 'BTBCModel', 65536, 0.000732471628510962)]
|
||||
RefDataBP = [('twobitCModel6', 'twobitCModel', 64, 128, 10.0060297551637), ('twobitCModel8', 'twobitCModel', 256, 512, 8.4320392215602), ('twobitCModel10', 'twobitCModel', 1024, 2048, 7.29493318805151),
|
||||
('twobitCModel12', 'twobitCModel', 4096, 8192, 6.84739616147794), ('twobitCModel14', 'twobitCModel', 16384, 32768, 5.68432926870082), ('twobitCModel16', 'twobitCModel', 65536, 131072, 5.68432926870082),
|
||||
('gshareCModel6', 'gshareCModel', 64, 128, 11.4737703417701), ('gshareCModel8', 'gshareCModel', 256, 512, 8.52341470761974), ('gshareCModel10', 'gshareCModel', 1024, 2048, 6.32975690693015),
|
||||
('gshareCModel12', 'gshareCModel', 4096, 8192, 4.55424632377659), ('gshareCModel14', 'gshareCModel', 16384, 32768, 3.54251547725509), ('gshareCModel16', 'gshareCModel', 65536, 131072, 1.90424999467293)]
|
||||
RefDataBTB = [('BTBCModel6', 'BTBCModel', 64, 128, 1.51480272475844), ('BTBCModel8', 'BTBCModel', 256, 512, 0.209057900418965), ('BTBCModel10', 'BTBCModel', 1024, 2048, 0.0117345454469572),
|
||||
('BTBCModel12', 'BTBCModel', 4096, 8192, 0.00125540990359826), ('BTBCModel14', 'BTBCModel', 16384, 32768, 0.000732471628510962), ('BTBCModel16', 'BTBCModel', 65536, 131072, 0.000732471628510962)]
|
||||
|
||||
def ParseBranchListFile(path):
|
||||
'''Take the path to the list of Questa Sim log files containing the performance counters outputs. File
|
||||
|
|
@ -120,25 +120,45 @@ def ComputeGeometricAverage(benchmarks):
|
|||
benchmarks.append(('Mean', '', AllAve))
|
||||
|
||||
def GenerateName(predictorType, predictorParams):
|
||||
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras'):
|
||||
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras' or predictorType == 'global'):
|
||||
return predictorType + predictorParams[0]
|
||||
elif(predictorParams == 'local'):
|
||||
elif(predictorType == 'local'):
|
||||
return predictorType + predictorParams[0] + '_' + predictorParams[1]
|
||||
else:
|
||||
print(f'Error unsupported predictor type {predictorType}')
|
||||
sys.exit(-1)
|
||||
|
||||
def GenerateDisplayName(predictorType, predictorParams):
|
||||
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'ras' or predictorType == 'global'):
|
||||
return predictorType
|
||||
elif(predictorType == 'local'):
|
||||
return predictorType + predictorParams[0]
|
||||
else:
|
||||
print(f'Error unsupported predictor type {predictorType}')
|
||||
sys.exit(-1)
|
||||
|
||||
def ComputePredNumEntries(predictorType, predictorParams):
|
||||
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class'):
|
||||
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'global'):
|
||||
return 2**int(predictorParams[0])
|
||||
elif(predictorType == 'ras'):
|
||||
return int(predictorParams[0])
|
||||
elif(predictorParams == 'local'):
|
||||
elif(predictorType == 'local'):
|
||||
return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2**int(predictorParams[1])
|
||||
else:
|
||||
print(f'Error unsupported predictor type {predictorType}')
|
||||
sys.exit(-1)
|
||||
|
||||
def ComputePredSize(predictorType, predictorParams):
|
||||
if(predictorType == 'gshare' or predictorType == 'twobit' or predictorType == 'btb' or predictorType == 'class' or predictorType == 'global'):
|
||||
return 2*2**int(predictorParams[0])
|
||||
elif(predictorType == 'ras'):
|
||||
return int(predictorParams[0])
|
||||
elif(predictorType == 'local'):
|
||||
return 2**int(predictorParams[0]) * int(predictorParams[1]) + 2*2**int(predictorParams[1])
|
||||
else:
|
||||
print(f'Error unsupported predictor type {predictorType}')
|
||||
sys.exit(-1)
|
||||
|
||||
def BuildDataBase(predictorLogs):
|
||||
# Once done with the following loop, performanceCounterList will contain the predictor type and size along with the
|
||||
# raw performance counter data and the processed data on a per benchmark basis. It also includes the geometric mean.
|
||||
|
|
@ -164,16 +184,16 @@ def BuildDataBase(predictorLogs):
|
|||
ComputeStats(performanceCounters)
|
||||
ComputeGeometricAverage(performanceCounters)
|
||||
#print(performanceCounters)
|
||||
performanceCounterList.append([GenerateName(predictorType, predictorParams), predictorType, performanceCounters, ComputePredNumEntries(predictorType, predictorParams)])
|
||||
performanceCounterList.append([GenerateName(predictorType, predictorParams), GenerateDisplayName(predictorType, predictorParams), performanceCounters, ComputePredNumEntries(predictorType, predictorParams), ComputePredSize(predictorType, predictorParams)])
|
||||
return performanceCounterList
|
||||
|
||||
def ReorderDataBase(performanceCounterList):
|
||||
# Reorder the data so the benchmark name comes first, then the branch predictor configuration
|
||||
benchmarkFirstList = []
|
||||
for (predictorName, predictorPrefixName, benchmarks, entries) in performanceCounterList:
|
||||
for (predictorName, predictorPrefixName, benchmarks, entries, size) in performanceCounterList:
|
||||
for benchmark in benchmarks:
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
benchmarkFirstList.append((nameString, opt, predictorName, predictorPrefixName, entries, dataDict))
|
||||
benchmarkFirstList.append((nameString, opt, predictorName, predictorPrefixName, entries, size, dataDict))
|
||||
return benchmarkFirstList
|
||||
|
||||
def ExtractSelectedData(benchmarkFirstList):
|
||||
|
|
@ -181,7 +201,8 @@ def ExtractSelectedData(benchmarkFirstList):
|
|||
# namestring + opt, config
|
||||
benchmarkDict = { }
|
||||
for benchmark in benchmarkFirstList:
|
||||
(name, opt, config, prefixName, entries, dataDict) = benchmark
|
||||
(name, opt, config, prefixName, entries, size, dataDict) = benchmark
|
||||
#print(f'config = {config}, prefixName = {prefixName} entries = {entries}')
|
||||
# use this code to distinguish speed opt and size opt.
|
||||
#if opt == 'bd_speedopt_speed': NewName = name+'Sp'
|
||||
#elif opt == 'bd_sizeopt_speed': NewName = name+'Sz'
|
||||
|
|
@ -190,18 +211,19 @@ def ExtractSelectedData(benchmarkFirstList):
|
|||
#print(NewName)
|
||||
#NewName = name+'_'+opt
|
||||
if NewName in benchmarkDict:
|
||||
benchmarkDict[NewName].append((config, prefixName, entries, dataDict[ReportPredictorType]))
|
||||
benchmarkDict[NewName].append((config, prefixName, entries, size, dataDict[ReportPredictorType]))
|
||||
else:
|
||||
benchmarkDict[NewName] = [(config, prefixName, entries, dataDict[ReportPredictorType])]
|
||||
benchmarkDict[NewName] = [(config, prefixName, entries, size, dataDict[ReportPredictorType])]
|
||||
return benchmarkDict
|
||||
|
||||
def ReportAsTable(benchmarkDict):
|
||||
refLine = benchmarkDict['Mean']
|
||||
FirstLine = []
|
||||
SecondLine = []
|
||||
for (name, typ, size, val) in refLine:
|
||||
for Elements in refLine:
|
||||
(name, typ, size, entries, val) = Elements
|
||||
FirstLine.append(name)
|
||||
SecondLine.append(size)
|
||||
SecondLine.append(entries if not args.size else size)
|
||||
|
||||
sys.stdout.write('benchmark\t\t')
|
||||
for name in FirstLine:
|
||||
|
|
@ -216,7 +238,7 @@ def ReportAsTable(benchmarkDict):
|
|||
|
||||
if(args.summary):
|
||||
sys.stdout.write('Mean\t\t\t')
|
||||
for (name, typ, size, val) in refLine:
|
||||
for (name, typ, size, entries, val) in refLine:
|
||||
sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 - val))
|
||||
sys.stdout.write('\n')
|
||||
|
||||
|
|
@ -226,7 +248,7 @@ def ReportAsTable(benchmarkDict):
|
|||
if(length < 8): sys.stdout.write('%s\t\t\t' % benchmark)
|
||||
elif(length < 16): sys.stdout.write('%s\t\t' % benchmark)
|
||||
else: sys.stdout.write('%s\t' % benchmark)
|
||||
for (name, typ, size, val) in benchmarkDict[benchmark]:
|
||||
for (name, typ, entries, size, val) in benchmarkDict[benchmark]:
|
||||
sys.stdout.write('%0.2f\t\t' % (val if not args.invert else 100 -val))
|
||||
sys.stdout.write('\n')
|
||||
|
||||
|
|
@ -234,14 +256,14 @@ def ReportAsText(benchmarkDict):
|
|||
if(args.summary):
|
||||
mean = benchmarkDict['Mean']
|
||||
print('Mean')
|
||||
for (name, typ, size, val) in mean:
|
||||
sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
|
||||
for (name, typ, entries. size, val) in mean:
|
||||
sys.stdout.write('%s %s %0.2f\n' % (name, entries if not args.size else size, val if not args.invert else 100 - val))
|
||||
|
||||
if(not args.summary):
|
||||
for benchmark in benchmarkDict:
|
||||
print(benchmark)
|
||||
for (name, type, size, val) in benchmarkDict[benchmark]:
|
||||
sys.stdout.write('%s %s %0.2f\n' % (name, size, val if not args.invert else 100 - val))
|
||||
for (name, type, entries, size, val) in benchmarkDict[benchmark]:
|
||||
sys.stdout.write('%s %s %0.2f\n' % (name, entries if not args.size else size, val if not args.invert else 100 - val))
|
||||
|
||||
def Inversion(lst):
|
||||
return [x if not args.invert else 100 - x for x in lst]
|
||||
|
|
@ -306,11 +328,11 @@ def ReportAsGraph(benchmarkDict, bar, FileName):
|
|||
# branch predictors with various parameterizations
|
||||
# group the parameterizations by the common typ.
|
||||
sequencies = {}
|
||||
for (name, typ, size, value) in benchmarkDict['Mean']:
|
||||
for (name, typ, entries, size, value) in benchmarkDict['Mean']:
|
||||
if not typ in sequencies:
|
||||
sequencies[typ] = [(size, value)]
|
||||
sequencies[typ] = [(entries if not args.size else int(size/8), value)]
|
||||
else:
|
||||
sequencies[typ].append((size,value))
|
||||
sequencies[typ].append((entries if not args.size else int(size/8) ,value))
|
||||
# then graph the common typ as a single line+scatter plot
|
||||
# finally repeat for all typs of branch predictors and overlay
|
||||
fig, axes = plt.subplots()
|
||||
|
|
@ -327,7 +349,8 @@ def ReportAsGraph(benchmarkDict, bar, FileName):
|
|||
axes.legend(loc='upper left')
|
||||
axes.set_xscale("log")
|
||||
axes.set_ylabel('Prediction Accuracy')
|
||||
axes.set_xlabel('Entries')
|
||||
Xlabel = 'Entries' if not args.size else 'Size (bytes)'
|
||||
axes.set_xlabel(Xlabel)
|
||||
axes.set_xticks(xdata)
|
||||
axes.set_xticklabels(xdata)
|
||||
axes.grid(color='b', alpha=0.5, linestyle='dashed', linewidth=0.5)
|
||||
|
|
@ -368,7 +391,7 @@ def ReportAsGraph(benchmarkDict, bar, FileName):
|
|||
for benchmarkName in benchmarkDict:
|
||||
currBenchmark = benchmarkDict[benchmarkName]
|
||||
xlabelList.append(benchmarkName)
|
||||
for (name, typ, size, value) in currBenchmark:
|
||||
for (name, typ, entries, size, value) in currBenchmark:
|
||||
if(name not in seriesDict):
|
||||
seriesDict[name] = [value]
|
||||
else:
|
||||
|
|
@ -381,7 +404,7 @@ def ReportAsGraph(benchmarkDict, bar, FileName):
|
|||
for benchmarkName in benchmarkDict:
|
||||
currBenchmark = benchmarkDict[benchmarkName]
|
||||
xlabelListBig.append(benchmarkName)
|
||||
for (name, typ, size, value) in currBenchmark:
|
||||
for (name, typ, entries, size, value) in currBenchmark:
|
||||
if(name not in seriesDictBig):
|
||||
seriesDictBig[name] = [value]
|
||||
else:
|
||||
|
|
@ -410,6 +433,7 @@ parser.add_argument('-s', '--summary', action='store_const', help='Show only the
|
|||
parser.add_argument('-b', '--bar', action='store_const', help='Plot graphs.', default=False, const=True)
|
||||
parser.add_argument('-g', '--reference', action='store_const', help='Include the golden reference model from branch-predictor-simulator. Data stored statically at the top of %(prog)s. If you need to regenreate use CModelBranchAcurracy.sh', default=False, const=True)
|
||||
parser.add_argument('-i', '--invert', action='store_const', help='Invert metric. Example Branch miss prediction becomes prediction accuracy. 100 - miss rate', default=False, const=True)
|
||||
parser.add_argument('--size', action='store_const', help='Display x-axis as size in bits rather than number of table entries', default=False, const=True)
|
||||
|
||||
displayMode = parser.add_mutually_exclusive_group()
|
||||
displayMode.add_argument('--text', action='store_const', help='Display in text format only.', default=False, const=True)
|
||||
|
|
|
|||
427
bin/regression-wally
Executable file
427
bin/regression-wally
Executable file
|
|
@ -0,0 +1,427 @@
|
|||
#!/usr/bin/python3
|
||||
##################################
|
||||
#
|
||||
# regression-wally
|
||||
# David_Harris@Hmc.edu 25 January 2021
|
||||
# Modified by Jarred Allen <jaallen@g.hmc.edu>
|
||||
#
|
||||
# Run a regression with multiple configurations in parallel and exit with
|
||||
# non-zero status code if an error happened, as well as printing human-readable
|
||||
# output.
|
||||
#
|
||||
##################################
|
||||
import sys,os,shutil
|
||||
import multiprocessing
|
||||
#import os
|
||||
from collections import namedtuple
|
||||
from multiprocessing import Pool, TimeoutError
|
||||
|
||||
##################################
|
||||
# Define lists of configurations and tests to run on each configuration
|
||||
##################################
|
||||
|
||||
# The tests are a list with one element for each configuration
|
||||
# The element consists of the configuration name, a list of test suites to run,
|
||||
# optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success
|
||||
|
||||
INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
|
||||
tests = [
|
||||
["rv32e", ["arch32e"]],
|
||||
["rv32i", ["arch32i"]],
|
||||
["rv32imc", ["arch32i", "arch32c", "arch32m", "wally32periph"]],
|
||||
["rv32gc", ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt",
|
||||
"arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond",
|
||||
"arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma",
|
||||
"arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph",
|
||||
"arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]], # "arch32zcb", "arch32zfad",
|
||||
["rv64i", ["arch64i"]],
|
||||
["buildroot", ["buildroot"], [f"+INSTR_LIMIT={INSTR_LIMIT}"], str(INSTR_LIMIT)+" instructions"]
|
||||
]
|
||||
|
||||
# Separate out floating-point tests for RV64 to speed up coverage
|
||||
tests64gc_nofp = [
|
||||
["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
|
||||
"arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv",
|
||||
"arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
|
||||
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zcb", "arch64zicboz"
|
||||
]
|
||||
|
||||
tests64gc_fp = [
|
||||
["rv64gc", ["arch64f", "arch64d", "arch64zfh",
|
||||
"arch64f_fma", "arch64d_fma", "arch64zfh_fma",
|
||||
"arch64f_divsqrt", "arch64d_divsqrt", "arch64zfh_divsqrt",
|
||||
"arch64zfaf", "arch64zfad"]]
|
||||
]
|
||||
|
||||
derivconfigtests = [
|
||||
# memory system
|
||||
["tlb2_rv32gc", ["wally32priv"]],
|
||||
["tlb16_rv32gc", ["wally32priv"]],
|
||||
["tlb2_rv64gc", ["wally64priv"]],
|
||||
["tlb16_rv64gc", ["wally64priv"]],
|
||||
["way_1_4096_512_rv32gc", ["arch32i"]],
|
||||
["way_2_4096_512_rv32gc", ["arch32i"]],
|
||||
["way_8_4096_512_rv32gc", ["arch32i"]],
|
||||
["way_4_2048_512_rv32gc", ["arch32i"]],
|
||||
["way_4_4096_256_rv32gc", ["arch32i"]],
|
||||
["way_1_4096_512_rv64gc", ["arch64i"]],
|
||||
["way_2_4096_512_rv64gc", ["arch64i"]],
|
||||
["way_8_4096_512_rv64gc", ["arch64i"]],
|
||||
["way_4_2048_512_rv64gc", ["arch64i"]],
|
||||
["way_4_4096_256_rv64gc", ["arch64i"]],
|
||||
["way_4_4096_1024_rv64gc", ["arch64i"]],
|
||||
["ram_0_0_rv64gc", ["ahb64"]],
|
||||
["ram_1_0_rv64gc", ["ahb64"]],
|
||||
["ram_1_1_rv64gc", ["ahb64"]],
|
||||
["ram_2_0_rv64gc", ["ahb64"]],
|
||||
["ram_2_1_rv64gc", ["ahb64"]],
|
||||
# RV32 cacheless designs will not work unless DTIM supports FLEN > XLEN. This support is not planned.
|
||||
# ["nodcache_rv32gc", ["ahb32"]],
|
||||
# ["nocache_rv32gc", ["ahb32"]],
|
||||
["noicache_rv32gc", ["ahb32"]],
|
||||
["noicache_rv64gc", ["ahb64"]],
|
||||
["nodcache_rv64gc", ["ahb64"]],
|
||||
["nocache_rv64gc", ["ahb64"]],
|
||||
|
||||
### add misaligned tests
|
||||
|
||||
# fp/int divider permutations
|
||||
["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
|
||||
# fpu permutations
|
||||
["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
|
||||
["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
|
||||
["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
|
||||
["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32i"]],
|
||||
["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32i"]],
|
||||
["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]],
|
||||
["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]],
|
||||
["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
|
||||
["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i"]],
|
||||
["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "wally64q"]],
|
||||
]
|
||||
|
||||
bpredtests = [
|
||||
["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
|
||||
["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
|
||||
# btb
|
||||
["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
|
||||
# ras
|
||||
["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
|
||||
["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"]
|
||||
]
|
||||
|
||||
##################################
|
||||
# Data Types & Functions
|
||||
##################################
|
||||
|
||||
TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
|
||||
# name: the name of this test configuration (used in printing human-readable
|
||||
# output and picking logfile names)
|
||||
# cmd: the command to run to test (should include the logfile as '{}', and
|
||||
# the command needs to write to that file)
|
||||
# grepstr: the string to grep through the log file for. The test succeeds iff
|
||||
# grep finds that string in the logfile (is used by grep, so it may
|
||||
# be any pattern grep accepts, see `man 1 grep` for more info).
|
||||
|
||||
class bcolors:
|
||||
HEADER = '\033[95m'
|
||||
OKBLUE = '\033[94m'
|
||||
OKCYAN = '\033[96m'
|
||||
OKGREEN = '\033[92m'
|
||||
WARNING = '\033[93m'
|
||||
FAIL = '\033[91m'
|
||||
ENDC = '\033[0m'
|
||||
BOLD = '\033[1m'
|
||||
UNDERLINE = '\033[4m'
|
||||
|
||||
def addTests(tests, sim):
|
||||
for test in tests:
|
||||
config = test[0];
|
||||
suites = test[1];
|
||||
if (len(test) >= 3):
|
||||
args = " --args " + " ".join(test[2])
|
||||
else:
|
||||
args = ""
|
||||
if (len(test) >= 4):
|
||||
gs = test[3]
|
||||
else:
|
||||
gs = "All tests ran without failures"
|
||||
cmdPrefix="wsim --sim " + sim + " " + config
|
||||
for t in suites:
|
||||
tc = TestCase(
|
||||
name=t,
|
||||
variant=config,
|
||||
cmd=cmdPrefix + " " + t + args,
|
||||
grepstr=gs)
|
||||
configs.append(tc)
|
||||
|
||||
def search_log_for_text(text, logfile):
|
||||
"""Search through the given log file for text, returning True if it is found or False if it is not"""
|
||||
grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile)
|
||||
# print(" search_log_for_text invoking %s" % grepcmd)
|
||||
return os.system(grepcmd) == 0
|
||||
|
||||
def run_test_case(config):
|
||||
"""Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
|
||||
logname = WALLY + "/sim/questa/logs/"+config.variant+"_"+config.name+".log" ### *** fix hardwiring to questa log
|
||||
#cmd = config.cmd + " > " + logname
|
||||
if ("lint-wally" in config.cmd):
|
||||
cmd = config.cmd + " | tee " + logname
|
||||
else:
|
||||
cmd = config.cmd + " > " + logname
|
||||
os.chdir(regressionDir)
|
||||
# print(" run_test_case invoking %s" % cmd)
|
||||
os.system(cmd)
|
||||
if search_log_for_text(config.grepstr, logname):
|
||||
print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
|
||||
return 0
|
||||
else:
|
||||
print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name))
|
||||
print(" Check %s" % logname)
|
||||
return 1
|
||||
|
||||
##################################
|
||||
# Main body
|
||||
##################################
|
||||
|
||||
|
||||
WALLY = os.environ.get('WALLY')
|
||||
regressionDir = WALLY + '/sim'
|
||||
os.chdir(regressionDir)
|
||||
|
||||
coveragesim = "questa" # Questa is required for code/functional coverage
|
||||
defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
|
||||
|
||||
coverage = '--coverage' in sys.argv
|
||||
fp = '--fp' in sys.argv
|
||||
nightly = '--nightly' in sys.argv
|
||||
testfloat = '--testfloat' in sys.argv
|
||||
soc = '--soc' in sys.argv
|
||||
|
||||
if (nightly):
|
||||
nightMode = "--nightly";
|
||||
sims = ["questa", "verilator", "vcs"]
|
||||
else:
|
||||
nightMode = "";
|
||||
sims = [defaultsim]
|
||||
|
||||
if (coverage): # only run RV64GC tests in coverage mode
|
||||
coverStr = '--coverage'
|
||||
else:
|
||||
coverStr = ''
|
||||
|
||||
|
||||
# Run Lint
|
||||
configs = [
|
||||
TestCase(
|
||||
name="lints",
|
||||
variant="all",
|
||||
cmd="lint-wally " + nightMode,
|
||||
grepstr="lints run with no errors or warnings"
|
||||
)
|
||||
]
|
||||
|
||||
if (coverage): # only run RV64GC tests on Questa in coverage mode
|
||||
addTests(tests64gc_nofp, "questa")
|
||||
if (fp):
|
||||
addTests(tests64gc_fp, "questa")
|
||||
else:
|
||||
for sim in sims:
|
||||
addTests(tests, sim)
|
||||
addTests(tests64gc_nofp, sim)
|
||||
addTests(tests64gc_fp, sim)
|
||||
# run derivative configurations in nightly regression
|
||||
if (nightly):
|
||||
addTests(derivconfigtests, defaultsim)
|
||||
|
||||
# testfloat tests
|
||||
if (testfloat):
|
||||
configs = []
|
||||
|
||||
testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"]
|
||||
for config in testfloatconfigs:
|
||||
tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"]
|
||||
if ("f_" in config):
|
||||
tests.remove("cvtfp")
|
||||
for test in tests:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant=config,
|
||||
cmd="wsim --tb testbench_fp " + config + " " + test,
|
||||
grepstr="All Tests completed with 0 errors")
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
testfloatdivconfigs = [
|
||||
"fdh_ieee_div_2_1_rv32gc", "fdh_ieee_div_2_1_rv64gc", "fdh_ieee_div_2_2_rv32gc",
|
||||
"fdh_ieee_div_2_2_rv64gc", "fdh_ieee_div_2_4_rv32gc", "fdh_ieee_div_2_4_rv64gc",
|
||||
"fdh_ieee_div_4_1_rv32gc", "fdh_ieee_div_4_1_rv64gc", "fdh_ieee_div_4_2_rv32gc",
|
||||
"fdh_ieee_div_4_2_rv64gc", "fdh_ieee_div_4_4_rv32gc", "fdh_ieee_div_4_4_rv64gc",
|
||||
"fd_ieee_div_2_1_rv32gc", "fd_ieee_div_2_1_rv64gc", "fd_ieee_div_2_2_rv32gc",
|
||||
"fd_ieee_div_2_2_rv64gc", "fd_ieee_div_2_4_rv32gc", "fd_ieee_div_2_4_rv64gc",
|
||||
"fd_ieee_div_4_1_rv32gc", "fd_ieee_div_4_1_rv64gc", "fd_ieee_div_4_2_rv32gc",
|
||||
"fd_ieee_div_4_2_rv64gc", "fd_ieee_div_4_4_rv32gc", "fd_ieee_div_4_4_rv64gc",
|
||||
"fdqh_ieee_div_2_1_rv32gc", "fdqh_ieee_div_2_1_rv64gc", "fdqh_ieee_div_2_2_rv32gc",
|
||||
"fdqh_ieee_div_2_2_rv64gc", "fdqh_ieee_div_2_4_rv32gc", "fdqh_ieee_div_2_4_rv64gc",
|
||||
"fdqh_ieee_div_4_1_rv32gc", "fdqh_ieee_div_4_1_rv64gc", "fdqh_ieee_div_4_2_rv32gc",
|
||||
"fdqh_ieee_div_4_2_rv64gc", "fdqh_ieee_div_4_4_rv32gc", "fdqh_ieee_div_4_4_rv64gc",
|
||||
"fdq_ieee_div_2_1_rv32gc", "fdq_ieee_div_2_1_rv64gc", "fdq_ieee_div_2_2_rv32gc",
|
||||
"fdq_ieee_div_2_2_rv64gc", "fdq_ieee_div_2_4_rv32gc", "fdq_ieee_div_2_4_rv64gc",
|
||||
"fdq_ieee_div_4_1_rv32gc", "fdq_ieee_div_4_1_rv64gc", "fdq_ieee_div_4_2_rv32gc",
|
||||
"fdq_ieee_div_4_2_rv64gc", "fdq_ieee_div_4_4_rv32gc", "fdq_ieee_div_4_4_rv64gc",
|
||||
"fh_ieee_div_2_1_rv32gc", "fh_ieee_div_2_1_rv64gc", "fh_ieee_div_2_2_rv32gc",
|
||||
"fh_ieee_div_2_2_rv64gc", "fh_ieee_div_2_4_rv32gc", "fh_ieee_div_2_4_rv64gc",
|
||||
"fh_ieee_div_4_1_rv32gc", "fh_ieee_div_4_1_rv64gc", "fh_ieee_div_4_2_rv32gc",
|
||||
"fh_ieee_div_4_2_rv64gc", "fh_ieee_div_4_4_rv32gc", "fh_ieee_div_4_4_rv64gc",
|
||||
"f_ieee_div_2_1_rv32gc", "f_ieee_div_2_1_rv64gc", "f_ieee_div_2_2_rv32gc",
|
||||
"f_ieee_div_2_2_rv64gc", "f_ieee_div_2_4_rv32gc", "f_ieee_div_2_4_rv64gc",
|
||||
"f_ieee_div_4_1_rv32gc", "f_ieee_div_4_1_rv64gc", "f_ieee_div_4_2_rv32gc",
|
||||
"f_ieee_div_4_2_rv64gc", "f_ieee_div_4_4_rv32gc", "f_ieee_div_4_4_rv64gc"
|
||||
]
|
||||
for config in testfloatdivconfigs:
|
||||
# div test case
|
||||
tests = ["div", "sqrt"]
|
||||
if ("ieee" in config):
|
||||
tests.append("cvtint")
|
||||
tests.append("cvtfp")
|
||||
if ("f_" in config):
|
||||
tests.remove("cvtfp")
|
||||
for test in tests:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant=config,
|
||||
cmd="wsim --tb testbench_fp --sim questa " + config + " " + test,
|
||||
grepstr="All Tests completed with 0 errors")
|
||||
configs.append(tc)
|
||||
|
||||
if (soc):
|
||||
configs = []
|
||||
addTests(tests64gc_nofp, defaultsim)
|
||||
|
||||
|
||||
def main():
|
||||
"""Run the tests and count the failures"""
|
||||
global configs, coverage
|
||||
os.chdir(regressionDir)
|
||||
for d in ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]:
|
||||
try:
|
||||
os.mkdir(d)
|
||||
except:
|
||||
pass
|
||||
|
||||
if '--makeTests' in sys.argv:
|
||||
os.chdir(regressionDir)
|
||||
os.system('./make-tests.sh | tee ./logs/make-tests.log')
|
||||
|
||||
if '--all' in sys.argv:
|
||||
TIMEOUT_DUR = 30*7200 # seconds
|
||||
#configs.append(getBuildrootTC(boot=True))
|
||||
elif '--buildroot' in sys.argv:
|
||||
TIMEOUT_DUR = 30*7200 # seconds
|
||||
#configs=[getBuildrootTC(boot=True)]
|
||||
elif '--coverage' in sys.argv:
|
||||
TIMEOUT_DUR = 20*60 # seconds
|
||||
# Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
|
||||
# Also it is slow to run.
|
||||
# configs.append(getBuildrootTC(boot=False))
|
||||
os.system('rm -f cov/*.ucdb')
|
||||
elif '--nightly' in sys.argv:
|
||||
TIMEOUT_DUR = 60*1440 # 1 day
|
||||
#configs.append(getBuildrootTC(boot=False))
|
||||
elif '--testfloat' in sys.argv:
|
||||
TIMEOUT_DUR = 60*60 # seconds
|
||||
elif '--soc' in sys.argv:
|
||||
TIMEOUT_DUR = 10*60 # seconds
|
||||
# Don't run buildroot because soc is based on rv64gc
|
||||
else:
|
||||
TIMEOUT_DUR = 10*60 # seconds
|
||||
#configs.append(getBuildrootTC(boot=False))
|
||||
|
||||
# Scale the number of concurrent processes to the number of test cases, but
|
||||
# max out at a limited number of concurrent processes to not overwhelm the system
|
||||
with Pool(processes=min(len(configs),multiprocessing.cpu_count())) as pool:
|
||||
num_fail = 0
|
||||
results = {}
|
||||
for config in configs:
|
||||
results[config] = pool.apply_async(run_test_case,(config,))
|
||||
for (config,result) in results.items():
|
||||
try:
|
||||
num_fail+=result.get(timeout=TIMEOUT_DUR)
|
||||
except TimeoutError:
|
||||
num_fail+=1
|
||||
print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR))
|
||||
|
||||
# Coverage report
|
||||
if coverage:
|
||||
os.system('make coverage')
|
||||
# Count the number of failures
|
||||
if num_fail:
|
||||
print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
|
||||
else:
|
||||
print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}")
|
||||
return num_fail
|
||||
|
||||
if __name__ == '__main__':
|
||||
exit(main())
|
||||
|
|
@ -176,8 +176,8 @@ git clone https://github.com/riscv/sail-riscv.git
|
|||
cd sail-riscv
|
||||
# For now, use checkout that is stable for Wally
|
||||
#git checkout 72b2516d10d472ac77482fd959a9401ce3487f60 # not new enough for Zicboz?
|
||||
make -j ${NUM_THREADS}
|
||||
ARCH=RV32 make -j ${NUM_THREADS}
|
||||
make -j ${NUM_THREADS} c_emulator/riscv_sim_RV64
|
||||
ARCH=RV32 make -j ${NUM_THREADS} c_emulator/riscv_sim_RV32
|
||||
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
|
||||
sudo ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
|
||||
|
||||
|
|
|
|||
70
bin/wsim
Executable file
70
bin/wsim
Executable file
|
|
@ -0,0 +1,70 @@
|
|||
#!/usr/bin/python3
|
||||
#
|
||||
# wsim
|
||||
# David_Harris@hmc.edu 5 April 2024
|
||||
# Invoke a Wally simulation for a desired configuration and test suite or ELF on the specified simulator
|
||||
# usage: wsim CONFIG TESTSUITE [-s/--sim SIMULATOR] [-g/--gui]
|
||||
# example: wsim rv64gc arch64i
|
||||
# example: wsim rv64gc tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ref/ref.elf
|
||||
# example: wsim rv32i arch32i -s verilator
|
||||
# example: wsim fdqh_ieee_rv64gc add -t testbench_fp # run TestFloat
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
import argparse
|
||||
import os
|
||||
|
||||
# Parse arguments
|
||||
parser = argparse.ArgumentParser()
|
||||
parser.add_argument("config", help="Configuration file")
|
||||
parser.add_argument("testsuite", help="Test suite or ELF file")
|
||||
parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa")
|
||||
parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench")
|
||||
parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true")
|
||||
parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true")
|
||||
parser.add_argument("--args", "-a", help="Optional arguments passed to simulator via $value$plusargs", default="")
|
||||
args = parser.parse_args()
|
||||
print("Config=" + args.config + " tests=" + args.testsuite + " sim=" + args.sim + " gui=" + str(args.gui) + " args='" + args.args + "'")
|
||||
|
||||
# Validate arguments
|
||||
if (args.gui):
|
||||
if (args.sim != "questa"):
|
||||
print("GUI option only supported for Questa")
|
||||
exit(1)
|
||||
|
||||
if (args.coverage):
|
||||
if (args.sim != "questa"):
|
||||
print("Coverage option only available for Questa")
|
||||
exit(1)
|
||||
|
||||
|
||||
# create the output sub-directories.
|
||||
WALLY = os.environ.get('WALLY')
|
||||
regressionDir = WALLY + '/sim/'
|
||||
for d in ["logs", "wkdir", "cov"]:
|
||||
try:
|
||||
os.mkdir(regressionDir+args.sim+"/"+d)
|
||||
except:
|
||||
pass
|
||||
|
||||
# Launch selected simulator
|
||||
cd = "cd $WALLY/sim/" +args.sim
|
||||
if (args.sim == "questa"):
|
||||
if (args.tb == "testbench_fp"):
|
||||
args.args = " -GTEST=" + args.testsuite + " " + args.args
|
||||
# cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + " -GTEST=" + args.testsuite + " " + args.args
|
||||
# else:
|
||||
# cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
|
||||
cmd = "do wally.do " + args.config + " " + args.testsuite + " " + args.tb + " " + args.args
|
||||
if (args.coverage):
|
||||
cmd += " -coverage"
|
||||
if (args.gui): # launch Questa with GUI; add +acc to keep variables accessible
|
||||
cmd = cd + "; vsim -do \"" + cmd + " +acc\""
|
||||
else: # launch Questa in batch mode
|
||||
cmd = cd + "; vsim -c -do \"" + cmd + "\""
|
||||
print("Running Questa with command: " + cmd)
|
||||
os.system(cmd)
|
||||
elif (args.sim == "verilator"):
|
||||
print("Running Verilator on %s %s", args.config, args.testsuite)
|
||||
elif (args.sim == "vcs"):
|
||||
print("Running VCS on %s %s", args.config, args.testsuite)
|
||||
|
|
@ -587,6 +587,9 @@ IEEE754 1
|
|||
deriv fd_ieee_rv64gc fd_rv64gc
|
||||
IEEE754 1
|
||||
|
||||
deriv fdh_ieee_rv64gc fdh_rv64gc
|
||||
IEEE754 1
|
||||
|
||||
deriv fdq_ieee_rv64gc fdq_rv64gc
|
||||
IEEE754 1
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,3 @@
|
|||
RISCV := /opt/riscv
|
||||
#BUILDROOT := ${RISCV}/buildroot-test
|
||||
BUILDROOT := buildroot
|
||||
IMAGES := ${BUILDROOT}/output/images
|
||||
|
|
@ -32,6 +31,8 @@ OBJDUMPS := $(foreach name, $(OBJDUMPS), $(DIS)/$(name).objdump)
|
|||
|
||||
all: clean download Image disassemble install
|
||||
|
||||
all_nosudo: clean download Image disassemble install_nosudo
|
||||
|
||||
Image:
|
||||
bash -c "unset LD_LIBRARY_PATH; make -C $(BUILDROOT) --jobs;"
|
||||
$(MAKE) generate
|
||||
|
|
@ -40,6 +41,18 @@ install:
|
|||
sudo rm -rf $(RISCV)/$(BUILDROOT)
|
||||
sudo mv $(BUILDROOT) $(RISCV)/$(BUILDROOT)
|
||||
|
||||
install_nosudo:
|
||||
rm -rf $(RISCV)/$(BUILDROOT)
|
||||
mv $(BUILDROOT) $(RISCV)/$(BUILDROOT)
|
||||
|
||||
dumptvs:
|
||||
sudo mkdir -p $(RISCV)/linux-testvectors
|
||||
cd testvector-generation; sudo ./genInitMem.sh
|
||||
|
||||
dumptvs_nosudo:
|
||||
mkdir -p $(RISCV)/linux-testvectors
|
||||
cd testvector-generation; ./genInitMem.sh
|
||||
|
||||
# Temp rule for debugging
|
||||
test:
|
||||
echo $(shell find $(BUILDROOT)/output/build -maxdepth 2 -type d -regex ".*/linux-[0-9]+\.[0-9]+\.[0-9]+$$")
|
||||
|
|
|
|||
|
|
@ -74,9 +74,9 @@ fi
|
|||
|
||||
# Prefix partition with "p" for non-SCSI disks (mmcblk, nvme)
|
||||
if [[ $SDCARD == "/dev/sd"* ]]; then
|
||||
$PART_PREFIX=""
|
||||
PART_PREFIX=""
|
||||
else
|
||||
$PART_PREFIX="p"
|
||||
PART_PREFIX="p"
|
||||
fi
|
||||
|
||||
# If no images directory, images have not been built
|
||||
|
|
|
|||
6
setup.sh
6
setup.sh
|
|
@ -27,6 +27,10 @@ export PATH=$WALLY/bin:$PATH
|
|||
ulimit -s 100000
|
||||
|
||||
# load site licenses and tool locations
|
||||
source $RISCV/site-setup.sh
|
||||
if [ -f ${RISCV}/site-setup.sh ]; then
|
||||
source ${RISCV}/site-setup.sh
|
||||
else
|
||||
source ${WALLY}/site-setup.sh
|
||||
fi
|
||||
|
||||
echo "setup done"
|
||||
|
|
|
|||
12
sim/bp-results/branch-list-gshare-local8.txt
Normal file
12
sim/bp-results/branch-list-gshare-local8.txt
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
../logs/rv32gc_gshare6.log gshare 6
|
||||
../logs/rv32gc_gshare8.log gshare 8
|
||||
../logs/rv32gc_gshare10.log gshare 10
|
||||
../logs/rv32gc_gshare12.log gshare 12
|
||||
../logs/rv32gc_gshare14.log gshare 14
|
||||
../logs/rv32gc_gshare16.log gshare 16
|
||||
../logs/rv32gc_8local_basic6.log local 8 6
|
||||
../logs/rv32gc_8local_basic8.log local 8 8
|
||||
../logs/rv32gc_8local_basic10.log local 8 10
|
||||
../logs/rv32gc_8local_basic12.log local 8 12
|
||||
../logs/rv32gc_8local_basic14.log local 8 14
|
||||
../logs/rv32gc_8local_basic16.log local 8 16
|
||||
|
|
@ -1,12 +1,36 @@
|
|||
../logs/bpred_GSHARE_6_16_10_0_rv32gc_embench.log gshare 6
|
||||
../logs/bpred_GSHARE_8_16_10_0_rv32gc_embench.log gshare 8
|
||||
../logs/bpred_GSHARE_10_16_10_0_rv32gc_embench.log gshare 10
|
||||
../logs/bpred_GSHARE_12_16_10_0_rv32gc_embench.log gshare 12
|
||||
../logs/bpred_GSHARE_14_16_10_0_rv32gc_embench.log gshare 14
|
||||
../logs/bpred_GSHARE_16_16_10_0_rv32gc_embench.log gshare 16
|
||||
../logs/bpred_TWOBIT_6_16_10_0_rv32gc_embench.log twobit 6
|
||||
../logs/bpred_TWOBIT_8_16_10_0_rv32gc_embench.log twobit 8
|
||||
../logs/bpred_TWOBIT_10_16_10_0_rv32gc_embench.log twobit 10
|
||||
../logs/bpred_TWOBIT_12_16_10_0_rv32gc_embench.log twobit 12
|
||||
../logs/bpred_TWOBIT_14_16_10_0_rv32gc_embench.log twobit 14
|
||||
../logs/bpred_TWOBIT_16_16_10_0_rv32gc_embench.log twobit 16
|
||||
../logs/rv32gc_gshare6.log gshare 6
|
||||
../logs/rv32gc_gshare8.log gshare 8
|
||||
../logs/rv32gc_gshare10.log gshare 10
|
||||
../logs/rv32gc_gshare12.log gshare 12
|
||||
../logs/rv32gc_gshare14.log gshare 14
|
||||
../logs/rv32gc_gshare16.log gshare 16
|
||||
../logs/rv32gc_twobit6.log twobit 6
|
||||
../logs/rv32gc_twobit8.log twobit 8
|
||||
../logs/rv32gc_twobit10.log twobit 10
|
||||
../logs/rv32gc_twobit12.log twobit 12
|
||||
../logs/rv32gc_twobit14.log twobit 14
|
||||
../logs/rv32gc_twobit16.log twobit 16
|
||||
../logs/rv32gc_global6.log global 6
|
||||
../logs/rv32gc_global8.log global 8
|
||||
../logs/rv32gc_global10.log global 10
|
||||
../logs/rv32gc_global12.log global 12
|
||||
../logs/rv32gc_global14.log global 14
|
||||
../logs/rv32gc_global16.log global 16
|
||||
../logs/rv32gc_10local_basic6.log local 10 6
|
||||
../logs/rv32gc_10local_basic8.log local 10 8
|
||||
../logs/rv32gc_10local_basic10.log local 10 10
|
||||
../logs/rv32gc_10local_basic12.log local 10 12
|
||||
../logs/rv32gc_10local_basic14.log local 10 14
|
||||
../logs/rv32gc_10local_basic16.log local 10 16
|
||||
../logs/rv32gc_4local_basic6.log local 4 6
|
||||
../logs/rv32gc_4local_basic8.log local 4 8
|
||||
../logs/rv32gc_4local_basic10.log local 4 10
|
||||
../logs/rv32gc_4local_basic12.log local 4 12
|
||||
../logs/rv32gc_4local_basic14.log local 4 14
|
||||
../logs/rv32gc_4local_basic16.log local 4 16
|
||||
../logs/rv32gc_8local_basic6.log local 8 6
|
||||
../logs/rv32gc_8local_basic8.log local 8 8
|
||||
../logs/rv32gc_8local_basic10.log local 8 10
|
||||
../logs/rv32gc_8local_basic12.log local 8 12
|
||||
../logs/rv32gc_8local_basic14.log local 8 14
|
||||
../logs/rv32gc_8local_basic16.log local 8 16
|
||||
|
|
|
|||
|
|
@ -1,357 +0,0 @@
|
|||
onerror {resume}
|
||||
quietly virtual function -install /testbench/dut/core/lsu -env /testbench/dut/core/lsu/bus { &{/testbench/dut/core/lsu/LSUHTRANS[1], /testbench/dut/core/lsu/LSUHADDR }} test
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /testbench/clk
|
||||
add wave -noupdate /testbench/reset
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/SATP_REGW
|
||||
add wave -noupdate -group Testbench /testbench/reset_ext
|
||||
add wave -noupdate -group Testbench -radix unsigned /testbench/InstrCountW
|
||||
add wave -noupdate -group Testbench -radix unsigned /testbench/AttemptedInstructionCount
|
||||
add wave -noupdate -group Testbench -radix decimal /testbench/interruptInstrCount
|
||||
add wave -noupdate -group Testbench /testbench/interruptCauseVal
|
||||
add wave -noupdate -group Testbench /testbench/interruptEpcVal
|
||||
add wave -noupdate -group Testbench /testbench/interruptTVal
|
||||
add wave -noupdate -group Testbench /testbench/interruptDesc
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/priv/priv/InterruptM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/ExceptionM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/InstrEName
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/textE
|
||||
add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/textM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/PCW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/textW
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCE
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCM
|
||||
add wave -noupdate -group PCS /testbench/PCW
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
|
||||
add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
|
||||
add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
|
||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
|
||||
add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
|
||||
add wave -noupdate -group alu -divider internals
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM
|
||||
add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW
|
||||
add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE
|
||||
add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE
|
||||
add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
|
||||
add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
|
||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/PAdrM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/CacheableM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM[2]}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits[2]}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits[2]}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_D
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_A
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_U
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_X
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_W
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_R
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/PTE_V
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/ImproperPrivilege
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Misaligned
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidRead
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group Status /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/dtlb/InvalidWrite
|
||||
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -group lsu -group dtlb -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESETn
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HREADY
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HRESP
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HADDR
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWDATA
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HWRITE
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HSIZE
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
|
||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
||||
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOIntr
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/SIN
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DSRb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/DCDb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/CTSb
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uncore/uart/uart/RIb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/SOUT
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RTSb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/DTRb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT1b
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/OUT2b
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/INTR
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/TXRDYb
|
||||
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uncore/uart/uart/RXRDYb
|
||||
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
|
||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
|
||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
|
||||
add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM
|
||||
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW
|
||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
|
||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/ExpectedPCW
|
||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/TrapW
|
||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/textW
|
||||
add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
||||
add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
||||
add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
||||
add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]}
|
||||
add wave -noupdate /testbench/dut/core/lsu/test
|
||||
add wave -noupdate {/testbench/dut/core/lsu/LSUHTRANS[1]}
|
||||
add wave -noupdate /testbench/dut/core/lsu/LSUHADDR
|
||||
add wave -noupdate /testbench/dut/core/lsu/LSUHTRANS
|
||||
add wave -noupdate /testbench/dut/core/lsu/HRDATA
|
||||
add wave -noupdate /testbench/dut/core/lsu/LSUHWDATA
|
||||
add wave -noupdate /testbench/dut/core/lsu/LSUHWRITE
|
||||
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/PrivilegeModeW
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{invalid oad data} {15916799 ns} 1} {{original store} {4919493 ns} 1} {{correct load data} {165196425 ns} 0} {{Cursor 4} {165662196 ns} 1} {{Cursor 5} {165196436 ns} 1}
|
||||
quietly wave cursor active 3
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 314
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {165196205 ns} {165196487 ns}
|
||||
2
sim/questa/coverage
Executable file
2
sim/questa/coverage
Executable file
|
|
@ -0,0 +1,2 @@
|
|||
# recompile coverage tests and run coverage including them
|
||||
pushd $WALLY/tests/coverage; make; popd; ./regression-wally -coverage
|
||||
|
|
@ -28,6 +28,10 @@
|
|||
# This file should be a last resort. It's preferable to put
|
||||
# // coverage off
|
||||
# statements inline with the code whenever possible.
|
||||
|
||||
set WALLY $::env(WALLY)
|
||||
set SRC ${WALLY}/src
|
||||
|
||||
# a hack to describe coverage exclusions without hardcoding linenumbers:
|
||||
do GetLineNum.do
|
||||
|
||||
|
|
@ -44,13 +48,13 @@ coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DON
|
|||
# which won't happen while the divider is busy.
|
||||
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state BUSY->IDLE
|
||||
# All Memory-stage stalls have resolved by time fdivsqrt finishes regular operation in this configuration, so can't test StallM
|
||||
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ../src/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item b 1
|
||||
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ../src/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item s 1
|
||||
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item b 1
|
||||
coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -linerange [GetLineNum ${SRC}/fpu/fdivsqrt/fdivsqrtfsm.sv "exclusion-tag: fdivsqrtfsm stallm"] -item s 1
|
||||
# Division by zero never sets sticky/guard/overflow/round to cause inexact or underflow result, but check out of paranoia
|
||||
coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ../src/fpu/postproc/flags.sv "assign FpInexact"] -item e 1 -fecexprrow 15
|
||||
coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ../src/fpu/postproc/flags.sv "assign Underflow"] -item e 1 -fecexprrow 22
|
||||
coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ${SRC}/fpu/postproc/flags.sv "assign FpInexact"] -item e 1 -fecexprrow 15
|
||||
coverage exclude -scope /dut/core/fpu/fpu/postprocess/flags -linerange [GetLineNum ${SRC}/fpu/postproc/flags.sv "assign Underflow"] -item e 1 -fecexprrow 22
|
||||
# Convert int to fp will never underflow
|
||||
coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [GetLineNum ../src/fpu/postproc/cvtshiftcalc.sv "assign CvtResUf"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [GetLineNum ${SRC}/fpu/postproc/cvtshiftcalc.sv "assign CvtResUf"] -item e 1 -fecexprrow 4
|
||||
|
||||
##################
|
||||
# Cache Exclusions
|
||||
|
|
@ -62,89 +66,89 @@ coverage exclude -scope /dut/core/fpu/fpu/postprocess/cvtshiftcalc -linerange [G
|
|||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -fstate CurrState STATE_FLUSH STATE_FLUSH_WRITEBACK STATE_FLUSH_WRITEBACK STATE_WRITEBACK
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_READY STATE_FETCH->STATE_READY
|
||||
# exclude unused transitions from case statement. Unfortunately the whole branch needs to be excluded I think. Expression coverage should still work.
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1
|
||||
# I$ does not flush
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FlushCache"] -item e 1 -fecexprrow 2
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache FlushCache"] -item e 1 -fecexprrow 2
|
||||
# exclude branch/condition coverage: LineDirty if statement
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FETCHStatement"] -item bc 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FLUSHStatement"] -item bs 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache FETCHStatement"] -item bc 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache FLUSHStatement"] -item bs 1
|
||||
# exclude the unreachable logic
|
||||
set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache case"]
|
||||
set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache case"]
|
||||
set start [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-start: icache case"]
|
||||
set end [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-end: icache case"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache WRITEBACKStatement"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache WRITEBACKStatement"]
|
||||
# exclude Atomic Operation logic
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 6
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache storeAMO1"] -item e 1 -fecexprrow 2-4
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache AnyUpdateHit"] -item e 1 -fecexprrow 2
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 6
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache storeAMO1"] -item e 1 -fecexprrow 2-4
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache AnyUpdateHit"] -item e 1 -fecexprrow 2
|
||||
# cache write logic
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheW"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache CacheW"] -item e 1 -fecexprrow 4
|
||||
# output signal logic
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache StallStates"] -item e 1 -fecexprrow 8 12 14
|
||||
set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache flushdirtycontrols"]
|
||||
set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache flushdirtycontrols"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache StallStates"] -item e 1 -fecexprrow 8 12 14
|
||||
set start [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-start: icache flushdirtycontrols"]
|
||||
set end [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag-end: icache flushdirtycontrols"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrTag"] -item e 1 -fecexprrow 8
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache SelAdrTag"] -item e 1 -fecexprrow 8
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12
|
||||
|
||||
# cache.sv AdrSelMuxData and AdrSelMuxTag and CacheBusAdrMux, excluding unhit Flush branch
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxData -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxTag -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheBusAdrMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 3
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxData -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMuxTag -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheBusAdrMux -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1 3
|
||||
# CacheWay Dirty logic. -scope does not accept wildcards.
|
||||
set numcacheways 4
|
||||
for {set i 0} {$i < $numcacheways} {incr i} {
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6
|
||||
# below: flushD can't go high during an icache write b/c of pipeline stall
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
|
||||
# No CMO to clear valid bits of I$
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache ClearValidBits"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache ClearValidWay"] -item e 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "// exclusion-tag: icache ClearValidBits"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "// exclusion-tag: icache ClearValidWay"] -item e 1
|
||||
# No dirty ways in read-only I$
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "// exclusion-tag: icache DirtyWay"] -item e 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "// exclusion-tag: icache DirtyWay"] -item e 1
|
||||
}
|
||||
# I$ buscachefsm does not perform atomics or write/writeback; HREADY is always 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicReadData"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicPhase"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item bs 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item b 2
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item s 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback2"] -item bs 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item bs 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item bs 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADYread"] -item c 1 -feccondrow 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item c 1 -feccondrow 1,2,3,4,6
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item c 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item c 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign HTRANS"] -item c 1 -feccondrow 5
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign BeatCntEn"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheAccess"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign BusStall"] -item e 1 -fecexprrow 10,12,18
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 3
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicReadData"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicPhase"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item bs 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item b 2
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item s 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"]
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback2"] -item bs 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item bs 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item bs 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADYread"] -item c 1 -feccondrow 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"] -item c 1 -feccondrow 1,2,3,4,6
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"] -item c 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"] -item c 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign HTRANS"] -item c 1 -feccondrow 5
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign BeatCntEn"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign CacheAccess"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign BusStall"] -item e 1 -fecexprrow 10,12,18
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 3
|
||||
|
||||
## D$ Exclusions.
|
||||
# InvalidateCache is I$ only:
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item b 2
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item s 1
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: dcache CacheEn"] -item e 1 -fecexprrow 12
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item b 2
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item s 1
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: dcache CacheEn"] -item e 1 -fecexprrow 12
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ${SRC}/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4
|
||||
set numcacheways 4
|
||||
for {set i 0} {$i < $numcacheways} {incr i} {
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4
|
||||
# InvalidateCacheDelay is always 0 for D$ because it is flushed, not invalidated
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache HitWay"] -item 3 1 -fecexprrow 2
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: dcache HitWay"] -item 3 1 -fecexprrow 2
|
||||
|
||||
# FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before
|
||||
# going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW.
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
|
||||
# Not right; other ways can get flushed and dirtied simultaneously coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache UpdateDirty"] -item c 1 -feccondrow 6
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
|
||||
# Not right; other ways can get flushed and dirtied simultaneously coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ${SRC}/cache/cacheway.sv "exclusion-tag: cache UpdateDirty"] -item c 1 -feccondrow 6
|
||||
}
|
||||
# D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY
|
||||
|
|
@ -164,16 +168,16 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/ddr4dec
|
|||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/sdcdec
|
||||
|
||||
# PMA Regions 1, 2, and 3 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-atomic"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-atomic"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-tim"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-tim"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-cachable"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-cachable"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6,8
|
||||
|
||||
|
|
@ -183,7 +187,7 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
|
|||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/spidec
|
||||
|
||||
# The following peripherals are always supported
|
||||
set line [GetLineNum ../src/mmu/adrdec.sv "exclusion-tag: adrdecSel"]
|
||||
set line [GetLineNum ${SRC}/mmu/adrdec.sv "exclusion-tag: adrdecSel"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec -linerange $line-$line -item e 1 -fecexprrow 3,7
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/gpiodec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uartdec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
|
|
@ -191,104 +195,104 @@ coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/plicdec -line
|
|||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/spidec -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
|
||||
#Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0
|
||||
set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
|
||||
set line [GetLineNum ${SRC}/mmu/adrdec.sv "& SizeValid"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5
|
||||
set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
|
||||
set line [GetLineNum ${SRC}/mmu/adrdec.sv "& SizeValid"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5
|
||||
|
||||
# set line [GetLineNum ../src/mmu/adrdec.sv "& Supported"]
|
||||
# set line [GetLineNum ${SRC}/mmu/adrdec.sv "& Supported"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/dtimdec
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/iromdec
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/ddr4dec
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/sdcdec
|
||||
|
||||
# No DTIM or IROM
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/UnCachedDataMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/UnCachedDataMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
|
||||
coverage exclude -scope /dut/core/ifu/bus/icache/UnCachedDataMux -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/UnCachedDataMux -linerange [GetLineNum ${SRC}/generic/mux.sv "exclusion-tag: mux3"] -item b 1
|
||||
|
||||
####################
|
||||
# Unused access types due to sharing IFU and LSU logic
|
||||
####################
|
||||
|
||||
## The lsu never executes instructions so 'ExecuteAccessF' will never be 1
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWXC ="]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "AccessRWXC ="]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "PMAInstrAccessFaultF \\|"]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "PMAInstrAccessFaultF \\|"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
|
||||
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
|
||||
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
|
||||
|
||||
## The IFU has ReadAccess = WriteAccess = 0 and ExecuteAccess = 1 hardwired, so exclude alternatives
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM & PMAAccessFault"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "ReadAccessM & PMAAccessFault"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "PMAStoreAmoAccessFaultM ="]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "PMAStoreAmoAccessFaultM ="]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line
|
||||
set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWXC \\| AtomicAccessM"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "AccessRWXC \\| AtomicAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2-4
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "assign AmoAccessM"]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "assign AmoAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "assign AmoMisalignedCausesAccessFaultM"]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "assign AmoMisalignedCausesAccessFaultM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & WriteAccessM"]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "DataMisalignedM & WriteAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ReadNoAmoAccessM"]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "TLBPageFault & ReadNoAmoAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "StoreAmoPageFaultM \="]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "StoreAmoPageFaultM \="]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
|
||||
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
|
||||
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"]
|
||||
set line [GetLineNum ${SRC}/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "LoadAccessFaultM \="]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "LoadAccessFaultM \="]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "StoreAmoAccessFaultM \="]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "StoreAmoAccessFaultM \="]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
|
||||
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"]
|
||||
set line [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 1,3,4
|
||||
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"]
|
||||
set line [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"]
|
||||
set line [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
|
||||
# IMMU only makes word-sized accesses
|
||||
set line [GetLineNum ../src/mmu/mmu.sv "exclusion-tag: immu-wordaccess"]
|
||||
set line [GetLineNum ${SRC}/mmu/mmu.sv "exclusion-tag: immu-wordaccess"]
|
||||
set line2 [expr $line + 6 ]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e 1 -fecexprrow 4
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1
|
||||
|
||||
# IMMU never disables translations
|
||||
coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign Translate"] -item e 1 -fecexprrow 2
|
||||
coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign UpdateDA"] -item e 1 -fecexprrow 5
|
||||
coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "assign Translate"] -item e 1 -fecexprrow 2
|
||||
coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "assign UpdateDA"] -item e 1 -fecexprrow 5
|
||||
# never reaches this when ENVCFG_ADUE_1 because HPTW updates A bit first
|
||||
coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18
|
||||
coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ${SRC}/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18
|
||||
|
||||
|
||||
|
||||
|
|
@ -298,19 +302,19 @@ coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerang
|
|||
###############
|
||||
|
||||
# RV64GC HPTW never starts at L1_ADR
|
||||
set line [GetLineNum ../src/mmu/hptw.sv "InitialWalkerState == L1_ADR"]
|
||||
set line [GetLineNum ${SRC}/mmu/hptw.sv "InitialWalkerState == L1_ADR"]
|
||||
coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item c 1 -feccondrow 2
|
||||
|
||||
# Never possible to get a page fault when neither reading nor writing
|
||||
set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWLoadPageFault"]
|
||||
set line [GetLineNum ${SRC}/mmu/hptw.sv "assign HPTWLoadPageFault"]
|
||||
coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 7
|
||||
|
||||
# Never possible to get a store page fault from an ITLB walk
|
||||
set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWStoreAmoPageFault"]
|
||||
set line [GetLineNum ${SRC}/mmu/hptw.sv "assign HPTWStoreAmoPageFault"]
|
||||
coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
|
||||
# Never possible to get Access = 0 on a nonleaf PTE with no OtherPageFault (because InvalidRead/Write will be 1 on the nonleaf)
|
||||
set line [GetLineNum ../src/mmu/hptw.sv "assign HPTWUpdateDA"]
|
||||
set line [GetLineNum ${SRC}/mmu/hptw.sv "assign HPTWUpdateDA"]
|
||||
coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item e 1 -fecexprrow 3
|
||||
|
||||
###############
|
||||
|
|
@ -318,78 +322,78 @@ coverage exclude -scope /dut/core/lsu/lsu/hptw/hptw -linerange $line-$line -item
|
|||
###############
|
||||
|
||||
# IMMU PMP does not support CBO instructions
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcbom"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboaccess"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcbom"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"]
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ${SRC}/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboaccess"]
|
||||
|
||||
# No irom
|
||||
set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"]
|
||||
set line [GetLineNum ${SRC}/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"]
|
||||
coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 6
|
||||
set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & CacheableF & ~SelIROM"]
|
||||
set line [GetLineNum ${SRC}/ifu/ifu.sv "~ITLBMissF & CacheableF & ~SelIROM"]
|
||||
coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondrow 4
|
||||
|
||||
# no DTIM
|
||||
set line [GetLineNum ../src/lsu/lsu.sv "assign BusRW"]
|
||||
set line [GetLineNum ${SRC}/lsu/lsu.sv "assign BusRW"]
|
||||
coverage exclude -scope /dut/core/lsu -linerange $line-$line -item c 1 -feccondrow 4
|
||||
set line [GetLineNum ../src/lsu/lsu.sv "assign CacheRWM"]
|
||||
set line [GetLineNum ${SRC}/lsu/lsu.sv "assign CacheRWM"]
|
||||
coverage exclude -scope /dut/core/lsu -linerange $line-$line -item c 1 -feccondrow 4
|
||||
|
||||
# Excluding reset and clear for impossible case in the wficountreg in privdec
|
||||
set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
|
||||
coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
|
||||
#set line [GetLineNum ${SRC}/generic/flop/floprc.sv "reset \\| clear"]
|
||||
#coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
|
||||
|
||||
# Exclude system reset case in ebu
|
||||
set line [GetLineNum ../src/ebu/ebufsmarb.sv "BeatCounter\\("]
|
||||
set line [GetLineNum ${SRC}/ebu/ebufsmarb.sv "BeatCounter\\("]
|
||||
coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
|
||||
set line [GetLineNum ../src/ebu/ebufsmarb.sv "FinalBeatReg\\("]
|
||||
set line [GetLineNum ${SRC}/ebu/ebufsmarb.sv "FinalBeatReg\\("]
|
||||
coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
|
||||
|
||||
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"]
|
||||
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"]
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
|
||||
|
||||
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"]
|
||||
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"]
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
|
||||
|
||||
# The WritebackWriteback and FetchWriteback support back to back pipelined cache writebacks and fetch then
|
||||
# writebacks. The cache never issues these type of requests.
|
||||
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"]
|
||||
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm WritebackWriteback"]
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2
|
||||
|
||||
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"]
|
||||
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWriteback"]
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 2
|
||||
|
||||
# FetchWait never occurs because HREADY is never 0.
|
||||
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWait"]
|
||||
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm FetchWait"]
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item bc 1
|
||||
|
||||
# all of these HREADY exclusions occur because HREADY is always 1. The ram_ahb module never stalls.
|
||||
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY0"]
|
||||
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY0"]
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
|
||||
|
||||
#set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"]
|
||||
#set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY1"]
|
||||
#coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
|
||||
|
||||
#set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"]
|
||||
#set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY2"]
|
||||
#coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
|
||||
|
||||
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY3"]
|
||||
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY3"]
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 4
|
||||
|
||||
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"]
|
||||
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY4"]
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 3
|
||||
|
||||
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY5"]
|
||||
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY5"]
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
|
||||
|
||||
set line [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"]
|
||||
set line [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm HREADY6"]
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 1
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange $line-$line -item c 1 -feccondrow 5
|
||||
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 5
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "assign CacheBusAck"] -item e 1 -fecexprrow 5
|
||||
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ../src/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item s 1
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicElse"] -item s 1
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -linerange [GetLineNum ${SRC}/ebu/buscachefsm.sv "exclusion-tag: buscachefsm AtomicWait"] -item s 1
|
||||
|
||||
# these transitions will not happen
|
||||
coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm -ftrans CurrState DATA_PHASE->ADR_PHASE ATOMIC_READ_DATA_PHASE->ADR_PHASE ATOMIC_PHASE->ADR_PHASE
|
||||
|
|
@ -399,15 +403,15 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefs
|
|||
coverage exclude -srcfile priorityonehot.sv
|
||||
|
||||
# Excluding pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ../src/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
|
||||
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ${SRC}/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
|
||||
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker/pmp/pmpadrdecs[0] -linerange [GetLineNum ${SRC}/mmu/pmpadrdec.sv "exclusion-tag: PAgePMPAdrIn"] -item e 1 -fecexprrow 1
|
||||
|
||||
####################
|
||||
# Privileged
|
||||
####################
|
||||
|
||||
# Instruction Misaligned never asserted because compresssed instructions are accepted
|
||||
coverage exclude -scope /dut/core/priv/priv/trap -linerange [GetLineNum ../src/privileged/trap.sv "assign ExceptionM"] -item e 1 -fecexprrow 2
|
||||
coverage exclude -scope /dut/core/priv/priv/trap -linerange [GetLineNum ${SRC}/privileged/trap.sv "assign ExceptionM"] -item e 1 -fecexprrow 2
|
||||
|
||||
####################
|
||||
# EBU
|
||||
|
|
@ -9,4 +9,6 @@
|
|||
# sqrt - test square root
|
||||
# all - test everything
|
||||
|
||||
vsim -do "do testfloat.do fdqh_ieee_rv64gc $1"
|
||||
|
||||
wsim fdqh_ieee_rv64gc $1 --tb testbench_fp --gui
|
||||
|
||||
|
|
@ -1,3 +1,4 @@
|
|||
# Run TestFloat simulation
|
||||
|
||||
# cvtint - test integer conversion unit (fcvtint)
|
||||
# cvtfp - test floating-point conversion unit (fcvtfp)
|
||||
|
|
@ -10,4 +11,7 @@
|
|||
# sqrt - test square root
|
||||
# all - test everything
|
||||
|
||||
vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1"
|
||||
#vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1"
|
||||
wsim fdqh_ieee_rv64gc $1 --tb testbench_fp
|
||||
#wsim fdqh_ieee_rv64gc $1 --tb testbench_fp --gui
|
||||
|
||||
27
sim/questa/sim-testfloat-verilator
Executable file
27
sim/questa/sim-testfloat-verilator
Executable file
|
|
@ -0,0 +1,27 @@
|
|||
#!/usr/bin/bash
|
||||
|
||||
# sim-testfloat-verilator
|
||||
# David_Harris@hmc.edu 3 April 2024
|
||||
# Run Testfloat simulations with Verilator
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
|
||||
# cvtint - test integer conversion unit (fcvtint)
|
||||
# cvtfp - test floating-point conversion unit (fcvtfp)
|
||||
# cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
|
||||
# add - test addition
|
||||
# fma - test fma
|
||||
# mul - test mult with fma
|
||||
# sub - test subtraction
|
||||
# div - test division
|
||||
# sqrt - test square root
|
||||
# all - test everything
|
||||
|
||||
#vsim -c -do "do testfloat.do fdqh_ieee_rv64gc $1"
|
||||
|
||||
verilator -GTEST="\"all\"" -GTEST_SIZE="\"all\"" --timescale "1ns/1ns" --timing --binary --top-module testbenchfp "-I../config/shared" "-I../config/deriv/fdqh_ieee_rv64gc" ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv --relative-includes
|
||||
|
||||
#vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
|
||||
|
||||
# Change TEST_SIZE to only test certain FP width
|
||||
# values are QP, DP, SP, HP or all for all tests
|
||||
#vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all"
|
||||
2
sim/questa/sim-wally
Executable file
2
sim/questa/sim-wally
Executable file
|
|
@ -0,0 +1,2 @@
|
|||
wsim rv64gc arch64i --gui
|
||||
|
||||
1
sim/questa/sim-wally-batch
Executable file
1
sim/questa/sim-wally-batch
Executable file
|
|
@ -0,0 +1 @@
|
|||
wsim rv64gc arch64i
|
||||
141
sim/questa/wally.do
Normal file
141
sim/questa/wally.do
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
# wally-batch.do
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Usage: do wally-batch.do <config> <testcases> <testbench> [-coverage] [+acc] [any number of +value] [any number of -G VAR=VAL]
|
||||
# Example: do wally-batch.do rv64gc arch64i testbench
|
||||
|
||||
# Use this wally-batch.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-batch.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-batch.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
set CFG ${1}
|
||||
set TESTSUITE ${2}
|
||||
set TESTBENCH ${3}
|
||||
set WKDIR wkdir/${CFG}_${TESTSUITE}
|
||||
set WALLY $::env(WALLY)
|
||||
set CONFIG ${WALLY}/config
|
||||
set SRC ${WALLY}/src
|
||||
set TB ${WALLY}/testbench
|
||||
|
||||
# create library
|
||||
if [file exists ${WKDIR}] {
|
||||
vdel -lib ${WKDIR} -all
|
||||
}
|
||||
vlib ${WKDIR}
|
||||
# Create directory for coverage data
|
||||
mkdir -p cov
|
||||
|
||||
set coverage 0
|
||||
set CoverageVoptArg ""
|
||||
set CoverageVsimArg ""
|
||||
|
||||
# Need to be able to pass arguments to vopt. Unforunately argv does not work because
|
||||
# it takes on different values if vsim and the do file are called from the command line or
|
||||
# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n
|
||||
# variables and compacts into a single list for passing to vopt.
|
||||
set tbArgs ""
|
||||
set from 4
|
||||
set step 1
|
||||
set lst {}
|
||||
set GUI 0
|
||||
set PlusArgs {}
|
||||
set ParamArgs {}
|
||||
set accFlag ""
|
||||
for {set i 0} true {incr i} {
|
||||
set x [expr {$i*$step + $from}]
|
||||
if {$x > $argc} break
|
||||
set arg [expr "$$x"]
|
||||
lappend lst $arg
|
||||
}
|
||||
|
||||
if {$argc >= 3} {
|
||||
if {[lindex $lst [expr { [llength $lst] -1 } ]] eq "+acc"} {
|
||||
set GUI 1
|
||||
set accFlag "+acc"
|
||||
set tbArgs [lrange $lst 0 end-1]
|
||||
} else {
|
||||
set tbArgs $lst
|
||||
}
|
||||
set tbArgsLst [split $lst " "]
|
||||
# separate the +args from the -G parameters
|
||||
foreach otherArg $tbArgsLst {
|
||||
if {[string index $otherArg 0] eq "+"} {
|
||||
lappend PlusArgs $otherArg
|
||||
} else {
|
||||
lappend ParamArgs $otherArg
|
||||
}
|
||||
}
|
||||
#echo "PlusArgs"
|
||||
#echo $PlusArgs
|
||||
#echo "ParamArgs"
|
||||
#echo $ParamArgs
|
||||
#echo "accFlag"
|
||||
#echo $accFlag
|
||||
|
||||
#if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
|
||||
# set coverage 1
|
||||
# set CoverageVoptArg "+cover=sbecf"
|
||||
# set CoverageVsimArg "-coverage"
|
||||
#} elseif {$3 eq "tbArgs"} {
|
||||
# set tbArgs $lst
|
||||
# puts $tbArgs
|
||||
#}
|
||||
}
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
vlog -lint -work ${WKDIR} +incdir+${CONFIG}/$1 +incdir+${CONFIG}/deriv/$1 +incdir+${CONFIG}/shared ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt $accFlag wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} ${tbArgs} -o testbenchopt ${CoverageVoptArg}
|
||||
# *** tbArgs producees a warning that TEST not found in design when running sim-testfloat-batch. Need to separate -G and + arguments to pass separately to vopt and vsim
|
||||
vsim -lib ${WKDIR} testbenchopt +TEST=${TESTSUITE} ${PlusArgs} -fatal 7 -suppress 3829 ${CoverageVsimArg}
|
||||
|
||||
# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
|
||||
# power add generates the logging necessary for said generation.
|
||||
# power add -r /dut/core/*
|
||||
if { ${GUI} } {
|
||||
add log -recursive /*
|
||||
if { ${TESTBENCH} eq "testbench_fp" } {
|
||||
do wave-fpu.do
|
||||
} else {
|
||||
do wave.do
|
||||
}
|
||||
}
|
||||
|
||||
run -all
|
||||
# power off -r /dut/core/*
|
||||
|
||||
|
||||
if {$coverage} {
|
||||
set UCDB cov/${CFG}_${TESTSUITE}.ucdb
|
||||
echo "Saving coverage to ${UCDB}"
|
||||
do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration
|
||||
coverage save -instance /testbench/dut/core ${UCDB}
|
||||
}
|
||||
|
||||
# These aren't doing anything helpful
|
||||
#profile report -calltree -file wally-calltree.rpt -cutoff 2
|
||||
#power report -all -bsaif power.saif
|
||||
|
||||
# terminate simulation unless we need to keep the GUI running
|
||||
if { ${GUI} == 0} {
|
||||
quit
|
||||
}
|
||||
|
||||
30
sim/questa/wave-fpu.do
Normal file
30
sim/questa/wave-fpu.do
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
|
||||
add wave -noupdate /testbench_fp/clk
|
||||
add wave -noupdate -radix decimal /testbench_fp/VectorNum
|
||||
add wave -noupdate /testbench_fp/FrmNum
|
||||
add wave -noupdate /testbench_fp/X
|
||||
add wave -noupdate /testbench_fp/Y
|
||||
add wave -noupdate /testbench_fp/Z
|
||||
add wave -noupdate /testbench_fp/Res
|
||||
add wave -noupdate /testbench_fp/Ans
|
||||
add wave -noupdate /testbench_fp/reset
|
||||
add wave -noupdate /testbench_fp/DivStart
|
||||
add wave -noupdate /testbench_fp/FDivBusyE
|
||||
add wave -noupdate /testbench_fp/CheckNow
|
||||
add wave -noupdate /testbench_fp/DivDone
|
||||
add wave -noupdate /testbench_fp/ResMatch
|
||||
add wave -noupdate /testbench_fp/FlagMatch
|
||||
add wave -noupdate /testbench_fp/CheckNow
|
||||
add wave -noupdate /testbench_fp/NaNGood
|
||||
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/*
|
||||
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/specialcase/*
|
||||
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/flags/*
|
||||
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/normshift/*
|
||||
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/shiftcorrection/*
|
||||
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/resultsign/*
|
||||
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/round/*
|
||||
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/fmashiftcalc/*
|
||||
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/divshiftcalc/*
|
||||
add wave -group {PostProc} -noupdate /testbench_fp/postprocess/cvtshiftcalc/*
|
||||
add wave -group {Testbench} -noupdate /testbench_fp/*
|
||||
add wave -group {Testbench} -noupdate /testbench_fp/readvectors/*
|
||||
|
|
@ -6,43 +6,43 @@ add wave -noupdate /testbench/reset
|
|||
add wave -noupdate /testbench/memfilename
|
||||
add wave -noupdate /testbench/dut/core/SATP_REGW
|
||||
add wave -noupdate /testbench/dut/core/InstrValidM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
|
||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
|
||||
add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallF
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallD
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM
|
||||
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM
|
||||
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM
|
||||
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
|
||||
add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/LoadStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ifu/IFUStallF
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPWrongE
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/ieu/c/MDUStallD
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
|
||||
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/FDivBusyE
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/HPTWInstrAccessFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/pmd/WFITimeoutM
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushM
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushW
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallF
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallD
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -group HDU -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/PendingIntsM
|
||||
add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/InstrValidM
|
||||
add wave -noupdate -group HDU -group interrupts /testbench/dut/core/priv/priv/trap/ValidIntsM
|
||||
add wave -noupdate -group HDU -group interrupts /testbench/dut/core/hzu/WFIInterruptedM
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||
|
|
@ -205,7 +205,6 @@ add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcAE
|
|||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/SrcBE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ALUResultE
|
||||
add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/FunctionName/FunctionName/FunctionName
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrValidM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
|
||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
|
||||
|
|
@ -407,29 +406,29 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dm
|
|||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/SelHPTW
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWStall
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/DTLBWalk
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/hptw/hptw/WalkerState
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextWalkerState
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/HPTWAdr
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/NextPageType
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/PageType
|
||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/hptw/hptw/ValidNonLeafPTE
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/hptw/hptw/DTLBWriteM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/HPTWInstrAccessFault
|
||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group faults /testbench/dut/core/lsu/hptw/hptw/PBMTFaultM
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrW
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
|
||||
add wave -noupdate -group {WriteBack stage} /testbench/dut/core/priv/priv/pmd/wfiW
|
||||
|
|
@ -678,4 +677,4 @@ configure wave -griddelta 40
|
|||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {11566 ns} {11760 ns}
|
||||
WaveRestoreZoom {0 ns} {284634 ns}
|
||||
|
|
@ -1,487 +0,0 @@
|
|||
#!/usr/bin/python3
|
||||
##################################
|
||||
#
|
||||
# regression-wally
|
||||
# David_Harris@Hmc.edu 25 January 2021
|
||||
# Modified by Jarred Allen <jaallen@g.hmc.edu>
|
||||
#
|
||||
# Run a regression with multiple configurations in parallel and exit with
|
||||
# non-zero status code if an error happened, as well as printing human-readable
|
||||
# output.
|
||||
#
|
||||
##################################
|
||||
import sys,os,shutil
|
||||
import multiprocessing
|
||||
|
||||
|
||||
|
||||
class bcolors:
|
||||
HEADER = '\033[95m'
|
||||
OKBLUE = '\033[94m'
|
||||
OKCYAN = '\033[96m'
|
||||
OKGREEN = '\033[92m'
|
||||
WARNING = '\033[93m'
|
||||
FAIL = '\033[91m'
|
||||
ENDC = '\033[0m'
|
||||
BOLD = '\033[1m'
|
||||
UNDERLINE = '\033[4m'
|
||||
|
||||
from collections import namedtuple
|
||||
regressionDir = os.path.dirname(os.path.abspath(__file__))
|
||||
os.chdir(regressionDir)
|
||||
|
||||
coverage = '-coverage' in sys.argv
|
||||
fp = '-fp' in sys.argv
|
||||
nightly = '-nightly' in sys.argv
|
||||
softfloat = '-softfloat' in sys.argv
|
||||
soc = '-soc' in sys.argv
|
||||
|
||||
TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
|
||||
# name: the name of this test configuration (used in printing human-readable
|
||||
# output and picking logfile names)
|
||||
# cmd: the command to run to test (should include the logfile as '{}', and
|
||||
# the command needs to write to that file)
|
||||
# grepstr: the string to grep through the log file for. The test succeeds iff
|
||||
# grep finds that string in the logfile (is used by grep, so it may
|
||||
# be any pattern grep accepts, see `man 1 grep` for more info).
|
||||
|
||||
# edit this list to add more test cases
|
||||
if (nightly):
|
||||
nightMode = "-nightly";
|
||||
configs = []
|
||||
else:
|
||||
nightMode = "";
|
||||
configs = [
|
||||
TestCase(
|
||||
name="lints",
|
||||
variant="all",
|
||||
cmd="./lint-wally " + nightMode + " | tee {}",
|
||||
grepstr="lints run with no errors or warnings"
|
||||
)
|
||||
]
|
||||
|
||||
def getBuildrootTC(boot):
|
||||
INSTR_LIMIT = 1000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
|
||||
MAX_EXPECTED = 246000000 # *** TODO: replace this with a search for the login prompt.
|
||||
if boot:
|
||||
name="buildrootboot"
|
||||
BRcmd="vsim > {} -c <<!\ndo wally.do buildroot buildroot-no-trace $RISCV 0 1 0\n!"
|
||||
BRgrepstr="WallyHostname login:"
|
||||
else:
|
||||
name="buildroot"
|
||||
if (coverage):
|
||||
print( "buildroot coverage")
|
||||
BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0 -coverage\n!"
|
||||
else:
|
||||
print( "buildroot no coverage")
|
||||
BRcmd="vsim > {} -c <<!\ndo wally-batch.do buildroot buildroot configOptions -GINSTR_LIMIT=" +str(INSTR_LIMIT) + " \n!"
|
||||
BRgrepstr=str(INSTR_LIMIT)+" instructions"
|
||||
return TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr)
|
||||
|
||||
tests64gcimperas = ["imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64c"] # unused
|
||||
|
||||
tests64i = ["arch64i"]
|
||||
for test in tests64i:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant="rv64i",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv64i "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused
|
||||
tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt",
|
||||
"arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zicond",
|
||||
"arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma",
|
||||
"arch32zfh_divsqrt", "arch32zfaf", "wally32a", "wally32priv", "wally32periph",
|
||||
"arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"] # "arch32zbc", "arch32zfad",
|
||||
#tests32gc = ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32a", "arch32zifencei", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zicboz", "arch32zcb", "wally32a", "wally32priv", "wally32periph"]
|
||||
for test in tests32gc:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant="rv32gc",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32gc "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
tests32imcimperas = ["imperas32i", "imperas32c"] # unused
|
||||
tests32imc = ["arch32i", "arch32c", "arch32m", "wally32periph"]
|
||||
for test in tests32imc:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant="rv32imc",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32imc "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
tests32i = ["arch32i"]
|
||||
for test in tests32i:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant="rv32i",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32i "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
tests32e = ["arch32e"]
|
||||
for test in tests32e:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant="rv32e",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv32e "+test+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64f_divsqrt", "arch64d_divsqrt", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64zfh", "arch64zfh_divsqrt", "arch64zfh_fma", "arch64zfaf", "arch64zfad", "arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
|
||||
"arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "arch64zicond", "wally64a", "wally64periph", "wally64priv"] # add arch64zfh_fma when available; arch64zicobz, arch64zcb when working
|
||||
#tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs",
|
||||
# "arch64priv", "arch64c", "arch64m", "arch64a", "arch64zifencei", "wally64a", "wally64periph", "wally64priv", "arch64zicboz", "arch64zcb"]
|
||||
if (coverage): # delete all but 64gc tests when running coverage
|
||||
configs = []
|
||||
tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m",
|
||||
"arch64zifencei", "arch64zicond", "arch64a", "wally64a", "wally64periph", "wally64priv",
|
||||
"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] # add when working: "arch64zcb", "arch64zicboz"
|
||||
if (fp):
|
||||
tests64gc.append("arch64f")
|
||||
tests64gc.append("arch64d")
|
||||
tests64gc.append("arch64zfh")
|
||||
tests64gc.append("arch64f_fma")
|
||||
tests64gc.append("arch64d_fma")
|
||||
tests64gc.append("arch64zfh_fma")
|
||||
tests64gc.append("arch64f_divsqrt")
|
||||
tests64gc.append("arch64d_divsqrt")
|
||||
tests64gc.append("arch64zfh_divsqrt")
|
||||
tests64gc.append("arch64zfaf")
|
||||
tests64gc.append("arch64zfad")
|
||||
coverStr = '-coverage'
|
||||
else:
|
||||
coverStr = ''
|
||||
for test in tests64gc:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant="rv64gc",
|
||||
cmd="vsim > {} -c <<!\ndo wally-batch.do rv64gc "+test+" " + coverStr + "\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
# run derivative configurations if requested
|
||||
if (nightly):
|
||||
derivconfigtests = [
|
||||
["tlb2_rv32gc", ["wally32priv"]],
|
||||
["tlb16_rv32gc", ["wally32priv"]],
|
||||
["tlb2_rv64gc", ["wally64priv"]],
|
||||
["tlb16_rv64gc", ["wally64priv"]],
|
||||
["way_1_4096_512_rv32gc", ["arch32i"]],
|
||||
["way_2_4096_512_rv32gc", ["arch32i"]],
|
||||
["way_8_4096_512_rv32gc", ["arch32i"]],
|
||||
["way_4_2048_512_rv32gc", ["arch32i"]],
|
||||
["way_4_4096_256_rv32gc", ["arch32i"]],
|
||||
["way_1_4096_512_rv64gc", ["arch64i"]],
|
||||
["way_2_4096_512_rv64gc", ["arch64i"]],
|
||||
["way_8_4096_512_rv64gc", ["arch64i"]],
|
||||
["way_4_2048_512_rv64gc", ["arch64i"]],
|
||||
["way_4_4096_256_rv64gc", ["arch64i"]],
|
||||
["way_4_4096_1024_rv64gc", ["arch64i"]],
|
||||
|
||||
["ram_0_0_rv64gc", ["ahb64"]],
|
||||
["ram_1_0_rv64gc", ["ahb64"]],
|
||||
["ram_1_1_rv64gc", ["ahb64"]],
|
||||
["ram_2_0_rv64gc", ["ahb64"]],
|
||||
["ram_2_1_rv64gc", ["ahb64"]],
|
||||
|
||||
["noicache_rv32gc", ["ahb32"]],
|
||||
# cacheless designs will not work until DTIM supports FLEN > XLEN
|
||||
# ["nodcache_rv32gc", ["ahb32"]],
|
||||
# ["nocache_rv32gc", ["ahb32"]],
|
||||
["noicache_rv64gc", ["ahb64"]],
|
||||
["nodcache_rv64gc", ["ahb64"]],
|
||||
["nocache_rv64gc", ["ahb64"]],
|
||||
|
||||
### add misaligned tests
|
||||
|
||||
["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
|
||||
["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
|
||||
|
||||
### branch predictor simulation
|
||||
|
||||
# ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
|
||||
# ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
|
||||
# # btb
|
||||
# ["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
|
||||
# # ras
|
||||
# ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
# ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"],
|
||||
|
||||
# enable floating-point tests when lint is fixed
|
||||
["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
|
||||
["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt"]],
|
||||
["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt"]],
|
||||
["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32i"]],
|
||||
["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32i"]],
|
||||
["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma"]],
|
||||
["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt"]], # hanging 1/31/24 dh; try again when lint is fixed
|
||||
["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt"]],
|
||||
["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i"]],
|
||||
["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "wally64q"]],
|
||||
|
||||
|
||||
]
|
||||
for test in derivconfigtests:
|
||||
config = test[0];
|
||||
tests = test[1];
|
||||
if(len(test) >= 4 and test[2] == "configOptions"):
|
||||
configOptions = test[3]
|
||||
cmdPrefix = "vsim > {} -c <<!\ndo wally-batch.do "+config
|
||||
else:
|
||||
configOptions = ""
|
||||
cmdPrefix = "vsim > {} -c <<!\ndo wally-batch.do "+config
|
||||
for t in tests:
|
||||
tc = TestCase(
|
||||
name=t,
|
||||
variant=config,
|
||||
cmd=cmdPrefix+" "+t+" configOptions "+configOptions+"\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
|
||||
|
||||
# softfloat tests
|
||||
if (softfloat):
|
||||
configs = []
|
||||
softfloatconfigs = [
|
||||
"fdh_ieee_div_2_1_rv32gc", "fdh_ieee_div_2_1_rv64gc", "fdh_ieee_div_2_2_rv32gc",
|
||||
"fdh_ieee_div_2_2_rv64gc", "fdh_ieee_div_2_4_rv32gc", "fdh_ieee_div_2_4_rv64gc",
|
||||
"fdh_ieee_div_4_1_rv32gc", "fdh_ieee_div_4_1_rv64gc", "fdh_ieee_div_4_2_rv32gc",
|
||||
"fdh_ieee_div_4_2_rv64gc", "fdh_ieee_div_4_4_rv32gc", "fdh_ieee_div_4_4_rv64gc",
|
||||
"fd_ieee_div_2_1_rv32gc", "fd_ieee_div_2_1_rv64gc", "fd_ieee_div_2_2_rv32gc",
|
||||
"fd_ieee_div_2_2_rv64gc", "fd_ieee_div_2_4_rv32gc", "fd_ieee_div_2_4_rv64gc",
|
||||
"fd_ieee_div_4_1_rv32gc", "fd_ieee_div_4_1_rv64gc", "fd_ieee_div_4_2_rv32gc",
|
||||
"fd_ieee_div_4_2_rv64gc", "fd_ieee_div_4_4_rv32gc", "fd_ieee_div_4_4_rv64gc",
|
||||
"fdqh_ieee_div_2_1_rv32gc", "fdqh_ieee_div_2_1_rv64gc", "fdqh_ieee_div_2_2_rv32gc",
|
||||
"fdqh_ieee_div_2_2_rv64gc", "fdqh_ieee_div_2_4_rv32gc", "fdqh_ieee_div_2_4_rv64gc",
|
||||
"fdqh_ieee_div_4_1_rv32gc", "fdqh_ieee_div_4_1_rv64gc", "fdqh_ieee_div_4_2_rv32gc",
|
||||
"fdqh_ieee_div_4_2_rv64gc", "fdqh_ieee_div_4_4_rv32gc", "fdqh_ieee_div_4_4_rv64gc",
|
||||
"fdq_ieee_div_2_1_rv32gc", "fdq_ieee_div_2_1_rv64gc", "fdq_ieee_div_2_2_rv32gc",
|
||||
"fdq_ieee_div_2_2_rv64gc", "fdq_ieee_div_2_4_rv32gc", "fdq_ieee_div_2_4_rv64gc",
|
||||
"fdq_ieee_div_4_1_rv32gc", "fdq_ieee_div_4_1_rv64gc", "fdq_ieee_div_4_2_rv32gc",
|
||||
"fdq_ieee_div_4_2_rv64gc", "fdq_ieee_div_4_4_rv32gc", "fdq_ieee_div_4_4_rv64gc",
|
||||
"fh_ieee_div_2_1_rv32gc", "fh_ieee_div_2_1_rv64gc", "fh_ieee_div_2_2_rv32gc",
|
||||
"fh_ieee_div_2_2_rv64gc", "fh_ieee_div_2_4_rv32gc", "fh_ieee_div_2_4_rv64gc",
|
||||
"fh_ieee_div_4_1_rv32gc", "fh_ieee_div_4_1_rv64gc", "fh_ieee_div_4_2_rv32gc",
|
||||
"fh_ieee_div_4_2_rv64gc", "fh_ieee_div_4_4_rv32gc", "fh_ieee_div_4_4_rv64gc",
|
||||
"f_ieee_div_2_1_rv32gc", "f_ieee_div_2_1_rv64gc", "f_ieee_div_2_2_rv32gc",
|
||||
"f_ieee_div_2_2_rv64gc", "f_ieee_div_2_4_rv32gc", "f_ieee_div_2_4_rv64gc",
|
||||
"f_ieee_div_4_1_rv32gc", "f_ieee_div_4_1_rv64gc", "f_ieee_div_4_2_rv32gc",
|
||||
"f_ieee_div_4_2_rv64gc", "f_ieee_div_4_4_rv32gc", "f_ieee_div_4_4_rv64gc"
|
||||
]
|
||||
for config in softfloatconfigs:
|
||||
# div test case
|
||||
divtest = TestCase(
|
||||
name="div",
|
||||
variant=config,
|
||||
cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " div \n!",
|
||||
grepstr="All Tests completed with 0 errors"
|
||||
)
|
||||
configs.insert(0,divtest)
|
||||
|
||||
# sqrt test case
|
||||
sqrttest = TestCase(
|
||||
name="sqrt",
|
||||
variant=config,
|
||||
cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " sqrt \n!",
|
||||
grepstr="All Tests completed with 0 errors"
|
||||
)
|
||||
#configs.append(sqrttest)
|
||||
configs.insert(0,sqrttest)
|
||||
|
||||
|
||||
# skip if divider variant config
|
||||
if ("ieee" in config):
|
||||
# cvtint test case
|
||||
cvtinttest = TestCase(
|
||||
name="cvtint",
|
||||
variant=config,
|
||||
cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " cvtint \n!",
|
||||
grepstr="All Tests completed with 0 errors"
|
||||
)
|
||||
configs.append(cvtinttest)
|
||||
|
||||
# cvtfp test case
|
||||
# WILL fail on F_only (refer to spec)
|
||||
cvtfptest = TestCase(
|
||||
name="cvtfp",
|
||||
variant=config,
|
||||
cmd="vsim > {} -c <<!\ndo testfloat-batch.do " + config + " cvtfp \n!",
|
||||
grepstr="All Tests completed with 0 errors"
|
||||
)
|
||||
configs.append(cvtfptest)
|
||||
|
||||
if (soc):
|
||||
print('Running soc coverage')
|
||||
configs = [] # Delete all configs, just use test64gc
|
||||
coverStr = '-coverage' # Include coverage report
|
||||
for test in tests64gc:
|
||||
if any(s in test for s in ['zfa', 'zfh', 'zbk', 'zkn']):
|
||||
continue # Skip tests for extensions that aren't in riscv-arch-tests yet
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
variant="rv64gc",
|
||||
cmd="vsim > {} -c <<!\ndo wally-soc.do rv64gc "+test+" " + coverStr + "\n!",
|
||||
grepstr="All tests ran without failures")
|
||||
configs.append(tc)
|
||||
|
||||
|
||||
import os
|
||||
from multiprocessing import Pool, TimeoutError
|
||||
|
||||
def search_log_for_text(text, logfile):
|
||||
"""Search through the given log file for text, returning True if it is found or False if it is not"""
|
||||
grepcmd = "grep -e '%s' '%s' > /dev/null" % (text, logfile)
|
||||
return os.system(grepcmd) == 0
|
||||
|
||||
def run_test_case(config):
|
||||
"""Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
|
||||
logname = "logs/"+config.variant+"_"+config.name+".log"
|
||||
cmd = config.cmd.format(logname)
|
||||
# print(cmd)
|
||||
os.chdir(regressionDir)
|
||||
os.system(cmd)
|
||||
if search_log_for_text(config.grepstr, logname):
|
||||
print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
|
||||
return 0
|
||||
else:
|
||||
print(f"{bcolors.FAIL}%s_%s: Failures detected in output{bcolors.ENDC}" % (config.variant, config.name))
|
||||
print(" Check %s" % logname)
|
||||
return 1
|
||||
|
||||
def main():
|
||||
"""Run the tests and count the failures"""
|
||||
global configs, coverage
|
||||
try:
|
||||
os.chdir(regressionDir)
|
||||
os.mkdir("logs")
|
||||
except:
|
||||
pass
|
||||
try:
|
||||
shutil.rmtree("wkdir")
|
||||
except:
|
||||
pass
|
||||
finally:
|
||||
os.mkdir("wkdir")
|
||||
|
||||
if '-makeTests' in sys.argv:
|
||||
os.chdir(regressionDir)
|
||||
os.system('./make-tests.sh | tee ./logs/make-tests.log')
|
||||
|
||||
if '-all' in sys.argv:
|
||||
TIMEOUT_DUR = 30*7200 # seconds
|
||||
configs.append(getBuildrootTC(boot=True))
|
||||
elif '-buildroot' in sys.argv:
|
||||
TIMEOUT_DUR = 30*7200 # seconds
|
||||
configs=[getBuildrootTC(boot=True)]
|
||||
elif '-coverage' in sys.argv:
|
||||
TIMEOUT_DUR = 20*60 # seconds
|
||||
# Presently don't run buildroot because it has a different config and can't be merged with the rv64gc coverage.
|
||||
# Also it is slow to run.
|
||||
# configs.append(getBuildrootTC(boot=False))
|
||||
os.system('rm -f cov/*.ucdb')
|
||||
elif '-nightly' in sys.argv:
|
||||
TIMEOUT_DUR = 60*1440 # 1 day
|
||||
configs.append(getBuildrootTC(boot=False))
|
||||
elif '-softfloat' in sys.argv:
|
||||
TIMEOUT_DUR = 60*60 # seconds
|
||||
elif '-soc' in sys.argv:
|
||||
TIMEOUT_DUR = 20*60 # seconds
|
||||
# FIXME: Do we need to run buildroot?
|
||||
else:
|
||||
TIMEOUT_DUR = 10*60 # seconds
|
||||
configs.append(getBuildrootTC(boot=False))
|
||||
|
||||
# Scale the number of concurrent processes to the number of test cases, but
|
||||
# max out at a limited number of concurrent processes to not overwhelm the system
|
||||
with Pool(processes=min(len(configs),multiprocessing.cpu_count())) as pool:
|
||||
num_fail = 0
|
||||
results = {}
|
||||
for config in configs:
|
||||
results[config] = pool.apply_async(run_test_case,(config,))
|
||||
for (config,result) in results.items():
|
||||
try:
|
||||
num_fail+=result.get(timeout=TIMEOUT_DUR)
|
||||
except TimeoutError:
|
||||
num_fail+=1
|
||||
print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR))
|
||||
|
||||
# Coverage report
|
||||
if coverage or soc:
|
||||
os.system('make coverage')
|
||||
# Count the number of failures
|
||||
if num_fail:
|
||||
print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
|
||||
else:
|
||||
print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}")
|
||||
return num_fail
|
||||
|
||||
if __name__ == '__main__':
|
||||
exit(main())
|
||||
|
|
@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100"
|
|||
#export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
|
||||
#export OTHERFLAGS=""
|
||||
|
||||
vsim -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0"
|
||||
vsim -c -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0"
|
||||
|
|
|
|||
|
|
@ -1,33 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
# Defaults
|
||||
INSTR_LIMIT=0
|
||||
INSTR_WAVEON=1
|
||||
CHECKPOINT=0
|
||||
|
||||
# Arg Parsing
|
||||
for i in "$@"; do
|
||||
case $i in
|
||||
--INSTR_LIMIT=*)
|
||||
INSTR_LIMIT="${i#*=}"
|
||||
shift # past argument=value
|
||||
;;
|
||||
--INSTR_WAVEON=*)
|
||||
INSTR_WAVEON="${i#*=}"
|
||||
shift # past argument=value
|
||||
;;
|
||||
--CHECKPOINT=*)
|
||||
CHECKPOINT="${i#*=}"
|
||||
shift # past argument=value
|
||||
;;
|
||||
*)
|
||||
# unknown option
|
||||
;;
|
||||
esac
|
||||
done
|
||||
|
||||
echo "INSTR_LIMIT = ${INSTR_LIMIT}"
|
||||
echo "INSTR_WAVEON = ${INSTR_WAVEON}"
|
||||
echo "CHECKPOINT = ${CHECKPOINT}"
|
||||
|
||||
vsim -do "do ./wally.do buildroot buildroot $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT"
|
||||
|
|
@ -1,36 +0,0 @@
|
|||
#!/bin/bash
|
||||
|
||||
# Defaults
|
||||
INSTR_LIMIT=0
|
||||
INSTR_WAVEON=1
|
||||
CHECKPOINT=0
|
||||
|
||||
# Arg Parsing
|
||||
for i in "$@"; do
|
||||
case $i in
|
||||
--INSTR_LIMIT=*)
|
||||
INSTR_LIMIT="${i#*=}"
|
||||
shift # past argument=value
|
||||
;;
|
||||
--INSTR_WAVEON=*)
|
||||
INSTR_WAVEON="${i#*=}"
|
||||
shift # past argument=value
|
||||
;;
|
||||
--CHECKPOINT=*)
|
||||
CHECKPOINT="${i#*=}"
|
||||
shift # past argument=value
|
||||
;;
|
||||
*)
|
||||
# unknown option
|
||||
;;
|
||||
esac
|
||||
done
|
||||
|
||||
echo "INSTR_LIMIT = ${INSTR_LIMIT}"
|
||||
echo "INSTR_WAVEON = ${INSTR_WAVEON}"
|
||||
echo "CHECKPOINT = ${CHECKPOINT}"
|
||||
|
||||
# *** change config from buildroot to rv64gc
|
||||
vsim -c <<!
|
||||
do wally-batch.do buildroot buildroot-no-trace $RISCV $INSTR_LIMIT $INSTR_WAVEON $CHECKPOINT
|
||||
!
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
vsim -do "do wally.do rv64gc wally64periph"
|
||||
|
||||
|
|
@ -1 +0,0 @@
|
|||
vsim -c -do "do wally-batch.do rv64gc wally64periph"
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
# testfloat-batch.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021; Kevin Kim 2024
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# run with vsim -do "do wally.do rv64ic riscvarchtest-64m"
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
|
||||
if [file exists wkdir/work_${1}_${2}] {
|
||||
vdel -lib wkdir/work_${1}_${2} -all
|
||||
}
|
||||
vlib wkdir/work_${1}_${2}
|
||||
|
||||
|
||||
|
||||
# c# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
# $num = the added words after the call
|
||||
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697,7033
|
||||
|
||||
|
||||
# Set WAV variable to avoid having any output to wave (to limit disk space)
|
||||
quietly set WAV 0;
|
||||
|
||||
# Determine if nowave argument is provided this removes any output to
|
||||
# a wlf or wave window to reduce disk space.
|
||||
if {$WAV eq 0} {
|
||||
puts "No wave output is selected"
|
||||
} else {
|
||||
puts "wave output is selected"
|
||||
view wave
|
||||
add log -recursive /*
|
||||
do wave-fpu.do
|
||||
}
|
||||
|
||||
# Change TEST_SIZE to only test certain FP width
|
||||
# values are QP, DP, SP, HP or all for all tests
|
||||
|
||||
vopt +acc wkdir/work_${1}_${2}.testbenchfp -work wkdir/work_${1}_${2} -G TEST=$2 -G TEST_SIZE="all" -o testbenchopt
|
||||
vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
|
||||
#-- Run the Simulation
|
||||
run -all
|
||||
|
|
@ -1,52 +0,0 @@
|
|||
# testfloat.do
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# run with vsim -do "do wally.do rv64ic riscvarchtest-64m"
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
# $num = the added words after the call
|
||||
vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697
|
||||
|
||||
# Change TEST_SIZE to only test certain FP width
|
||||
# values are QP, DP, SP, HP or all for all tests
|
||||
vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all"
|
||||
|
||||
# Set WAV variable to avoid having any output to wave (to limit disk space)
|
||||
quietly set WAV 1;
|
||||
|
||||
# Determine if nowave argument is provided this removes any output to
|
||||
# a wlf or wave window to reduce disk space.
|
||||
if {$WAV eq 0} {
|
||||
puts "No wave output is selected"
|
||||
} else {
|
||||
puts "wave output is selected"
|
||||
view wave
|
||||
add log -recursive /*
|
||||
do wave-fpu.do
|
||||
}
|
||||
|
||||
#-- Run the Simulation
|
||||
run -all
|
||||
noview testbench-fp.sv
|
||||
view wave
|
||||
|
||||
25
sim/vcs/run_vcs.sh
Executable file
25
sim/vcs/run_vcs.sh
Executable file
|
|
@ -0,0 +1,25 @@
|
|||
#!/bin/bash
|
||||
|
||||
|
||||
# Set CONFIG_VARIANT from the first script argument
|
||||
#CONFIG_VARIANT=${1:-rv64i}
|
||||
CONFIG_VARIANT=${1}
|
||||
# Set TESTSUITE from the second script argument
|
||||
TESTSUITE=$2
|
||||
INCLUDE_DIRS=$(find ../src -type d | xargs -I {} echo -n "{} ")
|
||||
SOURCE_PATH="+incdir+../config/${CONFIG_VARIANT} +incdir+../config/deriv/${CONFIG_VARIANT} +incdir+../config/shared +define+ +define+P.XLEN=64 +define+FPGA=0 +incdir+../testbench ../src/cvw.sv +incdir+../src"
|
||||
|
||||
SIMFILES="$INCLUDE_DIRS $(find ../src -name "*.sv" ! -path "../src/generic/clockgater.sv" ! -path "../src/generic/mem/rom1p1r_128x64.sv" ! -path "../src/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "../src/generic/mem/rom1p1r_128x32.sv" ! -path "../src/generic/mem/ram2p1r1wbe_512x64.sv") ../testbench/testbench.sv $(find ../testbench/common -name "*.sv" ! -path "../testbench/common/wallyTracer.sv")"
|
||||
OUTPUT="sim_out"
|
||||
|
||||
clean() {
|
||||
rm -rf obj_dir work transcript vsim.wlf $OUTPUT *.vcd csrc ucli.key vc_hdrs.h program.out
|
||||
rm -rf simv* *.daidir dve *.vpd *.dump DVEfiles/ verdi* novas* *fsdb* *.vg *.rep *.db *.chk *.log *.out profileReport* simprofile_dir*
|
||||
}
|
||||
|
||||
# Clean and run simulation with VCS
|
||||
clean
|
||||
#vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} +define+TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
|
||||
vcs +lint=all,noGCWM -simprofile -sverilog +vc -Mupdate -line -full64 -kdb -lca -debug_access+all+reverse -v2k_generate ${SOURCE_PATH} -pvalue+testbench.TEST=$TESTSUITE $SIMFILES -o $OUTPUT -error=NOODV
|
||||
./$OUTPUT | tee program.out
|
||||
|
||||
|
|
@ -1,92 +0,0 @@
|
|||
# wally-batch.do
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# Usage: do wally-batch.do <config> <testcases>
|
||||
# Example: do wally-batch.do rv32imc imperas-32i
|
||||
|
||||
# Use this wally-batch.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally-batch.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally-batch.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists wkdir/work_${1}_${2}] {
|
||||
vdel -lib wkdir/work_${1}_${2} -all
|
||||
}
|
||||
vlib wkdir/work_${1}_${2}
|
||||
# Create directory for coverage data
|
||||
mkdir -p cov
|
||||
|
||||
set coverage 0
|
||||
set CoverageVoptArg ""
|
||||
set CoverageVsimArg ""
|
||||
|
||||
# Need to be able to pass arguments to vopt. Unforunately argv does not work because
|
||||
# it takes on different values if vsim and the do file are called from the command line or
|
||||
# if the do file isd called from questa sim directly. This chunk of code uses the $4 through $n
|
||||
# variables and compacts into a single list for passing to vopt.
|
||||
set configOptions ""
|
||||
set from 4
|
||||
set step 1
|
||||
set lst {}
|
||||
for {set i 0} true {incr i} {
|
||||
set x [expr {$i*$step + $from}]
|
||||
if {$x > $argc} break
|
||||
set arg [expr "$$x"]
|
||||
lappend lst $arg
|
||||
}
|
||||
|
||||
if {$argc >= 3} {
|
||||
if {$3 eq "-coverage" || ($argc >= 7 && $7 eq "-coverage")} {
|
||||
set coverage 1
|
||||
set CoverageVoptArg "+cover=sbecf"
|
||||
set CoverageVsimArg "-coverage"
|
||||
} elseif {$3 eq "configOptions"} {
|
||||
set configOptions $lst
|
||||
puts $configOptions
|
||||
}
|
||||
}
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# default to config/rv64ic, but allow this to be overridden at the command line. For example:
|
||||
# do wally-pipelined-batch.do ../config/rv32imc rv32imc
|
||||
|
||||
vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg}
|
||||
vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 ${CoverageVsimArg}
|
||||
|
||||
# vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829
|
||||
# power add generates the logging necessary for said generation.
|
||||
# power add -r /dut/core/*
|
||||
run -all
|
||||
# power off -r /dut/core/*
|
||||
|
||||
|
||||
if {$coverage} {
|
||||
echo "Saving coverage to ${1}_${2}.ucdb"
|
||||
do coverage-exclusions-rv64gc.do # beware: this assumes testing the rv64gc configuration
|
||||
coverage save -instance /testbench/dut/core cov/${1}_${2}.ucdb
|
||||
}
|
||||
|
||||
# These aren't doing anything helpful
|
||||
#profile report -calltree -file wally-calltree.rpt -cutoff 2
|
||||
#power report -all -bsaif power.saif
|
||||
quit
|
||||
120
sim/wally.do
120
sim/wally.do
|
|
@ -1,120 +0,0 @@
|
|||
# wally.do
|
||||
# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
#
|
||||
# Modification by Oklahoma State University & Harvey Mudd College
|
||||
# Use with Testbench
|
||||
# James Stine, 2008; David Harris 2021
|
||||
# Go Cowboys!!!!!!
|
||||
#
|
||||
# Takes 1:10 to run RV64IC tests using gui
|
||||
|
||||
# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
|
||||
|
||||
# Use this wally-pipelined.do file to run this example.
|
||||
# Either bring up ModelSim and type the following at the "ModelSim>" prompt:
|
||||
# do wally.do
|
||||
# or, to run from a shell, type the following at the shell prompt:
|
||||
# vsim -do wally.do -c
|
||||
# (omit the "-c" to see the GUI while running from the shell)
|
||||
|
||||
onbreak {resume}
|
||||
|
||||
# create library
|
||||
if [file exists work] {
|
||||
vdel -all
|
||||
}
|
||||
vlib work
|
||||
|
||||
# compile source files
|
||||
# suppress spurious warnngs about
|
||||
# "Extra checking for conflicts with always_comb done at vopt time"
|
||||
# because vsim will run vopt
|
||||
|
||||
# start and run simulation
|
||||
# remove +acc flag for faster sim during regressions if there is no need to access internal signals
|
||||
if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G CHECKPOINT=$6 -G NO_SPOOFING=0 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
|
||||
|
||||
#-- Run the Simulation
|
||||
#run -all
|
||||
add log -recursive /*
|
||||
do linux-wave.do
|
||||
run -all
|
||||
|
||||
exec ./slack-notifier/slack-notifier.py
|
||||
|
||||
} elseif {$2 eq "buildroot-no-trace"} {
|
||||
vlog -lint -work work_${1}_${2} +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=0 -G INSTR_WAVEON=0 -G CHECKPOINT=0 -G NO_SPOOFING=1 -o testbenchopt
|
||||
vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286 -fatal 7
|
||||
|
||||
#-- Run the Simulation
|
||||
echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
|
||||
echo "Don't forget to change DEBUG_LEVEL = 0."
|
||||
echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
|
||||
#run 100 ns
|
||||
#force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
|
||||
#force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
|
||||
run 14000 ms
|
||||
#add log -recursive /*
|
||||
#do linux-wave.do
|
||||
#run -all
|
||||
|
||||
exec ./slack-notifier/slack-notifier.py
|
||||
|
||||
} elseif {$2 eq "fpga"} {
|
||||
echo "hello"
|
||||
vlog -work work +incdir+../config/fpga +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/sdc/*.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv ../../fpga/sim/*.sv -suppress 8852,12070,3084,3829,2583,7063,13286
|
||||
vopt +acc work.testbench -G TEST=$2 -G DEBUG=0 -o workopt
|
||||
vsim workopt +nowarn3829 -fatal 7
|
||||
|
||||
do fpga-wave.do
|
||||
add log -r /*
|
||||
run 20 ms
|
||||
|
||||
} else {
|
||||
vlog +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583,13286 -suppress 7063
|
||||
vopt +acc work.testbench -G TEST=$2 -G DEBUG=1 -o workopt
|
||||
|
||||
vsim workopt +nowarn3829 -fatal 7
|
||||
|
||||
view wave
|
||||
#-- display input and output signals as hexidecimal values
|
||||
#do ./wave-dos/peripheral-waves.do
|
||||
add log -recursive /*
|
||||
do wave.do
|
||||
#do wave-bus.do
|
||||
|
||||
# power add generates the logging necessary for saif generation.
|
||||
#power add -r /dut/core/*
|
||||
#-- Run the Simulation
|
||||
|
||||
run -all
|
||||
#power off -r /dut/core/*
|
||||
#power report -all -bsaif power.saif
|
||||
noview ../testbench/testbench.sv
|
||||
view wave
|
||||
}
|
||||
|
||||
|
||||
|
||||
#elseif {$2 eq "buildroot-no-trace""} {
|
||||
# vlog -lint -work work_${1}_${2} +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
|
||||
# start and run simulation
|
||||
# vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=470350800 -G INSTR_WAVEON=470350800 -G CHECKPOINT=470350800 -G DEBUG_TRACE=0 -o testbenchopt
|
||||
# vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829
|
||||
|
||||
#-- Run the Simulation
|
||||
# run 100 ns
|
||||
# force -deposit testbench/dut/core/priv/priv/csr/csri/IE_REGW 16'h2aa
|
||||
# force -deposit testbench/dut/uncore/uncore/clint/clint/MTIMECMP 64'h1000
|
||||
# add log -recursive /*
|
||||
# do linux-wave.do
|
||||
# run -all
|
||||
|
||||
# exec ./slack-notifier/slack-notifier.py
|
||||
#}
|
||||
1606
sim/wave-all.do
1606
sim/wave-all.do
File diff suppressed because it is too large
Load diff
|
|
@ -1,100 +0,0 @@
|
|||
restart -f
|
||||
delete wave /*
|
||||
view wave
|
||||
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
|
||||
# new
|
||||
#add wave /testbench/dut/core/ebu/ebu/IReadF
|
||||
add wave /testbench/dut/core/DataStall
|
||||
add wave /testbench/dut/core/ICacheStallF
|
||||
add wave /testbench/dut/core/StallF
|
||||
add wave /testbench/dut/core/StallD
|
||||
|
||||
add wave /testbench/dut/core/StallE
|
||||
add wave /testbench/dut/core/StallM
|
||||
add wave /testbench/dut/core/StallW
|
||||
add wave /testbench/dut/core/FlushD
|
||||
add wave /testbench/dut/core/FlushE
|
||||
add wave /testbench/dut/core/FlushM
|
||||
add wave /testbench/dut/core/FlushW
|
||||
|
||||
add wave -noupdate -divider -height 32 "MulDiv"
|
||||
add wave -hex /testbench/dut/core/mdu/*
|
||||
|
||||
add wave -noupdate -divider -height 32 "Integer Divider"
|
||||
add wave -hex /testbench/dut/core/mdu/genblk1/div/fsm1/CURRENT_STATE
|
||||
add wave -hex /testbench/dut/core/mdu/genblk1/div/fsm1/NEXT_STATE
|
||||
add wave -hex /testbench/dut/core/mdu/genblk1/div/*
|
||||
|
||||
add wave -noupdate -divider -height 32 "RF"
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/*
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf
|
||||
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/core/ifu/PCF
|
||||
add wave -hex /testbench/dut/core/ifu/PCD
|
||||
add wave -hex /testbench/dut/core/ifu/InstrD
|
||||
add wave /testbench/InstrDName
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ifu/PCE
|
||||
add wave -hex /testbench/dut/core/ifu/InstrE
|
||||
add wave /testbench/InstrEName
|
||||
add wave -hex /testbench/dut/core/ieu/dp/SrcAE
|
||||
add wave -hex /testbench/dut/core/ieu/dp/SrcBE
|
||||
add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
|
||||
#add wave /testbench/dut/core/ieu/dp/PCSrcE
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ifu/PCM
|
||||
add wave -hex /testbench/dut/core/ifu/InstrM
|
||||
add wave /testbench/InstrMName
|
||||
add wave /testbench/dut/uncore/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/uncore/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/uncore/HWDATA
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/BusState
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/NextBusState
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HADDR
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HREADY
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HTRANS
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HRDATA
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HWRITE
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HBURST
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/uncore/uncore/ram/*
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ifu/PCW
|
||||
add wave -hex /testbench/dut/core/ifu/InstrW
|
||||
add wave /testbench/InstrWName
|
||||
add wave /testbench/dut/core/ieu/dp/RegWriteW
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/RdW
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/uncore/uncore/ram/*
|
||||
add wave -divider
|
||||
|
||||
# appearance
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {100 ps}
|
||||
configure wave -namecolwidth 350
|
||||
configure wave -valuecolwidth 250
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
|
|
@ -1,89 +0,0 @@
|
|||
# ahb-waves.do
|
||||
restart -f
|
||||
delete wave /*
|
||||
view wave
|
||||
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
|
||||
#add wave /testbench/dut/core/ebu/ebu/IReadF
|
||||
add wave /testbench/dut/core/DataStall
|
||||
add wave /testbench/dut/core/ICacheStallF
|
||||
add wave /testbench/dut/core/StallF
|
||||
add wave /testbench/dut/core/StallD
|
||||
add wave /testbench/dut/core/StallE
|
||||
add wave /testbench/dut/core/StallM
|
||||
add wave /testbench/dut/core/StallW
|
||||
add wave /testbench/dut/core/FlushD
|
||||
add wave /testbench/dut/core/FlushE
|
||||
add wave /testbench/dut/core/FlushM
|
||||
add wave /testbench/dut/core/FlushW
|
||||
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/core/ifu/PCF
|
||||
add wave -hex /testbench/dut/core/ifu/PCD
|
||||
add wave -hex /testbench/dut/core/ifu/InstrD
|
||||
add wave /testbench/InstrDName
|
||||
add wave -hex /testbench/dut/core/ifu/ic/InstrRawD
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ifu/PCE
|
||||
add wave -hex /testbench/dut/core/ifu/InstrE
|
||||
add wave /testbench/InstrEName
|
||||
add wave -hex /testbench/dut/core/ieu/dp/SrcAE
|
||||
add wave -hex /testbench/dut/core/ieu/dp/SrcBE
|
||||
add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
|
||||
#add wave /testbench/dut/core/ieu/dp/PCSrcE
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ifu/PCM
|
||||
add wave -hex /testbench/dut/core/ifu/InstrM
|
||||
add wave /testbench/InstrMName
|
||||
add wave /testbench/dut/uncore/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/uncore/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/uncore/HWDATA
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/BusState
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/NextBusState
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HADDR
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HREADY
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HTRANS
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HRDATA
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HWRITE
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/CaptureDataM
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/uncore/uncore/ram/*
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ifu/PCW
|
||||
add wave -hex /testbench/dut/core/ifu/InstrW
|
||||
add wave /testbench/InstrWName
|
||||
add wave /testbench/dut/core/ieu/dp/RegWriteW
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/RdW
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/uncore/uncore/ram/*
|
||||
add wave -divider
|
||||
|
||||
add wave -hex -r /testbench/*
|
||||
|
||||
# appearance
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {100 ps}
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 150
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
|
|
@ -1,76 +0,0 @@
|
|||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
|
||||
#add wave /testbench/dut/core/ebu/ebu/IReadF
|
||||
add wave /testbench/dut/core/DataStall
|
||||
add wave /testbench/dut/core/ICacheStallF
|
||||
add wave /testbench/dut/core/StallF
|
||||
add wave /testbench/dut/core/StallD
|
||||
add wave /testbench/dut/core/StallE
|
||||
add wave /testbench/dut/core/StallM
|
||||
add wave /testbench/dut/core/StallW
|
||||
add wave /testbench/dut/core/FlushD
|
||||
add wave /testbench/dut/core/FlushE
|
||||
add wave /testbench/dut/core/FlushM
|
||||
add wave /testbench/dut/core/FlushW
|
||||
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/core/ifu/PCF
|
||||
add wave -hex /testbench/dut/core/ifu/PCD
|
||||
add wave -hex /testbench/dut/core/ifu/InstrD
|
||||
|
||||
add wave /testbench/InstrDName
|
||||
add wave -divider
|
||||
|
||||
|
||||
add wave -hex /testbench/dut/core/ifu/PCE
|
||||
add wave -hex /testbench/dut/core/ifu/InstrE
|
||||
add wave /testbench/InstrEName
|
||||
add wave -hex /testbench/dut/core/ieu/dp/SrcAE
|
||||
add wave -hex /testbench/dut/core/ieu/dp/SrcBE
|
||||
add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
|
||||
#add wave /testbench/dut/core/ieu/dp/PCSrcE
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ifu/PCM
|
||||
add wave -hex /testbench/dut/core/ifu/InstrM
|
||||
add wave /testbench/InstrMName
|
||||
add wave /testbench/dut/uncore/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/uncore/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/uncore/HWDATA
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/MemReadM
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/InstrReadF
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/BusState
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/NextBusState
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HADDR
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HREADY
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HTRANS
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HRDATA
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HWRITE
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/HWDATA
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/ReadDataM
|
||||
add wave -divider
|
||||
|
||||
add wave /testbench/dut/core/ebu/ebu/CaptureDataM
|
||||
add wave /testbench/dut/core/ebu/ebu/CapturedDataAvailable
|
||||
add wave /testbench/dut/core/StallW
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/CapturedData
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/ReadDataWnext
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
|
||||
add wave -hex /testbench/dut/core/ifu/PCW
|
||||
add wave -hex /testbench/dut/core/ifu/InstrW
|
||||
add wave /testbench/InstrWName
|
||||
add wave /testbench/dut/core/ieu/dp/RegWriteW
|
||||
add wave -hex /testbench/dut/core/ebu/ebu/ReadDataW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/RdW
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/dmem/*
|
||||
add wave -hex /testbench/dut/core/dmem/genblk1/*
|
||||
add wave -divider
|
||||
|
||||
add wave -hex -r /testbench/*
|
||||
|
|
@ -1,65 +0,0 @@
|
|||
# default-waves.do
|
||||
restart -f
|
||||
delete wave /*
|
||||
view wave
|
||||
|
||||
# Diplays All Signals recursively
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
#add wave /testbench/dut/core/ebu/ebu/IReadF
|
||||
#add wave /testbench/dut/core/DataStall
|
||||
add wave /testbench/dut/core/ICacheStallF
|
||||
add wave /testbench/dut/core/StallF
|
||||
add wave /testbench/dut/core/StallD
|
||||
add wave /testbench/dut/core/StallE
|
||||
add wave /testbench/dut/core/StallM
|
||||
add wave /testbench/dut/core/StallW
|
||||
add wave /testbench/dut/core/FlushD
|
||||
add wave /testbench/dut/core/FlushE
|
||||
add wave /testbench/dut/core/FlushM
|
||||
add wave /testbench/dut/core/FlushW
|
||||
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/core/ifu/PCF
|
||||
add wave -hex /testbench/dut/core/ifu/PCD
|
||||
add wave -hex /testbench/dut/core/ifu/InstrD
|
||||
add wave /testbench/InstrDName
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/core/ifu/PCE
|
||||
add wave -hex /testbench/dut/core/ifu/InstrE
|
||||
add wave /testbench/InstrEName
|
||||
add wave -hex /testbench/dut/core/ieu/dp/SrcAE
|
||||
add wave -hex /testbench/dut/core/ieu/dp/SrcBE
|
||||
add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
|
||||
#add wave /testbench/dut/core/ieu/dp/PCSrcE
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/core/ifu/PCM
|
||||
add wave -hex /testbench/dut/core/ifu/InstrM
|
||||
add wave /testbench/InstrMName
|
||||
add wave /testbench/dut/uncore/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/uncore/uncore/HADDR
|
||||
add wave -hex /testbench/dut/uncore/uncore/HWDATA
|
||||
add wave -divider
|
||||
add wave -hex /testbench/PCW
|
||||
add wave -hex /testbench/InstrW
|
||||
add wave /testbench/InstrWName
|
||||
add wave /testbench/dut/core/ieu/dp/RegWriteW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/RdW
|
||||
add wave -divider
|
||||
|
||||
add wave -hex -r /testbench/*
|
||||
|
||||
# appearance
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {100 ps}
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 150
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
# default-waves.do
|
||||
restart -f
|
||||
delete wave /*
|
||||
view wave
|
||||
|
||||
# Diplays All Signals recursively
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
add wave -hex -r /testbench/*
|
||||
|
||||
# appearance
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreZoom {0 ps} {300 ps}
|
||||
configure wave -namecolwidth 350
|
||||
configure wave -valuecolwidth 150
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 0
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
set DefaultRadix hexadecimal
|
||||
|
|
@ -1,207 +0,0 @@
|
|||
onerror {resume}
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate -divider <NULL>
|
||||
add wave -noupdate /testbench/clk
|
||||
add wave -noupdate /testbench/reset
|
||||
add wave -noupdate -radix decimal /testbench/errorCount
|
||||
add wave -noupdate -radix decimal /testbench/InstrCountW
|
||||
add wave -noupdate -divider Stalls_and_Flushes
|
||||
add wave -noupdate /testbench/dut/core/StallF
|
||||
add wave -noupdate /testbench/dut/core/StallD
|
||||
add wave -noupdate /testbench/dut/core/StallE
|
||||
add wave -noupdate /testbench/dut/core/StallM
|
||||
add wave -noupdate /testbench/dut/core/StallW
|
||||
add wave -noupdate /testbench/dut/core/FlushD
|
||||
add wave -noupdate /testbench/dut/core/FlushE
|
||||
add wave -noupdate /testbench/dut/core/FlushM
|
||||
add wave -noupdate /testbench/dut/core/FlushW
|
||||
add wave -noupdate -divider F
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCF
|
||||
add wave -noupdate -divider D
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate /testbench/InstrDName
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrD
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidD
|
||||
add wave -noupdate -divider E
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCE
|
||||
add wave -noupdate /testbench/InstrEName
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrE
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidE
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAE
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcBE
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultE
|
||||
add wave -noupdate -divider M
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCM
|
||||
add wave -noupdate /testbench/InstrMName
|
||||
add wave -noupdate /testbench/textM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/MemPAdrM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/MemRWM
|
||||
add wave -noupdate /testbench/dut/core/lsu.bus.dcache/WriteDataM
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/lsu.bus.dcache/ReadDataM
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/DTLBWalk
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/BasePageTablePPN
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/CurrentPPN
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/MemWrite
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Executable
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Writable
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Readable
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Valid
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/Misaligned
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/MegapageMisaligned
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidPTE
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/LeafPTE
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidLeafPTE
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/ValidNonLeafPTE
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/StartWalk
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/TLBMiss
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/PRegEn
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/NextPageType
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/SvMode
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/TranslationVAdr
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/WalkerState
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/NextWalkerState
|
||||
add wave -noupdate -group Walker /testbench/dut/core/lsu/hptw/genblk1/InitialWalkerState
|
||||
add wave -noupdate -group LSU -r /testbench/dut/core/lsu/*
|
||||
add wave -noupdate -group DCache -r /testbench/dut/core/lsu.bus.dcache/*
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/clk
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/reset
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/StallW
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/UnsignedLoadM
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/AtomicMaskedM
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/Funct7M
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrPAdrF
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrReadF
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrRData
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/InstrAckF
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBPAdrM
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBReadM
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBWriteM
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCtoAHBWriteData
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCfromAHBReadData
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/MemSizeM
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DCfromAHBAck
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATA
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HREADY
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRESP
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRESETn
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HADDR
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWDATA
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWRITE
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HSIZE
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HBURST
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HPROT
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HTRANS
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HMASTLOCK
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HADDRD
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HSIZED
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HWRITED
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/GrantData
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/AccessAddress
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/ISize
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATAMasked
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/ReadDataM
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/HRDATANext
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CapturedHRDATAMasked
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/WriteData
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/IReady
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/DReady
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CaptureDataM
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/CapturedDataAvailable
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/BusState
|
||||
add wave -noupdate -group EBU /testbench/dut/core/ebu/ebu/NextBusState
|
||||
add wave -noupdate -divider W
|
||||
add wave -noupdate -radix hexadecimal /testbench/PCW
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidW
|
||||
add wave -noupdate /testbench/textM
|
||||
add wave -noupdate /testbench/dut/core/ieu/dp/ReadDataW
|
||||
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -noupdate -group RF /testbench/dut/core/ieu/dp/RegWriteW
|
||||
add wave -noupdate -group RF -radix unsigned /testbench/dut/core/ieu/dp/RdW
|
||||
add wave -noupdate -group RF /testbench/dut/core/ieu/dp/regf/wd3
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[2]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[3]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[4]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[5]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[6]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[7]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[8]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[9]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[10]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[11]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[12]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[13]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[14]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[15]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[16]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[17]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[18]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[19]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[20]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[21]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[22]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[23]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[24]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[25]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[26]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[27]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[28]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[29]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[30]}
|
||||
add wave -noupdate -group RF -radix hexadecimal {/testbench/dut/core/ieu/dp/regf/rf[31]}
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MSTATUS_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTINHIBIT_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTEREN_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIDELEG_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIP_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIE_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVEC_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTEREN_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEDELEG_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIDELEG_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCH_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSE_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVAL_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/SSTATUS_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/SCOUNTEREN_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIP_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIE_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEPC_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/STVEC_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SCOUNTEREN_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEDELEG_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIDELEG_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SATP_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/USTATUS_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UEPC_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UTVEC_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIP_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIE_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MISA_REGW
|
||||
add wave -noupdate -group CSR -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/FRM_REGW
|
||||
add wave -noupdate -divider <NULL>
|
||||
add wave -hex -r /testbench/*
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 8} {42752672 ns} 1} {{Cursor 2} {42752634 ns} 0}
|
||||
quietly wave cursor active 2
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 297
|
||||
configure wave -justifyvalue left
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -snapdistance 10
|
||||
configure wave -datasetprefix 0
|
||||
configure wave -rowmargin 4
|
||||
configure wave -childrowmargin 2
|
||||
configure wave -gridoffset 0
|
||||
configure wave -gridperiod 1
|
||||
configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {42752559 ns} {42752771 ns}
|
||||
|
|
@ -1,118 +0,0 @@
|
|||
# peripheral-waves.do
|
||||
|
||||
restart -f
|
||||
delete wave /*
|
||||
view wave
|
||||
|
||||
# general stuff
|
||||
add wave /testbench/clk
|
||||
add wave /testbench/reset
|
||||
add wave -divider
|
||||
|
||||
#add wave /testbench/dut/core/DataStall
|
||||
add wave /testbench/dut/core/StallF
|
||||
add wave /testbench/dut/core/StallD
|
||||
add wave /testbench/dut/core/StallE
|
||||
add wave /testbench/dut/core/StallM
|
||||
add wave /testbench/dut/core/StallW
|
||||
add wave /testbench/dut/core/FlushD
|
||||
add wave /testbench/dut/core/FlushE
|
||||
add wave /testbench/dut/core/FlushM
|
||||
add wave /testbench/dut/core/FlushW
|
||||
add wave -divider
|
||||
|
||||
add wave -hex /testbench/dut/core/ifu/PCF
|
||||
add wave -hex /testbench/dut/core/ifu/PCD
|
||||
add wave -hex /testbench/dut/core/ifu/InstrD
|
||||
add wave -hex /testbench/dut/core/ieu/c/InstrValidD
|
||||
add wave /testbench/InstrDName
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/core/ifu/PCE
|
||||
add wave -hex /testbench/dut/core/ifu/InstrE
|
||||
add wave -hex /testbench/dut/core/ieu/c/InstrValidE
|
||||
add wave /testbench/InstrEName
|
||||
add wave -hex /testbench/dut/core/ieu/dp/SrcAE
|
||||
add wave -hex /testbench/dut/core/ieu/dp/SrcBE
|
||||
add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
|
||||
#add wave /testbench/dut/core/ieu/dp/PCSrcE
|
||||
add wave /testbench/dut/core/mdu/genblk1/div/DivStartE
|
||||
add wave /testbench/dut/core/mdu/DivBusyE
|
||||
add wave -hex /testbench/dut/core/mdu/genblk1/div/RemM
|
||||
add wave -hex /testbench/dut/core/mdu/genblk1/div/QuotM
|
||||
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/core/ifu/PCM
|
||||
add wave -hex /testbench/dut/core/ifu/InstrM
|
||||
add wave -hex /testbench/dut/core/ieu/c/InstrValidM
|
||||
add wave /testbench/InstrMName
|
||||
add wave /testbench/dut/uncore/uncore/ram/memwrite
|
||||
add wave -hex /testbench/dut/core/WriteDataM
|
||||
add wave -hex /testbench/dut/core/lsu.bus.dcache/MemPAdrM
|
||||
add wave -hex /testbench/dut/core/lsu.bus.dcache/WriteDataM
|
||||
add wave -hex /testbench/dut/core/lsu.bus.dcache/ReadDataM
|
||||
add wave -divider
|
||||
add wave -hex /testbench/PCW
|
||||
#add wave -hex /testbench/InstrW
|
||||
#add wave -hex /testbench/dut/core/ieu/c/InstrValidW
|
||||
#add wave /testbench/InstrWName
|
||||
add wave -hex /testbench/dut/core/ReadDataW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/ResultW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/RegWriteW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/WriteDataW
|
||||
add wave -hex /testbench/dut/core/ieu/dp/RdW
|
||||
add wave -divider
|
||||
add wave -hex /testbench/dut/core/priv/csr/TrapM
|
||||
add wave -hex /testbench/dut/core/priv/csr/UnalignedNextEPCM
|
||||
add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEPCM
|
||||
add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW
|
||||
|
||||
add wave -divider RegFile
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[1]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[2]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[3]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[4]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[5]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[6]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[7]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[8]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[9]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[10]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[11]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[12]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[13]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[14]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[15]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[16]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[17]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[18]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[19]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[20]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[21]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[22]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[23]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[24]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[25]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[26]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[27]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[28]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[29]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[30]
|
||||
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[31]
|
||||
|
||||
# peripherals
|
||||
add wave -divider PLIC
|
||||
add wave -hex /testbench/dut/core/priv/csr/TrapM
|
||||
add wave -hex /testbench/dut/uncore/uncore/plic/plic/*
|
||||
add wave -hex /testbench/dut/uncore/uncore/plic/plic/intPriority
|
||||
add wave -hex /testbench/dut/uncore/uncore/plic/plic/pendingArray
|
||||
add wave -divider UART
|
||||
add wave -hex /testbench/dut/uncore/uncore/uart/uart/u/*
|
||||
add wave -divider GPIO
|
||||
add wave -hex /testbench/dut/uncore/uncore/gpio/gpio/*
|
||||
#add wave -divider
|
||||
#add wave -hex /testbench/dut/core/ebu/ebu/*
|
||||
#add wave -divider
|
||||
#add wave -divider
|
||||
|
||||
# everything else
|
||||
add wave -hex -r /testbench/*
|
||||
|
|
@ -1,30 +0,0 @@
|
|||
|
||||
add wave -noupdate /testbenchfp/clk
|
||||
add wave -noupdate -radix decimal /testbenchfp/VectorNum
|
||||
add wave -noupdate /testbenchfp/FrmNum
|
||||
add wave -noupdate /testbenchfp/X
|
||||
add wave -noupdate /testbenchfp/Y
|
||||
add wave -noupdate /testbenchfp/Z
|
||||
add wave -noupdate /testbenchfp/Res
|
||||
add wave -noupdate /testbenchfp/Ans
|
||||
add wave -noupdate /testbenchfp/reset
|
||||
add wave -noupdate /testbenchfp/DivStart
|
||||
add wave -noupdate /testbenchfp/FDivBusyE
|
||||
add wave -noupdate /testbenchfp/CheckNow
|
||||
add wave -noupdate /testbenchfp/DivDone
|
||||
add wave -noupdate /testbenchfp/ResMatch
|
||||
add wave -noupdate /testbenchfp/FlagMatch
|
||||
add wave -noupdate /testbenchfp/CheckNow
|
||||
add wave -noupdate /testbenchfp/NaNGood
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/*
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/*
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/*
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/normshift/*
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/shiftcorrection/*
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/resultsign/*
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/round/*
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/fmashiftcalc/*
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/divshiftcalc/*
|
||||
add wave -group {PostProc} -noupdate /testbenchfp/postprocess/cvtshiftcalc/*
|
||||
add wave -group {Testbench} -noupdate /testbenchfp/*
|
||||
add wave -group {Testbench} -noupdate /testbenchfp/readvectors/*
|
||||
|
|
@ -12,11 +12,12 @@
|
|||
export MGLS_LICENSE_FILE=27002@zircon.eng.hmc.edu # Change this to your Siemens license server for Questa
|
||||
export SNPSLMD_LICENSE_FILE=27020@zircon.eng.hmc.edu # Change this to your Synopsys license server for Design Compiler
|
||||
export QUESTA_HOME=/cad/mentor/questa_sim-2023.4/questasim # Change this for your path to Questa, excluding bin
|
||||
export SNPS_HOME=/cad/synopsys/SYN # Change this for your path to Design Compiler, excluding bin
|
||||
export DC_HOME=/cad/synopsys/SYN # Change this for your path to Synopsys Design Compiler, excluding bin
|
||||
export VCS_HOME=/cad/synopsys/vcs/U-2023.03-SP2-4 # Change this for your path to Synopsys VCS, exccluding bin
|
||||
|
||||
# Tools
|
||||
# Questa and Synopsys
|
||||
export PATH=$QUESTA_HOME/bin:$SNPS_HOME/bin:$PATH
|
||||
export PATH=$QUESTA_HOME/bin:$DC_HOME/bin:$VCS_HOME/bin:$PATH
|
||||
|
||||
# GCC
|
||||
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ module ebufsmarb (
|
|||
statetype CurrState, NextState;
|
||||
|
||||
logic both; // Both the LSU and IFU request at the same time
|
||||
logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration
|
||||
logic IFUReqDelay; // 1 cycle delayed IFU request. Part of arbitration
|
||||
logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst
|
||||
logic BeatCntEn;
|
||||
logic [3:0] BeatCount; // Position within a burst transfer
|
||||
|
|
@ -85,11 +85,11 @@ module ebufsmarb (
|
|||
// Controller 1 (LSU)
|
||||
// When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
|
||||
// Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining
|
||||
// priority and re-issuing the same memory operation, the delayed IFUReqD squashes the LSU request.
|
||||
// priority and re-issuing the same memory operation, the delayed IFUReqDelay squashes the LSU request.
|
||||
// This is necessary because the pipeline is stalled for the entire duration of both transactions,
|
||||
// and the LSU memory request will stil be active.
|
||||
flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD);
|
||||
assign LSUDisable = (CurrState == ARBITRATE) ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeatD));
|
||||
flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqDelay);
|
||||
assign LSUDisable = (CurrState == ARBITRATE) ? 1'b0 : (IFUReqDelay & ~(HREADY & FinalBeatD));
|
||||
assign LSUSelect = (NextState == ARBITRATE) ? 1'b1: LSUReq;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
|
|||
|
|
@ -83,23 +83,23 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
|
|||
if (P.FPSIZES == 1) begin
|
||||
logic Sum0LEZ, Sum0GEFL;
|
||||
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
|
||||
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
|
||||
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
|
||||
assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
|
||||
end else if (P.FPSIZES == 2) begin
|
||||
logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL;
|
||||
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
|
||||
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
|
||||
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
|
||||
assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
|
||||
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-2+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
|
||||
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
|
||||
assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL) & ~FmaSZero;
|
||||
end else if (P.FPSIZES == 3) begin
|
||||
logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL;
|
||||
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
|
||||
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
|
||||
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1));
|
||||
assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
|
||||
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-2+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
|
||||
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
|
||||
assign Sum2LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS2));
|
||||
assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-2+P.BIAS-P.BIAS2)) | ~|PreNormSumExp;
|
||||
assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-1+P.BIAS-P.BIAS2)) | ~|PreNormSumExp;
|
||||
always_comb begin
|
||||
case (Fmt)
|
||||
P.FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL; // & ~FmaSZero; // checking sum is not zero is harmless but turns out to be unnecessary
|
||||
|
|
@ -111,13 +111,13 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
|
|||
end else if (P.FPSIZES == 4) begin
|
||||
logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL, Sum3LEZ, Sum3GEFL;
|
||||
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
|
||||
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-2));
|
||||
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1));
|
||||
assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.D_BIAS));
|
||||
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.D_NF-2+P.BIAS-P.D_BIAS)) | ~|PreNormSumExp;
|
||||
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.D_NF-1+P.BIAS-P.D_BIAS)) | ~|PreNormSumExp;
|
||||
assign Sum2LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.S_BIAS));
|
||||
assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.S_NF-2+P.BIAS-P.S_BIAS)) | ~|PreNormSumExp;
|
||||
assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.S_NF-1+P.BIAS-P.S_BIAS)) | ~|PreNormSumExp;
|
||||
assign Sum3LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.H_BIAS));
|
||||
assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-2+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp;
|
||||
assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-1+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp;
|
||||
always_comb begin
|
||||
case (Fmt)
|
||||
2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero;
|
||||
|
|
|
|||
|
|
@ -150,6 +150,7 @@ module clint_apb import cvw::*; #(parameter cvw_t P) (
|
|||
|
||||
endmodule
|
||||
|
||||
/*
|
||||
module timeregsync import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk, resetn,
|
||||
input logic we0, we1,
|
||||
|
|
@ -169,6 +170,7 @@ module timeregsync import cvw::*; #(parameter cvw_t P) (
|
|||
else q <= q + 1;
|
||||
endmodule
|
||||
|
||||
|
||||
module timereg import cvw::*; #(parameter cvw_t P) (
|
||||
input logic PCLK, PRESETn, TIMECLK,
|
||||
input logic we0, we1,
|
||||
|
|
@ -245,3 +247,4 @@ module graytobinary #(parameter N) (
|
|||
assign b[i] = g[i] ^ b[i+1];
|
||||
end
|
||||
endmodule
|
||||
*/
|
||||
|
|
@ -27,7 +27,7 @@
|
|||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module loggers import cvw::*; #(parameter cvw_t P,
|
||||
parameter string TEST,
|
||||
|
||||
parameter PrintHPMCounters,
|
||||
parameter I_CACHE_ADDR_LOGGER,
|
||||
parameter D_CACHE_ADDR_LOGGER,
|
||||
|
|
@ -39,7 +39,8 @@ module loggers import cvw::*; #(parameter cvw_t P,
|
|||
// input logic BeginSample,
|
||||
// input logic StartSample,
|
||||
// input logic EndSample,
|
||||
input string memfilename
|
||||
input string memfilename,
|
||||
input string TEST
|
||||
);
|
||||
|
||||
// performance counter logging
|
||||
|
|
@ -79,40 +80,64 @@ module loggers import cvw::*; #(parameter cvw_t P,
|
|||
"Divide Cycles"
|
||||
};
|
||||
|
||||
always_comb
|
||||
if (TEST == "embench") begin
|
||||
StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
|
||||
EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
|
||||
end else if (TEST == "coremark") begin
|
||||
StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
|
||||
EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
|
||||
end else begin
|
||||
StartSampleFirst = reset;
|
||||
EndSample = DCacheFlushStart & ~DCacheFlushDone;
|
||||
end
|
||||
|
||||
/*
|
||||
if(TEST == "embench") begin
|
||||
// embench runs warmup then runs start_trigger
|
||||
// embench end with stop_trigger.
|
||||
assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
|
||||
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
|
||||
assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
|
||||
//assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
|
||||
//flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
|
||||
//assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
|
||||
|
||||
assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
|
||||
//assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
|
||||
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
|
||||
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
|
||||
|
||||
end else if(TEST == "coremark") begin
|
||||
// embench runs warmup then runs start_trigger
|
||||
// embench end with stop_trigger.
|
||||
assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
|
||||
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
|
||||
assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
|
||||
//assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
|
||||
//flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
|
||||
//assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
|
||||
|
||||
assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
|
||||
//assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
|
||||
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
|
||||
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
|
||||
|
||||
end else begin
|
||||
// default start condiction is reset
|
||||
// default end condiction is end of test (DCacheFlushDone)
|
||||
assign StartSampleFirst = reset;
|
||||
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
|
||||
assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
|
||||
assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
|
||||
//assign StartSampleFirst = reset;
|
||||
//flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
|
||||
//assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
|
||||
//assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
|
||||
|
||||
flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
|
||||
assign BeginSample = StartSampleFirst & ~BeginDelayed;
|
||||
|
||||
end
|
||||
|
||||
*/
|
||||
|
||||
flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
|
||||
assign StartSample = StartSampleFirst & ~StartSampleDelayed;
|
||||
flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
|
||||
assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
|
||||
flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); // ** is this redundant with StartSampleReg?
|
||||
assign BeginSample = StartSampleFirst & ~BeginDelayed;
|
||||
|
||||
|
||||
always @(negedge clk) begin
|
||||
if(StartSample) begin
|
||||
for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
|
||||
|
|
@ -153,7 +178,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
|
|||
end
|
||||
string AccessTypeString, HitMissString;
|
||||
always @(*) begin
|
||||
HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" :
|
||||
HitMissString = dut.core.ifu.bus.icache.icache.Hit ? "H" :
|
||||
dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
|
||||
end
|
||||
always @(posedge clk) begin
|
||||
|
|
@ -178,7 +203,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
|
|||
flop #(1) ResetDReg(clk, reset, resetD);
|
||||
assign resetEdge = ~reset & resetD;
|
||||
always @(*) begin
|
||||
HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" :
|
||||
HitMissString = dut.core.lsu.bus.dcache.dcache.Hit ? "H" :
|
||||
(!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
|
||||
dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
|
||||
AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
|
||||
|
|
|
|||
25
testbench/coverage/test_fencei_coverage.svh
Normal file
25
testbench/coverage/test_fencei_coverage.svh
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
typedef RISCV_instruction #(ILEN, XLEN, FLEN, VLEN, NHART, RETIRE) test_ins_rv64i_t;
|
||||
|
||||
covergroup test_fencei_cg with function sample(test_ins_rv64i_t ins);
|
||||
option.per_instance = 1;
|
||||
option.comment = "Fence.I";
|
||||
|
||||
cp_asm_count : coverpoint ins.ins_str == "fence.i" iff (ins.trap == 0 ) {
|
||||
option.comment = "Number of times instruction is executed";
|
||||
bins count[] = {1};
|
||||
}
|
||||
endgroup
|
||||
|
||||
function void test_fencei_sample(int hart, int issue);
|
||||
test_ins_rv64i_t ins;
|
||||
|
||||
case (traceDataQ[hart][issue][0].inst_name)
|
||||
"fenci" : begin
|
||||
ins = new(hart, issue, traceDataQ);
|
||||
test_fencei_cg.sample(ins);
|
||||
end
|
||||
endcase
|
||||
|
||||
endfunction
|
||||
|
||||
|
||||
4
testbench/coverage/test_fencei_coverage_init.svh
Normal file
4
testbench/coverage/test_fencei_coverage_init.svh
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
test_fencei_cg = new(); test_fencei_cg.set_inst_name("obj_fencei");
|
||||
|
||||
// test_fencei_cg = new();
|
||||
//test_fencei_cg.set_inst_name("obj_fencei");
|
||||
|
|
@ -1,623 +0,0 @@
|
|||
///////////////////////////////////////////
|
||||
// testbench.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 9 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Wally Testbench and helper modules
|
||||
// Applies test programs from the riscv-arch-test and Imperas suites
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "config.vh"
|
||||
`include "tests.vh"
|
||||
|
||||
import cvw::*;
|
||||
|
||||
module testbench;
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
/* verilator lint_off WIDTHEXPAND */
|
||||
parameter DEBUG=0;
|
||||
parameter TEST="none";
|
||||
parameter PrintHPMCounters=1;
|
||||
parameter BPRED_LOGGER=0;
|
||||
parameter I_CACHE_ADDR_LOGGER=0;
|
||||
parameter D_CACHE_ADDR_LOGGER=0;
|
||||
|
||||
`include "parameter-defs.vh"
|
||||
|
||||
logic clk;
|
||||
logic reset_ext, reset;
|
||||
logic ResetMem;
|
||||
|
||||
// DUT signals
|
||||
logic [P.AHBW-1:0] HRDATAEXT;
|
||||
logic HREADYEXT, HRESPEXT;
|
||||
logic [P.PA_BITS-1:0] HADDR;
|
||||
logic [P.AHBW-1:0] HWDATA;
|
||||
logic [P.XLEN/8-1:0] HWSTRB;
|
||||
logic HWRITE;
|
||||
logic [2:0] HSIZE;
|
||||
logic [2:0] HBURST;
|
||||
logic [3:0] HPROT;
|
||||
logic [1:0] HTRANS;
|
||||
logic HMASTLOCK;
|
||||
logic HCLK, HRESETn;
|
||||
|
||||
logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
|
||||
logic UARTSin, UARTSout;
|
||||
|
||||
logic SDCCLK;
|
||||
logic SDCCmdIn;
|
||||
logic SDCCmdOut;
|
||||
logic SDCCmdOE;
|
||||
logic [3:0] SDCDatIn;
|
||||
tri1 [3:0] SDCDat;
|
||||
tri1 SDCCmd;
|
||||
logic SPIIn, SPIOut;
|
||||
logic [3:0] SPICS;
|
||||
|
||||
logic HREADY;
|
||||
logic HSELEXT;
|
||||
|
||||
|
||||
string ProgramAddrMapFile, ProgramLabelMapFile;
|
||||
integer ProgramAddrLabelArray [string];
|
||||
|
||||
int test, i, errors, totalerrors;
|
||||
|
||||
string outputfile;
|
||||
integer outputFilePointer;
|
||||
|
||||
string tests[];
|
||||
logic DCacheFlushDone, DCacheFlushStart;
|
||||
logic riscofTest;
|
||||
logic Validate;
|
||||
logic SelectTest;
|
||||
|
||||
|
||||
|
||||
// pick tests based on modes supported
|
||||
initial begin
|
||||
$display("TEST is %s", TEST);
|
||||
//tests = '{};
|
||||
if (P.XLEN == 64) begin // RV64
|
||||
case (TEST)
|
||||
"arch64i": tests = arch64i;
|
||||
"arch64priv": tests = arch64priv;
|
||||
"arch64c": if (P.C_SUPPORTED)
|
||||
if (P.ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
|
||||
else tests = {arch64c};
|
||||
"arch64m": if (P.M_SUPPORTED) tests = arch64m;
|
||||
"arch64f": if (P.F_SUPPORTED) tests = arch64f;
|
||||
"arch64d": if (P.D_SUPPORTED) tests = arch64d;
|
||||
"arch64f_fma": if (P.F_SUPPORTED) tests = arch64f_fma;
|
||||
"arch64d_fma": if (P.D_SUPPORTED) tests = arch64d_fma;
|
||||
"arch64zi": if (P.ZIFENCEI_SUPPORTED) tests = arch64zi;
|
||||
"imperas64i": tests = imperas64i;
|
||||
"imperas64f": if (P.F_SUPPORTED) tests = imperas64f;
|
||||
"imperas64d": if (P.D_SUPPORTED) tests = imperas64d;
|
||||
"imperas64m": if (P.M_SUPPORTED) tests = imperas64m;
|
||||
"wally64a": if (P.A_SUPPORTED) tests = wally64a;
|
||||
"imperas64c": if (P.C_SUPPORTED) tests = imperas64c;
|
||||
else tests = imperas64iNOc;
|
||||
"custom": tests = custom;
|
||||
"wally64i": tests = wally64i;
|
||||
"wally64priv": tests = wally64priv;
|
||||
"wally64periph": tests = wally64periph;
|
||||
"coremark": tests = coremark;
|
||||
"fpga": tests = fpga;
|
||||
"ahb" : tests = ahb;
|
||||
"coverage64gc" : tests = coverage64gc;
|
||||
"arch64zba": if (P.ZBA_SUPPORTED) tests = arch64zba;
|
||||
"arch64zbb": if (P.ZBB_SUPPORTED) tests = arch64zbb;
|
||||
"arch64zbc": if (P.ZBC_SUPPORTED) tests = arch64zbc;
|
||||
"arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs;
|
||||
"arch64zbkb": if (P.ZBKB_SUPPORTED) tests = arch64zbkb;
|
||||
"arch64zbkc": if (P.ZBKC_SUPPORTED) tests = arch64zbkc;
|
||||
"arch64zbkx": if (P.ZBKX_SUPPORTED) tests = arch64zbkx;
|
||||
"arch64zknd": if (P.ZKND_SUPPORTED) tests = arch64zknd;
|
||||
"arch64zkne": if (P.ZKNE_SUPPORTED) tests = arch64zkne;
|
||||
"arch64zknh": if (P.ZKNH_SUPPORTED) tests = arch64zknh;
|
||||
endcase
|
||||
end else begin // RV32
|
||||
case (TEST)
|
||||
"arch32i": tests = arch32i;
|
||||
"arch32priv": tests = arch32priv;
|
||||
"arch32c": if (P.C_SUPPORTED)
|
||||
if (P.ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
|
||||
else tests = {arch32c};
|
||||
"arch32m": if (P.M_SUPPORTED) tests = arch32m;
|
||||
"arch32f": if (P.F_SUPPORTED) tests = arch32f;
|
||||
"arch32d": if (P.D_SUPPORTED) tests = arch32d;
|
||||
"arch32f_fma": if (P.F_SUPPORTED) tests = arch32f_fma;
|
||||
"arch32d_fma": if (P.D_SUPPORTED) tests = arch32d_fma;
|
||||
"arch32zi": if (P.ZIFENCEI_SUPPORTED) tests = arch32zi;
|
||||
"imperas32i": tests = imperas32i;
|
||||
"imperas32f": if (P.F_SUPPORTED) tests = imperas32f;
|
||||
"imperas32m": if (P.M_SUPPORTED) tests = imperas32m;
|
||||
"wally32a": if (P.A_SUPPORTED) tests = wally32a;
|
||||
"imperas32c": if (P.C_SUPPORTED) tests = imperas32c;
|
||||
else tests = imperas32iNOc;
|
||||
"wally32i": tests = wally32i;
|
||||
"wally32e": tests = wally32e;
|
||||
"wally32priv": tests = wally32priv;
|
||||
"wally32periph": tests = wally32periph;
|
||||
"embench": tests = embench;
|
||||
"coremark": tests = coremark;
|
||||
"arch32zba": if (P.ZBA_SUPPORTED) tests = arch32zba;
|
||||
"arch32zbb": if (P.ZBB_SUPPORTED) tests = arch32zbb;
|
||||
"arch32zbc": if (P.ZBC_SUPPORTED) tests = arch32zbc;
|
||||
"arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs;
|
||||
"arch32zbkb": if (P.ZBKB_SUPPORTED) tests = arch32zbkb;
|
||||
"arch32zbkc": if (P.ZBKC_SUPPORTED) tests = arch32zbkc;
|
||||
"arch32zbkx": if (P.ZBKX_SUPPORTED) tests = arch32zbkx;
|
||||
"arch32zknd": if (P.ZKND_SUPPORTED) tests = arch32zknd;
|
||||
"arch32zkne": if (P.ZKNE_SUPPORTED) tests = arch32zkne;
|
||||
"arch32zknh": if (P.ZKNH_SUPPORTED) tests = arch32zknh;
|
||||
endcase
|
||||
end
|
||||
if (tests.size() == 0) begin
|
||||
$display("TEST %s not supported in this configuration", TEST);
|
||||
$stop;
|
||||
end
|
||||
end // initial begin
|
||||
|
||||
// Model the testbench as an fsm.
|
||||
// Do this in parts so it easier to verify
|
||||
// part 1: build a version which echos the same behavior as the below code, but does not drive anything
|
||||
// part 2: drive some of the controls
|
||||
// part 3: drive all logic and remove old inital and always @ negedge clk block
|
||||
|
||||
typedef enum logic [3:0]{STATE_TESTBENCH_RESET,
|
||||
STATE_INIT_TEST,
|
||||
STATE_RESET_MEMORIES,
|
||||
STATE_RESET_MEMORIES2,
|
||||
STATE_LOAD_MEMORIES,
|
||||
STATE_RESET_TEST,
|
||||
STATE_RUN_TEST,
|
||||
STATE_CHECK_TEST,
|
||||
STATE_CHECK_TEST_WAIT,
|
||||
STATE_VALIDATE,
|
||||
STATE_INCR_TEST} statetype;
|
||||
statetype CurrState, NextState;
|
||||
logic TestBenchReset;
|
||||
logic [2:0] ResetCount, ResetThreshold;
|
||||
logic LoadMem;
|
||||
logic ResetCntEn;
|
||||
logic ResetCntRst;
|
||||
|
||||
|
||||
string signame, memfilename, pathname;
|
||||
integer begin_signature_addr;
|
||||
|
||||
assign ResetThreshold = 3'd5;
|
||||
|
||||
initial begin
|
||||
TestBenchReset = 1;
|
||||
# 100;
|
||||
TestBenchReset = 0;
|
||||
end
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
|
||||
else CurrState <= #1 NextState;
|
||||
|
||||
// fsm next state logic
|
||||
always_comb begin
|
||||
// riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests
|
||||
// and tests[0] == "2" refers to WallyRiscvArchTests
|
||||
riscofTest = tests[0] == "1" | tests[0] == "2";
|
||||
pathname = tvpaths[tests[0].atoi()];
|
||||
|
||||
case(CurrState)
|
||||
STATE_TESTBENCH_RESET: NextState = STATE_INIT_TEST;
|
||||
STATE_INIT_TEST: NextState = STATE_RESET_MEMORIES;
|
||||
STATE_RESET_MEMORIES: NextState = STATE_RESET_MEMORIES2;
|
||||
STATE_RESET_MEMORIES2: NextState = STATE_LOAD_MEMORIES; // Give the reset enough time to ensure the bus is reset before loading the memories.
|
||||
STATE_LOAD_MEMORIES: NextState = STATE_RESET_TEST;
|
||||
STATE_RESET_TEST: if(ResetCount < ResetThreshold) NextState = STATE_RESET_TEST;
|
||||
else NextState = STATE_RUN_TEST;
|
||||
STATE_RUN_TEST: if(DCacheFlushStart) NextState = STATE_CHECK_TEST;
|
||||
else NextState = STATE_RUN_TEST;
|
||||
STATE_CHECK_TEST: if (DCacheFlushDone) NextState = STATE_VALIDATE;
|
||||
else NextState = STATE_CHECK_TEST_WAIT;
|
||||
STATE_CHECK_TEST_WAIT: if(DCacheFlushDone) NextState = STATE_VALIDATE;
|
||||
else NextState = STATE_CHECK_TEST_WAIT;
|
||||
STATE_VALIDATE: NextState = STATE_INIT_TEST;
|
||||
STATE_INCR_TEST: NextState = STATE_INIT_TEST;
|
||||
default: NextState = STATE_TESTBENCH_RESET;
|
||||
endcase
|
||||
end // always_comb
|
||||
// fsm output control logic
|
||||
assign reset_ext = CurrState == STATE_TESTBENCH_RESET | CurrState == STATE_INIT_TEST |
|
||||
CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2 |
|
||||
CurrState == STATE_LOAD_MEMORIES | CurrState ==STATE_RESET_TEST;
|
||||
// this initialization is very expensive, only do it for coremark.
|
||||
assign ResetMem = (CurrState == STATE_RESET_MEMORIES | CurrState == STATE_RESET_MEMORIES2) & TEST == "coremark";
|
||||
assign LoadMem = CurrState == STATE_LOAD_MEMORIES;
|
||||
assign ResetCntRst = CurrState == STATE_INIT_TEST;
|
||||
assign ResetCntEn = CurrState == STATE_RESET_TEST;
|
||||
assign Validate = CurrState == STATE_VALIDATE;
|
||||
assign SelectTest = CurrState == STATE_INIT_TEST;
|
||||
|
||||
// fsm reset counter
|
||||
counter #(3) RstCounter(clk, ResetCntRst, ResetCntEn, ResetCount);
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Find the test vector files and populate the PC to function label converter
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
logic [P.XLEN-1:0] testadr;
|
||||
assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
|
||||
always @(posedge clk) begin
|
||||
if(SelectTest) begin
|
||||
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
|
||||
else memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
if (riscofTest) begin
|
||||
ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
|
||||
end else begin
|
||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
||||
end
|
||||
// declare memory labels that interest us, the updateProgramAddrLabelArray task will find
|
||||
// the addr of each label and fill the array. To expand, add more elements to this array
|
||||
// and initialize them to zero (also initilaize them to zero at the start of the next test)
|
||||
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Verify the test ran correctly by checking the memory against a known signature.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
if(TestBenchReset) test = 1;
|
||||
if (TEST == "coremark")
|
||||
if (dut.core.EcallFaultM) begin
|
||||
$display("Benchmark: coremark is done.");
|
||||
$stop;
|
||||
end
|
||||
if(Validate) begin
|
||||
if (TEST == "embench") begin
|
||||
// Writes contents of begin_signature to .sim.output file
|
||||
// this contains instret and cycles for start and end of test run, used by embench
|
||||
// python speed script to calculate embench speed score.
|
||||
// also, begin_signature contains the results of the self checking mechanism,
|
||||
// which will be read by the python script for error checking
|
||||
$display("Embench Benchmark: %s is done.", tests[test]);
|
||||
if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
|
||||
else outputfile = {pathname, tests[test], ".sim.output"};
|
||||
outputFilePointer = $fopen(outputfile, "w");
|
||||
i = 0;
|
||||
testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
|
||||
while ($unsigned(i) < $unsigned(5'd5)) begin
|
||||
$fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
|
||||
i = i + 1;
|
||||
end
|
||||
$fclose(outputFilePointer);
|
||||
$display("Embench Benchmark: created output file: %s", outputfile);
|
||||
end else if (TEST == "coverage64gc") begin
|
||||
$display("Coverage tests don't get checked");
|
||||
end else begin
|
||||
// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
|
||||
// clear signature to prevent contamination from previous tests
|
||||
end
|
||||
|
||||
if (!begin_signature_addr)
|
||||
$display("begin_signature addr not found in %s", ProgramLabelMapFile);
|
||||
else if (TEST != "embench") begin // *** quick hack for embench. need a better long term solution
|
||||
CheckSignature(pathname, tests[test], riscofTest, begin_signature_addr, errors);
|
||||
end
|
||||
if(errors > 0) totalerrors = totalerrors + 1;
|
||||
test = test + 1; // *** this probably needs to be moved.
|
||||
if (test == tests.size()) begin
|
||||
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
|
||||
else $display("FAIL: %d test programs had errors", totalerrors);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Some memories are not reset, but should be zeros or set to some initial value for simulation
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
integer adrindex;
|
||||
|
||||
if (P.UNCORE_RAM_SUPPORTED) `define TB_UNCORE_RAM_SUPPORTED;
|
||||
if (P.BPRED_SUPPORTED) `define TB_BPRED_SUPPORTED;
|
||||
if (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR) `define TB_BHT;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (ResetMem) // program memory is sometimes reset
|
||||
if (P.UNCORE_RAM_SUPPORTED) begin
|
||||
`ifdef TB_UNCORE_RAM_SUPPORTED
|
||||
for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
|
||||
dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = 0;
|
||||
`endif
|
||||
end
|
||||
if(reset) begin // branch predictor must always be reset
|
||||
if (P.BPRED_SUPPORTED) begin
|
||||
`ifdef TB_BPRED_SUPPORTED
|
||||
// local history only
|
||||
if (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR) begin
|
||||
`ifdef TB_BHT
|
||||
for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++)
|
||||
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0;
|
||||
`endif
|
||||
end
|
||||
// these are both always included if there is a bpred
|
||||
for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++)
|
||||
dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
|
||||
for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++)
|
||||
dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
|
||||
`endif
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// load memories with program image
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
if (P.SDC_SUPPORTED) `define TB_SDC_SUPPORTED // this is a gross hack for xcelium and verilator
|
||||
if (P.IROM_SUPPORTED) `define TB_IROM_SUPPORTED
|
||||
if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED
|
||||
if (P.BUS_SUPPORTED) `define TB_BUS_SUPPORTED
|
||||
always @(posedge clk) begin
|
||||
if (LoadMem) begin
|
||||
if (P.SDC_SUPPORTED) begin
|
||||
`ifdef TB_SDC_SUPPORTED
|
||||
string romfilename, sdcfilename;
|
||||
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
|
||||
sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
|
||||
//$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
|
||||
//$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
|
||||
// shorten sdc timers for simulation
|
||||
//dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
|
||||
`endif
|
||||
end
|
||||
else if (P.IROM_SUPPORTED) begin
|
||||
`ifdef TB_IROM_SUPPORTED
|
||||
$readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
|
||||
`endif
|
||||
end
|
||||
else if (P.BUS_SUPPORTED) begin
|
||||
`ifdef TB_BUS_SUPPORTED
|
||||
$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
|
||||
`endif
|
||||
end
|
||||
if (P.DTIM_SUPPORTED) begin
|
||||
`ifdef TB_DTIM_SUPPORTED
|
||||
$readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
|
||||
`endif
|
||||
end
|
||||
$display("Read memfile %s", memfilename);
|
||||
end
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Actual hardware
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// instantiate device to be tested
|
||||
assign GPIOIN = 0;
|
||||
assign UARTSin = 1;
|
||||
|
||||
if(P.EXT_MEM_SUPPORTED) begin
|
||||
ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
|
||||
ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
|
||||
.HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
|
||||
end else begin
|
||||
assign HREADYEXT = 1;
|
||||
assign {HRESPEXT, HRDATAEXT} = 0;
|
||||
end
|
||||
|
||||
if(P.FPGA) begin : sdcard
|
||||
sdModel sdcard
|
||||
(.sdClk(SDCCLK),
|
||||
.cmd(SDCCmd),
|
||||
.dat(SDCDat));
|
||||
|
||||
assign SDCCmd = SDCCmdOE ? SDCCmdOut : 1'bz;
|
||||
assign SDCCmdIn = SDCCmd;
|
||||
assign SDCDatIn = SDCDat;
|
||||
end else begin
|
||||
assign SDCCmd = 0;
|
||||
assign SDCDat = 0;
|
||||
end
|
||||
|
||||
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
|
||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout, .SDCIntr, .SPICS, .SPIOut, .SPIIn);
|
||||
|
||||
// generate clock to sequence tests
|
||||
always begin
|
||||
clk = 1; # 5; clk = 0; # 5;
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Support logic
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Duplicate copy of pipeline registers that are optimized out of some configurations
|
||||
logic [31:0] NextInstrE, InstrM;
|
||||
mux2 #(32) FlushInstrMMux(dut.core.ifu.InstrE, dut.core.ifu.nop, dut.core.ifu.FlushM, NextInstrE);
|
||||
flopenr #(32) InstrMReg(clk, reset, ~dut.core.ifu.StallM, NextInstrE, InstrM);
|
||||
|
||||
// Track names of instructions
|
||||
string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
|
||||
logic [31:0] InstrW;
|
||||
flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, InstrM, InstrW);
|
||||
instrTrackerTB it(clk, reset, dut.core.ieu.dp.FlushE,
|
||||
dut.core.ifu.InstrRawF[31:0],
|
||||
dut.core.ifu.InstrD, dut.core.ifu.InstrE,
|
||||
InstrM, InstrW,
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// watch for problems such as lockup, reading unitialized memory, bad configs
|
||||
watchdog #(P.XLEN, 1000000) watchdog(.clk, .reset); // check if PCW is stuck
|
||||
ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM,
|
||||
dut.core.ifu.PCM, InstrM, dut.core.lsu.IEUAdrM, InstrMName);
|
||||
riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration
|
||||
loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
|
||||
loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename);
|
||||
|
||||
// track the current function or global label
|
||||
if (DEBUG == 1 | (PrintHPMCounters & P.ZICNTR_SUPPORTED)) begin : FunctionName
|
||||
FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset),
|
||||
.clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
|
||||
end
|
||||
|
||||
|
||||
// Termination condition
|
||||
// terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed
|
||||
// or sw gp,-56(t0) for new Imperas tests
|
||||
// or sd gp, -56(t0)
|
||||
// or on a jump to self infinite loop (6f) for RISC-V Arch tests
|
||||
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
|
||||
if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
|
||||
else assign ecf = 0;
|
||||
assign DCacheFlushStart = ecf &
|
||||
(dut.core.ieu.dp.regf.rf[3] == 1 |
|
||||
(dut.core.ieu.dp.regf.we3 &
|
||||
dut.core.ieu.dp.regf.a3 == 3 &
|
||||
dut.core.ieu.dp.regf.wd3 == 1)) |
|
||||
((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
|
||||
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
|
||||
|
||||
DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
|
||||
|
||||
task automatic CheckSignature;
|
||||
// This task must be declared inside this module as it needs access to parameter P. There is
|
||||
// no way to pass P to the task unless we convert it to a module.
|
||||
|
||||
input string pathname;
|
||||
input string TestName;
|
||||
input logic riscofTest;
|
||||
input integer begin_signature_addr;
|
||||
output integer errors;
|
||||
|
||||
localparam SIGNATURESIZE = 5000000;
|
||||
integer i;
|
||||
logic [31:0] sig32[0:SIGNATURESIZE];
|
||||
logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
|
||||
string signame;
|
||||
logic [P.XLEN-1:0] testadr, testadrNoBase;
|
||||
|
||||
if (P.DTIM_SUPPORTED) `define TB_DTIM_SUPPORTED2
|
||||
|
||||
// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
|
||||
// clear signature to prevent contamination from previous tests
|
||||
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
||||
sig32[i] = 'bx;
|
||||
end
|
||||
if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
|
||||
else signame = {pathname, TestName, ".signature.output"};
|
||||
// read signature, reformat in 64 bits if necessary
|
||||
$readmemh(signame, sig32);
|
||||
i = 0;
|
||||
while (i < SIGNATURESIZE) begin
|
||||
if (P.XLEN == 32) begin
|
||||
signature[i] = sig32[i];
|
||||
i = i+1;
|
||||
end else begin
|
||||
signature[i/2] = {sig32[i+1], sig32[i]};
|
||||
i = i + 2;
|
||||
end
|
||||
if (i >= 4 & sig32[i-4] === 'bx) begin
|
||||
if (i == 4) begin
|
||||
i = SIGNATURESIZE+1; // flag empty file
|
||||
$display(" Error: empty test file");
|
||||
end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
|
||||
end
|
||||
end
|
||||
|
||||
// Check errors
|
||||
errors = (i == SIGNATURESIZE+1); // error if file is empty
|
||||
i = 0;
|
||||
testadr = ($unsigned(begin_signature_addr))/(P.XLEN/8);
|
||||
testadrNoBase = (begin_signature_addr - P.UNCORE_RAM_BASE)/(P.XLEN/8);
|
||||
/* verilator lint_off INFINITELOOP */
|
||||
while (signature[i] !== 'bx) begin
|
||||
logic [P.XLEN-1:0] sig;
|
||||
if (P.DTIM_SUPPORTED) begin
|
||||
`ifdef TB_DTIM_SUPPORTED2
|
||||
//sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
|
||||
`endif
|
||||
end
|
||||
else if (P.UNCORE_RAM_SUPPORTED) begin
|
||||
`ifdef TB_UNCORE_RAM_SUPPORTED
|
||||
sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
|
||||
//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
|
||||
`endif
|
||||
end
|
||||
if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
||||
errors = errors+1;
|
||||
$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
|
||||
TestName, i, (testadr+i)*(P.XLEN/8), testbench.DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
|
||||
$stop; //***debug
|
||||
end
|
||||
i = i + 1;
|
||||
end
|
||||
/* verilator lint_on INFINITELOOP */
|
||||
if (errors == 0) begin
|
||||
$display("%s succeeded. Brilliant!!!", TestName);
|
||||
end else begin
|
||||
$display("%s failed with %d errors. :(", TestName, errors);
|
||||
//totalerrors = totalerrors+1;
|
||||
end
|
||||
|
||||
endtask //
|
||||
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
/* verilator lint_on WIDTHEXPAND */
|
||||
|
||||
endmodule
|
||||
|
||||
/* verilator lint_on STMTDLY */
|
||||
/* verilator lint_on WIDTH */
|
||||
|
||||
task automatic updateProgramAddrLabelArray;
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
/* verilator lint_off WIDTHEXPAND */
|
||||
input string ProgramAddrMapFile, ProgramLabelMapFile;
|
||||
inout integer ProgramAddrLabelArray [string];
|
||||
// Gets the memory location of begin_signature
|
||||
integer ProgramLabelMapFP, ProgramAddrMapFP;
|
||||
ProgramLabelMapFP = $fopen(ProgramLabelMapFile, "r");
|
||||
ProgramAddrMapFP = $fopen(ProgramAddrMapFile, "r");
|
||||
|
||||
|
||||
if (ProgramLabelMapFP & ProgramAddrMapFP) begin // check we found both files
|
||||
// *** RT: I'm a bit confused by the required initialization here.
|
||||
ProgramAddrLabelArray["begin_signature"] = 0;
|
||||
ProgramAddrLabelArray["tohost"] = 0;
|
||||
while (!$feof(ProgramLabelMapFP)) begin
|
||||
string label, adrstr;
|
||||
integer returncode;
|
||||
returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
|
||||
returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
|
||||
if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
|
||||
end
|
||||
end
|
||||
$fclose(ProgramLabelMapFP);
|
||||
$fclose(ProgramAddrMapFP);
|
||||
/* verilator lint_on WIDTHTRUNC */
|
||||
/* verilator lint_on WIDTHEXPAND */
|
||||
endtask
|
||||
|
||||
|
|
@ -34,18 +34,16 @@
|
|||
`endif
|
||||
|
||||
import cvw::*;
|
||||
import "DPI-C" function string getenv(input string env_name);
|
||||
|
||||
module testbench;
|
||||
/* verilator lint_off WIDTHTRUNC */
|
||||
/* verilator lint_off WIDTHEXPAND */
|
||||
parameter DEBUG=0;
|
||||
parameter string TEST="arch64m";
|
||||
parameter PrintHPMCounters=0;
|
||||
parameter BPRED_LOGGER=0;
|
||||
parameter I_CACHE_ADDR_LOGGER=0;
|
||||
parameter D_CACHE_ADDR_LOGGER=0;
|
||||
parameter RISCV_DIR = "/opt/riscv";
|
||||
parameter INSTR_LIMIT = 0;
|
||||
|
||||
`ifdef USE_IMPERAS_DV
|
||||
import idvPkg::*;
|
||||
|
|
@ -59,6 +57,11 @@ module testbench;
|
|||
logic reset_ext, reset;
|
||||
logic ResetMem;
|
||||
|
||||
// Variables that can be overwritten with $value$plusargs at start of simulation
|
||||
string TEST;
|
||||
integer INSTR_LIMIT;
|
||||
string RISCV_DIR = getenv("RISCV"); // "/opt/riscv";
|
||||
|
||||
// DUT signals
|
||||
logic [P.AHBW-1:0] HRDATAEXT;
|
||||
logic HREADYEXT, HRESPEXT;
|
||||
|
|
@ -99,9 +102,14 @@ module testbench;
|
|||
logic SelectTest;
|
||||
logic TestComplete;
|
||||
|
||||
// pick tests based on modes supported
|
||||
initial begin
|
||||
$display("TEST is %s", TEST);
|
||||
// look for arguments passed to simulation, or use defaults
|
||||
if (!$value$plusargs("TEST=%s", TEST))
|
||||
TEST = "none";
|
||||
if (!$value$plusargs("INSTR_LIMIT=%d", INSTR_LIMIT))
|
||||
INSTR_LIMIT = 0;
|
||||
|
||||
// pick tests based on modes supported
|
||||
//tests = '{};
|
||||
if (P.XLEN == 64) begin // RV64
|
||||
case (TEST)
|
||||
|
|
@ -236,7 +244,7 @@ module testbench;
|
|||
logic ResetCntRst;
|
||||
logic CopyRAM;
|
||||
|
||||
string signame, memfilename, bootmemfilename, pathname;
|
||||
string signame, memfilename, bootmemfilename, uartoutfilename, pathname, rmCmd;
|
||||
integer begin_signature_addr, end_signature_addr, signature_size;
|
||||
|
||||
assign ResetThreshold = 3'd5;
|
||||
|
|
@ -248,8 +256,8 @@ module testbench;
|
|||
end
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
|
||||
else CurrState <= #1 NextState;
|
||||
if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET;
|
||||
else CurrState <= NextState;
|
||||
|
||||
// fsm next state logic
|
||||
always_comb begin
|
||||
|
|
@ -299,15 +307,38 @@ module testbench;
|
|||
// Find the test vector files and populate the PC to function label converter
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
logic [P.XLEN-1:0] testadr;
|
||||
assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
|
||||
assign end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
|
||||
assign signature_size = end_signature_addr - begin_signature_addr;
|
||||
always_comb begin
|
||||
begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
|
||||
end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
|
||||
signature_size = end_signature_addr - begin_signature_addr;
|
||||
end
|
||||
always @(posedge clk) begin
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Verify the test ran correctly by checking the memory against a known signature.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
if(TestBenchReset) test = 1;
|
||||
if (P.ZICSR_SUPPORTED & TEST == "coremark")
|
||||
if (dut.core.priv.priv.EcallFaultM) begin
|
||||
$display("Benchmark: coremark is done.");
|
||||
$stop;
|
||||
end
|
||||
if (P.ZICSR_SUPPORTED & dut.core.ifu.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.ieu.InstrValidM) begin
|
||||
$display("Program fetched illegal instruction 0x00000000 from address 0x00000000. Might be fault with no fault handler.");
|
||||
//$stop; // presently wally32/64priv tests trigger this for reasons not yet understood.
|
||||
end
|
||||
|
||||
// modifications 4/3/24 kunlin & harris to speed up Verilator
|
||||
// For some reason, Verilator runs ~100x slower when these SelectTest and Validate codes are in the posedge clk block
|
||||
//end // added
|
||||
//always @(posedge SelectTest) // added
|
||||
if(SelectTest) begin
|
||||
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
|
||||
else if(TEST == "buildroot") begin
|
||||
memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
|
||||
bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
|
||||
uartoutfilename = {"logs/", TEST, "_uart.out"};
|
||||
rmCmd = {"rm -f ", uartoutfilename};
|
||||
$system(rmCmd); // Delete existing UARToutfile
|
||||
end
|
||||
else memfilename = {pathname, tests[test], ".elf.memfile"};
|
||||
if (riscofTest) begin
|
||||
|
|
@ -325,20 +356,14 @@ module testbench;
|
|||
// and initialize them to zero (also initilaize them to zero at the start of the next test)
|
||||
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
|
||||
end
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Verify the test ran correctly by checking the memory against a known signature.
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
if(TestBenchReset) test = 1;
|
||||
if (TEST == "coremark")
|
||||
if (dut.core.priv.priv.EcallFaultM) begin
|
||||
$display("Benchmark: coremark is done.");
|
||||
$stop;
|
||||
end
|
||||
if (P.ZICSR_SUPPORTED & dut.core.ifu.PCM == 0 & dut.core.ifu.InstrM == 0 & dut.core.ieu.InstrValidM) begin
|
||||
$display("Program fetched illegal instruction 0x00000000 from address 0x00000000. Might be fault with no fault handler.");
|
||||
//$stop; // presently wally32/64priv tests trigger this for reasons not yet understood.
|
||||
end
|
||||
`ifdef VERILATOR // this macro is defined when verilator is used
|
||||
// Simulator Verilator has an issue that the validate logic below slows runtime 110x if it is
|
||||
// in the posedge clk block rather than a separate posedge Validate block.
|
||||
// Until it is fixed, provide a silly posedge Validate block to keep Verilator happy.
|
||||
// https://github.com/verilator/verilator/issues/4967
|
||||
end // restored
|
||||
always @(posedge Validate) // added
|
||||
`endif
|
||||
if(Validate) begin
|
||||
if (TEST == "embench") begin
|
||||
// Writes contents of begin_signature to .sim.output file
|
||||
|
|
@ -374,10 +399,17 @@ module testbench;
|
|||
if (test == tests.size()) begin
|
||||
if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
|
||||
else $display("FAIL: %d test programs had errors", totalerrors);
|
||||
$stop; // if this is changed to $finish, wally-batch.do does not go to the next step to run coverage
|
||||
`ifdef VERILATOR // this macro is defined when verilator is used
|
||||
$finish; // Simulator Verilator needs $finish to terminate simulation.
|
||||
`else
|
||||
$stop; // if this is changed to $finish for Questa, wally-batch.do does not go to the next step to run coverage, and wally.do terminates without allowing GUI debug
|
||||
`endif
|
||||
end
|
||||
end
|
||||
end
|
||||
`ifndef VERILATOR
|
||||
// Remove this when issue 4967 is resolved and the posedge Validate logic above is removed
|
||||
end
|
||||
`endif
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
|
@ -469,7 +501,7 @@ module testbench;
|
|||
assign SPIIn = 0;
|
||||
|
||||
if(P.EXT_MEM_SUPPORTED) begin
|
||||
ram_ahb #(.BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
|
||||
ram_ahb #(.P(P), .BASE(P.EXT_MEM_BASE), .RANGE(P.EXT_MEM_RANGE))
|
||||
ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELRam(HSELEXT),
|
||||
.HREADRam(HRDATAEXT), .HREADYRam(HREADYEXT), .HRESPRam(HRESPEXT), .HREADY, .HWSTRB);
|
||||
end else begin
|
||||
|
|
@ -538,8 +570,8 @@ module testbench;
|
|||
ramxdetector #(P.XLEN, P.LLEN) ramxdetector(clk, dut.core.lsu.MemRWM[1], dut.core.lsu.LSULoadAccessFaultM, dut.core.lsu.ReadDataM,
|
||||
dut.core.ifu.PCM, InstrM, dut.core.lsu.IEUAdrM, InstrMName);
|
||||
riscvassertions #(P) riscvassertions(); // check assertions for a legal configuration
|
||||
loggers #(P, TEST, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
|
||||
loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename);
|
||||
loggers #(P, PrintHPMCounters, I_CACHE_ADDR_LOGGER, D_CACHE_ADDR_LOGGER, BPRED_LOGGER)
|
||||
loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename, TEST);
|
||||
|
||||
// track the current function or global label
|
||||
if (DEBUG == 1 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : FunctionName
|
||||
|
|
@ -547,6 +579,16 @@ module testbench;
|
|||
.clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
|
||||
end
|
||||
|
||||
// Append UART output to file for tests
|
||||
always @(posedge clk) begin
|
||||
if (P.UART_SUPPORTED & TEST == "buildroot") begin
|
||||
if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin
|
||||
memFile = $fopen(uartoutfilename, "ab");
|
||||
$fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din);
|
||||
$fclose(memFile);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// Termination condition
|
||||
// terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed
|
||||
|
|
@ -556,7 +598,8 @@ module testbench;
|
|||
logic ecf; // remove this once we don't rely on old Imperas tests with Ecalls
|
||||
if (P.ZICSR_SUPPORTED) assign ecf = dut.core.priv.priv.EcallFaultM;
|
||||
else assign ecf = 0;
|
||||
assign TestComplete = ecf &
|
||||
always_comb begin
|
||||
TestComplete = ecf &
|
||||
(dut.core.ieu.dp.regf.rf[3] == 1 |
|
||||
(dut.core.ieu.dp.regf.we3 &
|
||||
dut.core.ieu.dp.regf.a3 == 3 &
|
||||
|
|
@ -564,15 +607,18 @@ module testbench;
|
|||
((InstrM == 32'h6f | InstrM == 32'hfc32a423 | InstrM == 32'hfc32a823) & dut.core.ieu.c.InstrValidM ) |
|
||||
((dut.core.lsu.IEUAdrM == ProgramAddrLabelArray["tohost"]) & InstrMName == "SW" );
|
||||
//assign DCacheFlushStart = TestComplete;
|
||||
end
|
||||
|
||||
DCacheFlushFSM #(P) DCacheFlushFSM(.clk(clk), .reset(reset), .start(DCacheFlushStart), .done(DCacheFlushDone));
|
||||
|
||||
if(P.ZICSR_SUPPORTED & INSTR_LIMIT != 0) begin
|
||||
if(P.ZICSR_SUPPORTED) begin
|
||||
logic [P.XLEN-1:0] Minstret;
|
||||
assign Minstret = testbench.dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
|
||||
always @(negedge clk) begin
|
||||
if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
|
||||
if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
|
||||
if (INSTR_LIMIT > 0) begin
|
||||
if((Minstret != 0) && (Minstret % 'd100000 == 0)) $display("Reached %d instructions", Minstret);
|
||||
if((Minstret == INSTR_LIMIT) & (INSTR_LIMIT!=0)) begin $stop; $stop; end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -756,6 +802,8 @@ end
|
|||
logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
|
||||
string signame;
|
||||
logic [P.XLEN-1:0] testadr, testadrNoBase;
|
||||
|
||||
//$display("Invoking CheckSignature %s %s %0t", pathname, TestName, $time);
|
||||
|
||||
// read .signature.output file and compare to check for errors
|
||||
if (riscofTest) signame = {pathname, TestName, "/ref/Reference-sail_c_simulator.signature"};
|
||||
|
|
|
|||
|
|
@ -23,15 +23,15 @@
|
|||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "config.vh"
|
||||
`include "tests-fp.vh"
|
||||
`include "tests_fp.vh"
|
||||
|
||||
import cvw::*;
|
||||
|
||||
module testbenchfp;
|
||||
module testbench_fp;
|
||||
// Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir
|
||||
// to run specific precisions (e.g., quad or all)
|
||||
parameter TEST="none";
|
||||
parameter TEST_SIZE="none";
|
||||
parameter string TEST="none";
|
||||
parameter string TEST_SIZE="all";
|
||||
|
||||
`include "parameter-defs.vh"
|
||||
|
||||
|
|
@ -85,7 +85,7 @@ module testbenchfp;
|
|||
logic [P.LOGCVTLEN-1:0] CvtShiftAmtE; // how much to shift by
|
||||
logic [P.DIVb:0] Quot;
|
||||
logic CvtResSubnormUfE;
|
||||
logic DivStart=0;
|
||||
logic DivStart;
|
||||
logic FDivBusyE;
|
||||
logic OldFDivBusyE;
|
||||
logic reset = 1'b0;
|
||||
|
|
@ -154,7 +154,7 @@ module testbenchfp;
|
|||
// $display("This simulation for TEST is %s", TEST);
|
||||
// $display("This simulation for TEST is of the operand size of %s", TEST_SIZE);
|
||||
|
||||
if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported
|
||||
if (P.Q_SUPPORTED & (TEST_SIZE == "QP" | TEST_SIZE == "all")) begin // if Quad percision is supported
|
||||
if (TEST === "cvtint" | TEST === "all") begin // if testing integer conversion
|
||||
// add the 128-bit cvtint tests to the to-be-tested list
|
||||
Tests = {Tests, f128rv32cvtint};
|
||||
|
|
@ -653,7 +653,7 @@ module testbenchfp;
|
|||
static string pp = `PATH;
|
||||
string testname;
|
||||
string tt0;
|
||||
tt0 = $psprintf("%s", Tests[TestNum]);
|
||||
tt0 = $sformatf("%s", Tests[TestNum]);
|
||||
testname = {pp, tt0};
|
||||
//$display("Here you are %s", testname);
|
||||
$display("\n\nRunning %s vectors ", Tests[TestNum]);
|
||||
|
|
@ -662,18 +662,20 @@ module testbenchfp;
|
|||
TestNum = 0;
|
||||
end
|
||||
|
||||
// set a the signals for all tests
|
||||
always_comb UnitVal = Unit[TestNum];
|
||||
always_comb FmtVal = Fmt[TestNum];
|
||||
always_comb OpCtrlVal = OpCtrl[OpCtrlNum];
|
||||
always_comb WriteIntVal = WriteInt[OpCtrlNum];
|
||||
always_comb FrmVal = Frm[FrmNum];
|
||||
// set the signals for all tests
|
||||
always_ff @(posedge clk) begin
|
||||
UnitVal = Unit[TestNum];
|
||||
FmtVal = Fmt[TestNum];
|
||||
OpCtrlVal = OpCtrl[OpCtrlNum];
|
||||
WriteIntVal = WriteInt[OpCtrlNum];
|
||||
FrmVal = Frm[FrmNum];
|
||||
end
|
||||
|
||||
// modify the format signal if only 2 percisions supported
|
||||
// - 1 for the larger precision
|
||||
// - 0 for the smaller precision
|
||||
always_comb begin
|
||||
if (P.FMTBITS == 1) ModFmt = FmtVal == P.FMT;
|
||||
if (P.FMTBITS == 1) ModFmt = {1'b0, FmtVal == P.FMT};
|
||||
else ModFmt = FmtVal;
|
||||
end
|
||||
|
||||
|
|
@ -819,8 +821,8 @@ module testbenchfp;
|
|||
case (UnitVal)
|
||||
`FMAUNIT: Res = FpRes;
|
||||
`DIVUNIT: Res = FpRes;
|
||||
`CMPUNIT: Res = CmpRes;
|
||||
`CVTINTUNIT: if (WriteIntVal) Res = IntRes; else Res = FpRes;
|
||||
`CMPUNIT: Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, CmpRes};
|
||||
`CVTINTUNIT: if (WriteIntVal) Res = {{(FLEN > XLEN ? FLEN-XLEN : XLEN-FLEN){1'b0}}, IntRes}; else Res = FpRes;
|
||||
`CVTFPUNIT: Res = FpRes;
|
||||
endcase
|
||||
|
||||
|
|
@ -859,6 +861,10 @@ module testbenchfp;
|
|||
DivStart = 1'b0;
|
||||
nextstate = S0;
|
||||
end
|
||||
default: begin
|
||||
DivStart = 1'b0;
|
||||
nextstate = S0;
|
||||
end
|
||||
endcase // case (state)
|
||||
|
||||
end
|
||||
|
|
@ -1149,22 +1155,22 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
|||
2'b11: begin // quad
|
||||
X = TestVector[12+2*(P.Q_LEN)-1:12+(P.Q_LEN)];
|
||||
Y = TestVector[12+(P.Q_LEN)-1:12];
|
||||
Ans = TestVector[8];
|
||||
Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+2*(P.D_LEN)-1:12+(P.D_LEN)]};
|
||||
Y = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[12+(P.D_LEN)-1:12]};
|
||||
Ans = TestVector[8];
|
||||
Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
|
||||
end
|
||||
2'b00: if (P.S_SUPPORTED) begin // single
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+2*(P.S_LEN)-1:12+(P.S_LEN)]};
|
||||
Y = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[12+(P.S_LEN)-1:12]};
|
||||
Ans = TestVector[8];
|
||||
Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
|
||||
end
|
||||
2'b10: begin // half
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+2*(P.H_LEN)-1:12+(P.H_LEN)]};
|
||||
Y = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[12+(P.H_LEN)-1:12]};
|
||||
Ans = TestVector[8];
|
||||
Ans = {{P.FLEN-1{1'b0}}, TestVector[8]};
|
||||
end
|
||||
endcase
|
||||
`CVTFPUNIT:
|
||||
|
|
@ -1254,7 +1260,7 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
|||
case (Fmt)
|
||||
2'b11: begin // quad
|
||||
// {is the integer a long, is the opperation to an integer}
|
||||
casex ({OpCtrl[2:1]})
|
||||
casez ({OpCtrl[2:1]})
|
||||
2'b11: begin // long -> quad
|
||||
X = {P.FLEN{1'bx}};
|
||||
SrcA = TestVector[8+P.Q_LEN+P.XLEN-1:8+(P.Q_LEN)];
|
||||
|
|
@ -1269,18 +1275,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
|||
2'b01: begin // quad -> long
|
||||
X = {TestVector[8+P.XLEN+P.Q_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {TestVector[8+(P.XLEN-1):8]};
|
||||
Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
|
||||
end
|
||||
2'b00: begin // quad -> int
|
||||
X = {TestVector[8+32+P.Q_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b01: if (P.D_SUPPORTED) begin // double
|
||||
// {Int->Fp?, is the integer a long}
|
||||
casex ({OpCtrl[2:1]})
|
||||
casez ({OpCtrl[2:1]})
|
||||
2'b11: begin // long -> double
|
||||
X = {P.FLEN{1'bx}};
|
||||
SrcA = TestVector[8+P.D_LEN+P.XLEN-1:8+(P.D_LEN)];
|
||||
|
|
@ -1295,18 +1301,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
|||
2'b01: begin // double -> long
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+P.XLEN+P.D_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {TestVector[8+(P.XLEN-1):8]};
|
||||
Ans = {{(P.FLEN-64){1'b0}}, TestVector[8+(P.XLEN-1):8]};
|
||||
end
|
||||
2'b00: begin // double -> int
|
||||
X = {{P.FLEN-P.D_LEN{1'b1}}, TestVector[8+32+P.D_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b00: if (P.S_SUPPORTED) begin // single
|
||||
// {is the integer a long, is the opperation to an integer}
|
||||
casex ({OpCtrl[2:1]})
|
||||
casez ({OpCtrl[2:1]})
|
||||
2'b11: begin // long -> single
|
||||
X = {P.FLEN{1'bx}};
|
||||
SrcA = TestVector[8+P.S_LEN+P.XLEN-1:8+(P.S_LEN)];
|
||||
|
|
@ -1321,18 +1327,18 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
|||
2'b01: begin // single -> long
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+P.XLEN+P.S_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {TestVector[8+(P.XLEN-1):8]};
|
||||
Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
|
||||
end
|
||||
2'b00: begin // single -> int
|
||||
X = {{P.FLEN-P.S_LEN{1'b1}}, TestVector[8+32+P.S_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.XLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
Ans = {{P.FLEN-32{TestVector[8+32-1]}},TestVector[8+(32-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
2'b10: begin // half
|
||||
// {is the integer a long, is the opperation to an integer}
|
||||
casex ({OpCtrl[2:1]})
|
||||
casez ({OpCtrl[2:1]})
|
||||
2'b11: begin // long -> half
|
||||
X = {P.FLEN{1'bx}};
|
||||
SrcA = TestVector[8+P.H_LEN+P.XLEN-1:8+(P.H_LEN)];
|
||||
|
|
@ -1347,12 +1353,12 @@ module readvectors import cvw::*; #(parameter cvw_t P) (
|
|||
2'b01: begin // half -> long
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+P.XLEN+P.H_LEN-1:8+(P.XLEN)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {TestVector[8+(P.XLEN-1):8]};
|
||||
Ans = {{(P.FLEN > 64 ? P.FLEN-64 : 0){1'b0}}, TestVector[8+(P.XLEN-1):8]};
|
||||
end
|
||||
2'b00: begin // half -> int
|
||||
X = {{P.FLEN-P.H_LEN{1'b1}}, TestVector[8+32+P.H_LEN-1:8+(32)]};
|
||||
SrcA = {P.XLEN{1'bx}};
|
||||
Ans = {{P.XLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
|
||||
Ans = {{P.FLEN-32{TestVector[8+32-1]}}, TestVector[8+(32-1):8]};
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
|
@ -35,12 +35,12 @@
|
|||
|
||||
string tvpaths[] = '{
|
||||
"$RISCV/imperas-riscv-tests/work/",
|
||||
"../tests/riscof/work/riscv-arch-test/",
|
||||
"../tests/riscof/work/wally-riscv-arch-test/",
|
||||
"../benchmarks/coremark/work/",
|
||||
"../addins/embench-iot/",
|
||||
"../tests/custom/work/",
|
||||
"../tests/coverage/"
|
||||
"../../tests/riscof/work/riscv-arch-test/",
|
||||
"../../tests/riscof/work/wally-riscv-arch-test/",
|
||||
"../../benchmarks/coremark/work/",
|
||||
"../../addins/embench-iot/",
|
||||
"../../tests/custom/work/",
|
||||
"../../tests/coverage/"
|
||||
};
|
||||
|
||||
string coverage64gc[] = '{
|
||||
|
|
@ -1209,8 +1209,7 @@ string imperas32f[] = '{
|
|||
};
|
||||
|
||||
string arch64zfh_fma[] = '{
|
||||
//`RISCVARCHTEST,
|
||||
`WALLYTEST,
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/Zfh/src/fmadd_b15-01.S",
|
||||
"rv64i_m/Zfh/src/fmsub_b15-01.S",
|
||||
"rv64i_m/Zfh/src/fnmadd_b15-01.S",
|
||||
|
|
@ -1368,8 +1367,7 @@ string imperas32f[] = '{
|
|||
};
|
||||
|
||||
string arch64zfh_divsqrt[] = '{
|
||||
//`RISCVARCHTEST,
|
||||
`WALLYTEST,
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/Zfh/src/fdiv_b20-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b2-01.S",
|
||||
|
|
@ -1393,8 +1391,7 @@ string imperas32f[] = '{
|
|||
};
|
||||
|
||||
string arch64zfh[] = '{
|
||||
//`RISCVARCHTEST,
|
||||
`WALLYTEST,
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/Zfh/src/fadd_b10-01.S",
|
||||
"rv64i_m/Zfh/src/fadd_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fadd_b11-01.S",
|
||||
|
|
@ -1425,10 +1422,10 @@ string imperas32f[] = '{
|
|||
"rv64i_m/Zfh/src/fcvt.wu.h_b27-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.wu.h_b28-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.wu.h_b29-01.S",
|
||||
// "rv64i_m/Zfh/src/fcvt.h.l_b25-01.S", // tests commented out because they involve a fsd that hangs on vsim -c -do "do wally-batch.do fh_rv64gc arch64zfh" which lacks fsd support
|
||||
// "rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
|
||||
// "rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
|
||||
// "rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.h.l_b25-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.l.h_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.l.h_b22-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.l.h_b23-01.S",
|
||||
|
|
@ -2059,8 +2056,7 @@ string arch64zknh[] = '{
|
|||
};
|
||||
|
||||
string arch32zfh_divsqrt[] = '{
|
||||
//`RISCVARCHTEST,
|
||||
`WALLYTEST,
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/Zfh/src/fdiv_b20-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b2-01.S",
|
||||
|
|
@ -2084,8 +2080,7 @@ string arch64zknh[] = '{
|
|||
};
|
||||
|
||||
string arch32zfh[] = '{
|
||||
//`RISCVARCHTEST,
|
||||
`WALLYTEST,
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/Zfh/src/fadd_b10-01.S",
|
||||
"rv32i_m/Zfh/src/fadd_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fadd_b11-01.S",
|
||||
|
|
@ -2310,8 +2305,7 @@ string arch64zknh[] = '{
|
|||
};
|
||||
|
||||
string arch32zfh_fma[] = '{
|
||||
//`RISCVARCHTEST,
|
||||
`WALLYTEST,
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/Zfh/src/fmadd_b15-01.S",
|
||||
"rv32i_m/Zfh/src/fmsub_b15-01.S",
|
||||
"rv32i_m/Zfh/src/fnmadd_b15-01.S",
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
///////////////////////////////////////////
|
||||
// tests0fo.vh
|
||||
// tests_fp.vh
|
||||
//
|
||||
// Written: Katherine Parry 2022
|
||||
// Modified:
|
||||
|
|
@ -24,7 +24,7 @@
|
|||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`define PATH "../tests/fp/vectors/"
|
||||
`define PATH "../../tests/fp/vectors/"
|
||||
`define ADD_OPCTRL 3'b110
|
||||
`define MUL_OPCTRL 3'b100
|
||||
`define SUB_OPCTRL 3'b111
|
||||
19
tests/custom/lpddrtest/Makefile
Normal file
19
tests/custom/lpddrtest/Makefile
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
TARGETDIR := lpddr_test
|
||||
TARGET := $(TARGETDIR)/$(TARGETDIR).elf
|
||||
ROOT := ..
|
||||
LIBRARY_DIRS := ${ROOT}/crt0
|
||||
LIBRARY_FILES := crt0
|
||||
|
||||
MARCH :=-march=rv64imfdczicbom
|
||||
MABI :=-mabi=lp64d
|
||||
LINKER := ${ROOT}/linker8000-0000.x
|
||||
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
|
||||
|
||||
CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align -O2
|
||||
CC=riscv64-unknown-elf-gcc
|
||||
DA=riscv64-unknown-elf-objdump -d
|
||||
|
||||
|
||||
include $(ROOT)/makefile.inc
|
||||
|
||||
|
||||
5
tests/custom/lpddrtest/header.h
Normal file
5
tests/custom/lpddrtest/header.h
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
#ifndef __header
|
||||
#define __header
|
||||
|
||||
void lpddr_test();
|
||||
#endif
|
||||
29
tests/custom/lpddrtest/lpddr_test.s
Normal file
29
tests/custom/lpddrtest/lpddr_test.s
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
.section .text
|
||||
.globl lpddr_test
|
||||
.type lpddr_test, @function
|
||||
lpddr_test:
|
||||
li t1, 0x90000000
|
||||
addi t5, t1, 0
|
||||
li t2, 0xAABBCCDD00112233
|
||||
|
||||
li t3, 10
|
||||
li t4, 0
|
||||
loop_write:
|
||||
beq t4, t3, done_write
|
||||
sd t2, 0(t5)
|
||||
addi t5, t5, 8
|
||||
addi t4, t4, 1
|
||||
j loop_write
|
||||
done_write:
|
||||
|
||||
li t4, 0
|
||||
addi t5, t1, 0
|
||||
loop_read:
|
||||
beq t4, t3, done_read
|
||||
ld t6, 0(t5)
|
||||
addi t5, t5, 8
|
||||
addi t4, t4, 1
|
||||
j loop_read
|
||||
done_read:
|
||||
ret
|
||||
|
||||
6
tests/custom/lpddrtest/main.c
Normal file
6
tests/custom/lpddrtest/main.c
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
#include "header.h"
|
||||
|
||||
int main(){
|
||||
lpddr_test();
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -27,7 +27,7 @@ hart0:
|
|||
warl:
|
||||
dependency_fields: []
|
||||
legal:
|
||||
- extensions[25:0] bitmask [0x014112D, 0x0000000]
|
||||
- extensions[25:0] bitmask [0x015112D, 0x0000000]
|
||||
wr_illegal:
|
||||
- Unchanged
|
||||
|
||||
|
|
|
|||
207
tests/testgen/covergen.py
Executable file
207
tests/testgen/covergen.py
Executable file
|
|
@ -0,0 +1,207 @@
|
|||
#!/usr/bin/python3
|
||||
##################################
|
||||
# covergen.py
|
||||
#
|
||||
# David_Harris@hmc.edu 27 March 2024
|
||||
#
|
||||
# Generate directed tests for functional coverage
|
||||
##################################
|
||||
|
||||
##################################
|
||||
# libraries
|
||||
##################################
|
||||
from datetime import datetime
|
||||
from random import randint
|
||||
from random import seed
|
||||
from random import getrandbits
|
||||
|
||||
##################################
|
||||
# functions
|
||||
##################################
|
||||
|
||||
def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen):
|
||||
rdval = randint(0, 2**xlen-1)
|
||||
lines = "\n# Testcase " + str(desc) + "\n"
|
||||
lines = lines + "li x" + str(rd) + ", MASK_XLEN(" + formatstr.format(rdval) + ") # initialize rd to a random value that should get changed\n"
|
||||
lines = lines + "li x" + str(rs1) + ", MASK_XLEN(" + formatstr.format(rs1val) + ") # initialize rs1 to a random value \n"
|
||||
lines = lines + "li x" + str(rs2) + ", MASK_XLEN(" + formatstr.format(rs2val) + ") # initialize rs2 to a random value\n"
|
||||
lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", x" + str(rs2) + " # perform operation\n"
|
||||
f.write(lines)
|
||||
|
||||
def make_cp_rd(rd, test, storecmd, xlen):
|
||||
rs1 = randint(0, 31)
|
||||
rs2 = randint(0, 31)
|
||||
rs1val = randint(0, 2**xlen-1)
|
||||
rs2val = randint(0, 2**xlen-1)
|
||||
desc = "cp_rd (Test destination rd = x" + str(rd) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
|
||||
|
||||
def make_cp_rs1(rs1, test, storecmd, xlen):
|
||||
rd = randint(0, 31)
|
||||
rs2 = randint(0, 31)
|
||||
rs1val = randint(0, 2**xlen-1)
|
||||
rs2val = randint(0, 2**xlen-1)
|
||||
desc = "cp_rs1 (Test source rs1 = x" + str(rs1) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
|
||||
|
||||
def make_cp_rs2(rs2, test, storecmd, xlen):
|
||||
rd = randint(0, 31)
|
||||
rs1 = randint(0, 31)
|
||||
rs1val = randint(0, 2**xlen-1)
|
||||
rs2val = randint(0, 2**xlen-1)
|
||||
desc = "cp_rs2 (Test source rs2 = x" + str(rs2) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
|
||||
|
||||
def make_cmp_rd_rs1(r, test, storecmd, xlen):
|
||||
rd = r
|
||||
rs1 = r
|
||||
rs2 = randint(0, 31)
|
||||
rs1val = randint(0, 2**xlen-1)
|
||||
rs2val = randint(0, 2**xlen-1)
|
||||
desc = "cmp_rd_rs1 (Test destination rd = source rs1 = x" + str(r) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
|
||||
|
||||
def make_cmp_rd_rs2(r, test, storecmd, xlen):
|
||||
rd = r
|
||||
rs1 = randint(0, 31)
|
||||
rs2 = r
|
||||
rs1val = randint(0, 2**xlen-1)
|
||||
rs2val = randint(0, 2**xlen-1)
|
||||
desc = "cmp_rd_rs2 (Test destination rd = source rs2 = x" + str(r) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
|
||||
|
||||
def make_cmp_rd_rs1_rs2(r, test, storecmd, xlen):
|
||||
rd = r
|
||||
rs1 = r
|
||||
rs2 = r
|
||||
rs1val = randint(0, 2**xlen-1)
|
||||
rs2val = randint(0, 2**xlen-1)
|
||||
desc = "cmp_rd_rs1_rs2 (Test destination rd = source rs1 = source rs2 = x" + str(r) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
|
||||
|
||||
def make_cp_gpr_hazard(test, storecmd, xlen):
|
||||
rs1val = randint(0, 2**xlen-1)
|
||||
rs2val = randint(0, 2**xlen-1)
|
||||
desc = "cp_gpr_hazard"
|
||||
writeCovVector(desc, 20, 21, 22, rs1val, rs2val, test, storecmd, xlen)
|
||||
lines = test + " x23, x22, x20 # RAW\n"
|
||||
lines = lines + test + " x22, x23, x20 # WAR\n"
|
||||
lines = lines + test + " x22, x21, x20 # WAW\n"
|
||||
f.write(lines)
|
||||
|
||||
def make_cp_rs1_maxvals(test, storecmd, xlen):
|
||||
for rs1val in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
|
||||
rd = randint(1, 31)
|
||||
rs1 = randint(0, 31)
|
||||
rs2 = randint(0, 31)
|
||||
rs2val = randint(0, 2**xlen-1)
|
||||
desc = "cp_rs1_maxvals (rs1 = " + str(rs1val) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
|
||||
|
||||
def make_cp_rs2_maxvals(test, storecmd, xlen):
|
||||
for rs2val in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
|
||||
rd = randint(1, 31)
|
||||
rs1 = randint(0, 31)
|
||||
rs2 = randint(0, 31)
|
||||
rs1val = randint(0, 2**xlen-1)
|
||||
desc = "cp_rs2_maxvals (rs2 = " + str(rs2val) + ")"
|
||||
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
|
||||
|
||||
|
||||
def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen):
|
||||
rdval = randint(0, 2**xlen-1)
|
||||
lines = "\n# Testcase " + str(desc) + "\n"
|
||||
lines = lines + "li x" + str(rd) + ", MASK_XLEN(" + formatstr.format(rdval) + ") # initialize rd to a random value that should get changed\n"
|
||||
lines = lines + "li x" + str(rs1) + ", MASK_XLEN(" + formatstr.format(rs1val) + ") # initialize rs1 to a random value \n"
|
||||
lines = lines + "li x" + str(rs2) + ", MASK_XLEN(" + formatstr.format(rs2val) + ") # initialize rs2 to a random value\n"
|
||||
lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", x" + str(rs2) + " # perform operation\n"
|
||||
f.write(lines)
|
||||
|
||||
|
||||
def write_rtype_arith_vectors(test, storecmd, xlen):
|
||||
for r in range(32):
|
||||
make_cp_rd(r, test, storecmd, xlen)
|
||||
for r in range(32):
|
||||
make_cp_rs1(r, test, storecmd, xlen)
|
||||
for r in range(32):
|
||||
make_cp_rs2(r, test, storecmd, xlen)
|
||||
for r in range(32):
|
||||
make_cmp_rd_rs2(r, test, storecmd, xlen)
|
||||
for r in range(32):
|
||||
make_cmp_rd_rs1(r, test, storecmd, xlen)
|
||||
for r in range(32):
|
||||
make_cmp_rd_rs1_rs2(r, test, storecmd, xlen)
|
||||
make_cp_gpr_hazard(test, storecmd, xlen)
|
||||
make_cp_rs1_maxvals(test, storecmd, xlen)
|
||||
make_cp_rs2_maxvals(test, storecmd, xlen)
|
||||
|
||||
##################################
|
||||
# main body
|
||||
##################################
|
||||
|
||||
# change these to suite your tests
|
||||
rtests = ["ADD", "SUB", "SLT", "SLTU", "XOR"]
|
||||
tests = rtests
|
||||
author = "David_Harris@hmc.edu"
|
||||
xlens = [64]
|
||||
numrand = 3
|
||||
|
||||
# setup
|
||||
seed(0) # make tests reproducible
|
||||
|
||||
# generate files for each test
|
||||
for xlen in xlens:
|
||||
formatstrlen = str(int(xlen/4))
|
||||
formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
|
||||
formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
|
||||
if (xlen == 32):
|
||||
storecmd = "sw"
|
||||
wordsize = 4
|
||||
else:
|
||||
storecmd = "sd"
|
||||
wordsize = 8
|
||||
for test in tests:
|
||||
# corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1,
|
||||
# 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
|
||||
corners = [0, 1, 2**(xlen)-1]
|
||||
pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
|
||||
basename = "WALLY-COV-" + test
|
||||
fname = pathname + "src/" + basename + ".S"
|
||||
|
||||
# print custom header part
|
||||
f = open(fname, "w")
|
||||
line = "///////////////////////////////////////////\n"
|
||||
f.write(line)
|
||||
lines="// "+fname+ "\n// " + author + "\n"
|
||||
f.write(lines)
|
||||
line ="// Created " + str(datetime.now())
|
||||
f.write(line)
|
||||
|
||||
# insert generic header
|
||||
h = open("covergen_header.S", "r")
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
# print directed and random test vectors
|
||||
# Coverage for R-type arithmetic instructions
|
||||
if (test not in rtests):
|
||||
exit("Error: %s not implemented yet" % test)
|
||||
else:
|
||||
write_rtype_arith_vectors(test, storecmd, xlen)
|
||||
|
||||
# print footer
|
||||
line = "\n.EQU NUMTESTS," + str(1) + "\n\n"
|
||||
f.write(line)
|
||||
h = open("covergen_footer.S", "r")
|
||||
for line in h:
|
||||
f.write(line)
|
||||
|
||||
# Finish
|
||||
# lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
|
||||
# lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
|
||||
f.write(lines)
|
||||
f.close()
|
||||
|
||||
|
||||
|
||||
|
||||
30
tests/testgen/covergen_footer.S
Normal file
30
tests/testgen/covergen_footer.S
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0x98765432
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
|
||||
|
||||
wally_signature:
|
||||
.fill NUMTESTS*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*(XLEN/32),4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
RVMODEL_DATA_END
|
||||
18
tests/testgen/covergen_header.S
Normal file
18
tests/testgen/covergen_header.S
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
//
|
||||
// Copyright (C) 2024 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV64I")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",temp)
|
||||
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
// Copyright (C) 2024 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
///////////////////////////////////////////
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1,413 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Sat May 6 11:38:58 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fadd_b10 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fadd_b10)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f31; op2:f31; dest:f31; op1val:0x52ee; op2val:0x52ee;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f29, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0a and fm2 == 0x262 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f29; op2:f28; dest:f30; op1val:0x52ee; op2val:0x2a62;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f30, f29, f28, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3fb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f29; op1val:0x52ee; op2val:0x37fb;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f29, f30, f29, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f28; op2:f30; dest:f28; op1val:0x52ee; op2val:0x44fd;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f28, f28, f30, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x14 and fm2 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f26; op2:f26; dest:f27; op1val:0x52ee; op2val:0x52ee;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f27, f26, f26, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3cb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f27; op2:f25; dest:f26; op1val:0x52ee; op2val:0x5fcb;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f26, f27, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f24, rs2==f27, rd==f25,
|
||||
/* opcode: fadd.h ; op1:f24; op2:f27; dest:f25; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f25, f24, f27, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f25, rs2==f23, rd==f24,
|
||||
/* opcode: fadd.h ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f24, f25, f23, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f22, rs2==f24, rd==f23,
|
||||
/* opcode: fadd.h ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f23, f22, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f23, rs2==f21, rd==f22,
|
||||
/* opcode: fadd.h ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f22, f23, f21, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f20, rs2==f22, rd==f21,
|
||||
/* opcode: fadd.h ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f21, rs2==f19, rd==f20,
|
||||
/* opcode: fadd.h ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f20, f21, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f18, rs2==f20, rd==f19,
|
||||
/* opcode: fadd.h ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f19, f18, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f19, rs2==f17, rd==f18,
|
||||
/* opcode: fadd.h ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f18, f19, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f16, rs2==f18, rd==f17,
|
||||
/* opcode: fadd.h ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f17, f16, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f17, rs2==f15, rd==f16,
|
||||
/* opcode: fadd.h ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f16, f17, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f14, rs2==f16, rd==f15,
|
||||
/* opcode: fadd.h ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f15, f14, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f15, rs2==f13, rd==f14,
|
||||
/* opcode: fadd.h ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f14, f15, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f12, rs2==f14, rd==f13,
|
||||
/* opcode: fadd.h ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f13, f12, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f13, rs2==f11, rd==f12,
|
||||
/* opcode: fadd.h ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f12, f13, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f10, rs2==f12, rd==f11,
|
||||
/* opcode: fadd.h ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f11, f10, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f11, rs2==f9, rd==f10,
|
||||
/* opcode: fadd.h ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f10, f11, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f8, rs2==f10, rd==f9,
|
||||
/* opcode: fadd.h ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f9, f8, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f9, rs2==f7, rd==f8,
|
||||
/* opcode: fadd.h ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f8, f9, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:// rs1==f6, rs2==f8, rd==f7,
|
||||
/* opcode: fadd.h ; op1:f6; op2:f8; dest:f7; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f7, f6, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:// rs1==f7, rs2==f5, rd==f6,
|
||||
/* opcode: fadd.h ; op1:f7; op2:f5; dest:f6; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f6, f7, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:// rs1==f4, rs2==f6, rd==f5,
|
||||
/* opcode: fadd.h ; op1:f4; op2:f6; dest:f5; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f5, f4, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:// rs1==f5, rs2==f3, rd==f4,
|
||||
/* opcode: fadd.h ; op1:f5; op2:f3; dest:f4; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f4, f5, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:// rs1==f2, rs2==f4, rd==f3,
|
||||
/* opcode: fadd.h ; op1:f2; op2:f4; dest:f3; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f3, f2, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:// rs1==f3, rs2==f1, rd==f2,
|
||||
/* opcode: fadd.h ; op1:f3; op2:f1; dest:f2; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f2, f3, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:// rs1==f0, rs2==f2, rd==f1,
|
||||
/* opcode: fadd.h ; op1:f0; op2:f2; dest:f1; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f1, f0, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:// rs1==f1,
|
||||
/* opcode: fadd.h ; op1:f1; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f1, f30, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:// rs2==f0,
|
||||
/* opcode: fadd.h ; op1:f30; op2:f0; dest:f31; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f0, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:// rd==f0,
|
||||
/* opcode: fadd.h ; op1:f31; op2:f30; dest:f0; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f0, f31, f30, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_34:// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x52ee; op2val:0x53;
|
||||
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_35:// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x14 and fm2 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x52ee; op2val:0x523c;
|
||||
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(10850,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(14331,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(17661,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(24523,16,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(83,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(21052,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 72*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,548 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Sat May 6 11:38:58 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fadd_b12 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fadd_b12)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 1 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f31; op2:f31; dest:f31; op1val:0xfac0; op2val:0xfac0;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f29, rs2==f28, rd==f30,fs1 == 1 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f29; op2:f28; dest:f30; op1val:0xf6b9; op2val:0x796e;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f30, f29, f28, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 1 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f29; op1val:0xf816; op2val:0x7b53;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f29, f30, f29, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 1 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f28; op2:f30; dest:f28; op1val:0xfa44; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f28, f28, f30, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 1 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f26; op2:f26; dest:f27; op1val:0xf79f; op2val:0xf79f;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f27, f26, f26, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f27, rs2==f25, rd==f26,fs1 == 1 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f27; op2:f25; dest:f26; op1val:0xfb42; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f26, f27, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f24, rs2==f27, rd==f25,fs1 == 1 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f24; op2:f27; dest:f25; op1val:0xf481; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f25, f24, f27, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f25, rs2==f23, rd==f24,fs1 == 1 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f2 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f25; op2:f23; dest:f24; op1val:0xf8f1; op2val:0x7af2;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f24, f25, f23, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f22, rs2==f24, rd==f23,fs1 == 1 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f22; op2:f24; dest:f23; op1val:0xfb46; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f23, f22, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f23, rs2==f21, rd==f22,fs1 == 1 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f23; op2:f21; dest:f22; op1val:0xfa7a; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f22, f23, f21, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f20, rs2==f22, rd==f21,fs1 == 1 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f20; op2:f22; dest:f21; op1val:0xf4f5; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f21, rs2==f19, rd==f20,fs1 == 1 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f21; op2:f19; dest:f20; op1val:0xfb2f; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f20, f21, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f18, rs2==f20, rd==f19,fs1 == 1 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x094 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f18; op2:f20; dest:f19; op1val:0xf78c; op2val:0x7894;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f19, f18, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f19, rs2==f17, rd==f18,fs1 == 1 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f19; op2:f17; dest:f18; op1val:0xf6f1; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f18, f19, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f16, rs2==f18, rd==f17,fs1 == 1 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f16; op2:f18; dest:f17; op1val:0xfb4c; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f17, f16, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f17, rs2==f15, rd==f16,fs1 == 1 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f17; op2:f15; dest:f16; op1val:0xf7a0; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f16, f17, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f14, rs2==f16, rd==f15,fs1 == 1 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f14; op2:f16; dest:f15; op1val:0xf42a; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f15, f14, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f15, rs2==f13, rd==f14,fs1 == 1 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f15; op2:f13; dest:f14; op1val:0xf863; op2val:0x787f;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f14, f15, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f12, rs2==f14, rd==f13,fs1 == 1 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f12; op2:f14; dest:f13; op1val:0xf9c1; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f13, f12, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f13, rs2==f11, rd==f12,fs1 == 1 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f13; op2:f11; dest:f12; op1val:0xfa98; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f12, f13, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f10, rs2==f12, rd==f11,fs1 == 1 and fe1 == 0x15 and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f10; op2:f12; dest:f11; op1val:0xd4ad; op2val:0x77e9;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f11, f10, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f11, rs2==f9, rd==f10,fs1 == 1 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f11; op2:f9; dest:f10; op1val:0xfaef; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f10, f11, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f8, rs2==f10, rd==f9,fs1 == 1 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f8; op2:f10; dest:f9; op1val:0xf533; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f9, f8, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f9, rs2==f7, rd==f8,fs1 == 1 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x210 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f9; op2:f7; dest:f8; op1val:0xf21c; op2val:0x7a10;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f8, f9, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f6; op2:f8; dest:f7; op1val:0xf3a1; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f7, f6, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:// rs1==f7, rs2==f5, rd==f6,fs1 == 1 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f7; op2:f5; dest:f6; op1val:0xfa6c; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f6, f7, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f4; op2:f6; dest:f5; op1val:0xed25; op2val:0x7667;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f5, f4, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:// rs1==f5, rs2==f3, rd==f4,fs1 == 1 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f5; op2:f3; dest:f4; op1val:0xf80f; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f4, f5, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x1b and fm1 == 0x2f9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x147 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f2; op2:f4; dest:f3; op1val:0xeef9; op2val:0x7947;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f3, f2, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f3; op2:f1; dest:f2; op1val:0xf9a6; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f2, f3, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f0; op2:f2; dest:f1; op1val:0xfa83; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f1, f0, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:// rs1==f1,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f1; op2:f30; dest:f31; op1val:0xfbb4; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f1, f30, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f0; dest:f31; op1val:0xf8b2; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f0, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:// rd==f0,fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f31; op2:f30; dest:f0; op1val:0xf8c4; op2val:0x7bd8;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f0, f31, f30, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_34:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf89a; op2val:0x7aec;
|
||||
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_35:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x203 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf20e; op2val:0x7603;
|
||||
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_36:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf8e6; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_37:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x087 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf79e; op2val:0x7887;
|
||||
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_38:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfa0e; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_39:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfb62; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_40:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfb2e; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_41:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x373 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf852; op2val:0x7b73;
|
||||
valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_42:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf9a3; op2val:0x7bd7;
|
||||
valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_43:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfa7d; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_44:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfb28; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_45:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfb98; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_46:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf734; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_47:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfbf7; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_48:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfa57; op2val:0x7b00;
|
||||
valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_49:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfac0; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_50:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf79f; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(64192,16,FLEN)
|
||||
NAN_BOXED(64192,16,FLEN)
|
||||
NAN_BOXED(63161,16,FLEN)
|
||||
NAN_BOXED(31086,16,FLEN)
|
||||
NAN_BOXED(63510,16,FLEN)
|
||||
NAN_BOXED(31571,16,FLEN)
|
||||
NAN_BOXED(64068,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63391,16,FLEN)
|
||||
NAN_BOXED(63391,16,FLEN)
|
||||
NAN_BOXED(64322,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(62593,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63729,16,FLEN)
|
||||
NAN_BOXED(31474,16,FLEN)
|
||||
NAN_BOXED(64326,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64122,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(62709,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64303,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63372,16,FLEN)
|
||||
NAN_BOXED(30868,16,FLEN)
|
||||
NAN_BOXED(63217,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64332,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63392,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(62506,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63587,16,FLEN)
|
||||
NAN_BOXED(30847,16,FLEN)
|
||||
NAN_BOXED(63937,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64152,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(54445,16,FLEN)
|
||||
NAN_BOXED(30697,16,FLEN)
|
||||
NAN_BOXED(64239,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(62771,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(61980,16,FLEN)
|
||||
NAN_BOXED(31248,16,FLEN)
|
||||
NAN_BOXED(62369,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64108,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(60709,16,FLEN)
|
||||
NAN_BOXED(30311,16,FLEN)
|
||||
NAN_BOXED(63503,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(61177,16,FLEN)
|
||||
NAN_BOXED(31047,16,FLEN)
|
||||
NAN_BOXED(63910,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64131,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64436,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63666,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63684,16,FLEN)
|
||||
NAN_BOXED(31704,16,FLEN)
|
||||
NAN_BOXED(63642,16,FLEN)
|
||||
NAN_BOXED(31468,16,FLEN)
|
||||
NAN_BOXED(61966,16,FLEN)
|
||||
NAN_BOXED(30211,16,FLEN)
|
||||
NAN_BOXED(63718,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63390,16,FLEN)
|
||||
NAN_BOXED(30855,16,FLEN)
|
||||
NAN_BOXED(64014,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64354,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64302,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63570,16,FLEN)
|
||||
NAN_BOXED(31603,16,FLEN)
|
||||
NAN_BOXED(63907,16,FLEN)
|
||||
NAN_BOXED(31703,16,FLEN)
|
||||
NAN_BOXED(64125,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64296,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64408,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63284,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64503,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64087,16,FLEN)
|
||||
NAN_BOXED(31488,16,FLEN)
|
||||
NAN_BOXED(64192,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63391,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 102*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,602 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Sat May 6 11:38:58 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fadd_b7 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fadd_b7)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f31; op2:f31; dest:f31; op1val:0x7ac0; op2val:0x7ac0;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f31, f31, dyn, 96, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f29, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f29; op2:f28; dest:f30; op1val:0x76b9; op2val:0xf6b9;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f30, f29, f28, dyn, 96, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f29; op1val:0x7816; op2val:0xf816;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f29, f30, f29, dyn, 96, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f28; op2:f30; dest:f28; op1val:0x7a44; op2val:0xfa44;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f28, f28, f30, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f26; op2:f26; dest:f27; op1val:0x779f; op2val:0x779f;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f27, f26, f26, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f27; op2:f25; dest:f26; op1val:0x7b42; op2val:0xfb42;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f26, f27, f25, dyn, 96, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f24; op2:f27; dest:f25; op1val:0x7481; op2val:0xf481;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f25, f24, f27, dyn, 96, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f25; op2:f23; dest:f24; op1val:0x78f1; op2val:0xf8f1;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f24, f25, f23, dyn, 96, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f22; op2:f24; dest:f23; op1val:0x7b46; op2val:0xfb46;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f23, f22, f24, dyn, 96, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f23; op2:f21; dest:f22; op1val:0x7a7a; op2val:0xfa7a;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f22, f23, f21, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f20; op2:f22; dest:f21; op1val:0x74f5; op2val:0xf4f5;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f21, f20, f22, dyn, 96, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f21; op2:f19; dest:f20; op1val:0x7b2f; op2val:0xfb2f;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f20, f21, f19, dyn, 96, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f18; op2:f20; dest:f19; op1val:0x778c; op2val:0xf78c;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f19, f18, f20, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f19; op2:f17; dest:f18; op1val:0x76f1; op2val:0xf6f1;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f18, f19, f17, dyn, 96, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f16; op2:f18; dest:f17; op1val:0x7b4c; op2val:0xfb4c;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f17, f16, f18, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f17; op2:f15; dest:f16; op1val:0x77a0; op2val:0xf7a0;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f16, f17, f15, dyn, 96, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f14; op2:f16; dest:f15; op1val:0x742a; op2val:0xf42a;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f15, f14, f16, dyn, 96, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f15; op2:f13; dest:f14; op1val:0x7863; op2val:0xf863;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f14, f15, f13, dyn, 96, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f12; op2:f14; dest:f13; op1val:0x79c1; op2val:0xf9c1;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f13, f12, f14, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f13; op2:f11; dest:f12; op1val:0x7a98; op2val:0xfa98;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f12, f13, f11, dyn, 96, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f10; op2:f12; dest:f11; op1val:0x54bd; op2val:0xd4bd;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f11, f10, f12, dyn, 96, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f11; op2:f9; dest:f10; op1val:0x7aef; op2val:0xfaef;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f10, f11, f9, dyn, 96, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f8; op2:f10; dest:f9; op1val:0x7533; op2val:0xf533;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f9, f8, f10, dyn, 96, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f9; op2:f7; dest:f8; op1val:0x721c; op2val:0xf21c;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f8, f9, f7, dyn, 96, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:// rs1==f6, rs2==f8, rd==f7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f6; op2:f8; dest:f7; op1val:0x73a1; op2val:0xf3a1;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f7, f6, f8, dyn, 96, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f7; op2:f5; dest:f6; op1val:0x7a6c; op2val:0xfa6c;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f6, f7, f5, dyn, 96, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:// rs1==f4, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f4; op2:f6; dest:f5; op1val:0x6d25; op2val:0xed25;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f5, f4, f6, dyn, 96, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f5; op2:f3; dest:f4; op1val:0x780f; op2val:0xf80f;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f4, f5, f3, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f2; op2:f4; dest:f3; op1val:0x6efa; op2val:0xeefa;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f3, f2, f4, dyn, 96, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:// rs1==f3, rs2==f1, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f3; op2:f1; dest:f2; op1val:0x79a6; op2val:0xf9a6;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f2, f3, f1, dyn, 96, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f0; op2:f2; dest:f1; op1val:0x7a83; op2val:0xfa83;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f1, f0, f2, dyn, 96, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:// rs1==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f1; op2:f30; dest:f31; op1val:0x7bb4; op2val:0xfbb4;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f1, f30, dyn, 96, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:// rs2==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f0; dest:f31; op1val:0x78b2; op2val:0xf8b2;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f0, dyn, 96, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:// rd==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f31; op2:f30; dest:f0; op1val:0x78c4; op2val:0xf8c4;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f0, f31, f30, dyn, 96, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x789a; op2val:0xf89a;
|
||||
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 68*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_35:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x720e; op2val:0xf20e;
|
||||
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 70*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x78e6; op2val:0xf8e6;
|
||||
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 72*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_37:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x779e; op2val:0xf79e;
|
||||
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 74*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a0e; op2val:0xfa0e;
|
||||
valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 76*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_39:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b62; op2val:0xfb62;
|
||||
valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 78*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b2e; op2val:0xfb2e;
|
||||
valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 80*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_41:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7852; op2val:0xf852;
|
||||
valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 82*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_42:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x79a3; op2val:0xf9a1;
|
||||
valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_43:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a7d; op2val:0xfa7b;
|
||||
valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 86*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x326 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b28; op2val:0xfb26;
|
||||
valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 88*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_45:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x396 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b98; op2val:0xfb96;
|
||||
valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 90*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_46:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x330 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7734; op2val:0xf730;
|
||||
valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 92*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_47:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f5 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7bf7; op2val:0xfbf5;
|
||||
valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 94*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_48:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x255 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a57; op2val:0xfa55;
|
||||
valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 96*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_49:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x109 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7909; op2val:0xf909;
|
||||
valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 98*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_50:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x73c6; op2val:0xf3c6;
|
||||
valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 100*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_51:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x37e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x6f7e; op2val:0xef7e;
|
||||
valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 102*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_52:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x25a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a5a; op2val:0xfa5a;
|
||||
valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 104*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_53:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x286 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a86; op2val:0xfa86;
|
||||
valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 106*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_54:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x70ae; op2val:0xf0ae;
|
||||
valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 108*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_55:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7ac0; op2val:0xfac0;
|
||||
valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 110*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_56:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x779f; op2val:0xf79f;
|
||||
valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 112*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(30393,16,FLEN)
|
||||
NAN_BOXED(63161,16,FLEN)
|
||||
NAN_BOXED(30742,16,FLEN)
|
||||
NAN_BOXED(63510,16,FLEN)
|
||||
NAN_BOXED(31300,16,FLEN)
|
||||
NAN_BOXED(64068,16,FLEN)
|
||||
NAN_BOXED(30623,16,FLEN)
|
||||
NAN_BOXED(30623,16,FLEN)
|
||||
NAN_BOXED(31554,16,FLEN)
|
||||
NAN_BOXED(64322,16,FLEN)
|
||||
NAN_BOXED(29825,16,FLEN)
|
||||
NAN_BOXED(62593,16,FLEN)
|
||||
NAN_BOXED(30961,16,FLEN)
|
||||
NAN_BOXED(63729,16,FLEN)
|
||||
NAN_BOXED(31558,16,FLEN)
|
||||
NAN_BOXED(64326,16,FLEN)
|
||||
NAN_BOXED(31354,16,FLEN)
|
||||
NAN_BOXED(64122,16,FLEN)
|
||||
NAN_BOXED(29941,16,FLEN)
|
||||
NAN_BOXED(62709,16,FLEN)
|
||||
NAN_BOXED(31535,16,FLEN)
|
||||
NAN_BOXED(64303,16,FLEN)
|
||||
NAN_BOXED(30604,16,FLEN)
|
||||
NAN_BOXED(63372,16,FLEN)
|
||||
NAN_BOXED(30449,16,FLEN)
|
||||
NAN_BOXED(63217,16,FLEN)
|
||||
NAN_BOXED(31564,16,FLEN)
|
||||
NAN_BOXED(64332,16,FLEN)
|
||||
NAN_BOXED(30624,16,FLEN)
|
||||
NAN_BOXED(63392,16,FLEN)
|
||||
NAN_BOXED(29738,16,FLEN)
|
||||
NAN_BOXED(62506,16,FLEN)
|
||||
NAN_BOXED(30819,16,FLEN)
|
||||
NAN_BOXED(63587,16,FLEN)
|
||||
NAN_BOXED(31169,16,FLEN)
|
||||
NAN_BOXED(63937,16,FLEN)
|
||||
NAN_BOXED(31384,16,FLEN)
|
||||
NAN_BOXED(64152,16,FLEN)
|
||||
NAN_BOXED(21693,16,FLEN)
|
||||
NAN_BOXED(54461,16,FLEN)
|
||||
NAN_BOXED(31471,16,FLEN)
|
||||
NAN_BOXED(64239,16,FLEN)
|
||||
NAN_BOXED(30003,16,FLEN)
|
||||
NAN_BOXED(62771,16,FLEN)
|
||||
NAN_BOXED(29212,16,FLEN)
|
||||
NAN_BOXED(61980,16,FLEN)
|
||||
NAN_BOXED(29601,16,FLEN)
|
||||
NAN_BOXED(62369,16,FLEN)
|
||||
NAN_BOXED(31340,16,FLEN)
|
||||
NAN_BOXED(64108,16,FLEN)
|
||||
NAN_BOXED(27941,16,FLEN)
|
||||
NAN_BOXED(60709,16,FLEN)
|
||||
NAN_BOXED(30735,16,FLEN)
|
||||
NAN_BOXED(63503,16,FLEN)
|
||||
NAN_BOXED(28410,16,FLEN)
|
||||
NAN_BOXED(61178,16,FLEN)
|
||||
NAN_BOXED(31142,16,FLEN)
|
||||
NAN_BOXED(63910,16,FLEN)
|
||||
NAN_BOXED(31363,16,FLEN)
|
||||
NAN_BOXED(64131,16,FLEN)
|
||||
NAN_BOXED(31668,16,FLEN)
|
||||
NAN_BOXED(64436,16,FLEN)
|
||||
NAN_BOXED(30898,16,FLEN)
|
||||
NAN_BOXED(63666,16,FLEN)
|
||||
NAN_BOXED(30916,16,FLEN)
|
||||
NAN_BOXED(63684,16,FLEN)
|
||||
NAN_BOXED(30874,16,FLEN)
|
||||
NAN_BOXED(63642,16,FLEN)
|
||||
NAN_BOXED(29198,16,FLEN)
|
||||
NAN_BOXED(61966,16,FLEN)
|
||||
NAN_BOXED(30950,16,FLEN)
|
||||
NAN_BOXED(63718,16,FLEN)
|
||||
NAN_BOXED(30622,16,FLEN)
|
||||
NAN_BOXED(63390,16,FLEN)
|
||||
NAN_BOXED(31246,16,FLEN)
|
||||
NAN_BOXED(64014,16,FLEN)
|
||||
NAN_BOXED(31586,16,FLEN)
|
||||
NAN_BOXED(64354,16,FLEN)
|
||||
NAN_BOXED(31534,16,FLEN)
|
||||
NAN_BOXED(64302,16,FLEN)
|
||||
NAN_BOXED(30802,16,FLEN)
|
||||
NAN_BOXED(63570,16,FLEN)
|
||||
NAN_BOXED(31139,16,FLEN)
|
||||
NAN_BOXED(63905,16,FLEN)
|
||||
NAN_BOXED(31357,16,FLEN)
|
||||
NAN_BOXED(64123,16,FLEN)
|
||||
NAN_BOXED(31528,16,FLEN)
|
||||
NAN_BOXED(64294,16,FLEN)
|
||||
NAN_BOXED(31640,16,FLEN)
|
||||
NAN_BOXED(64406,16,FLEN)
|
||||
NAN_BOXED(30516,16,FLEN)
|
||||
NAN_BOXED(63280,16,FLEN)
|
||||
NAN_BOXED(31735,16,FLEN)
|
||||
NAN_BOXED(64501,16,FLEN)
|
||||
NAN_BOXED(31319,16,FLEN)
|
||||
NAN_BOXED(64085,16,FLEN)
|
||||
NAN_BOXED(30985,16,FLEN)
|
||||
NAN_BOXED(63753,16,FLEN)
|
||||
NAN_BOXED(29638,16,FLEN)
|
||||
NAN_BOXED(62406,16,FLEN)
|
||||
NAN_BOXED(28542,16,FLEN)
|
||||
NAN_BOXED(61310,16,FLEN)
|
||||
NAN_BOXED(31322,16,FLEN)
|
||||
NAN_BOXED(64090,16,FLEN)
|
||||
NAN_BOXED(31366,16,FLEN)
|
||||
NAN_BOXED(64134,16,FLEN)
|
||||
NAN_BOXED(28846,16,FLEN)
|
||||
NAN_BOXED(61614,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(64192,16,FLEN)
|
||||
NAN_BOXED(30623,16,FLEN)
|
||||
NAN_BOXED(63391,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 114*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,320 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Sat May 6 10:51:45 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fclass.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fclass.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fclass_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fclass_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f30; dest:x30; op1val:0x8000; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f28; dest:x28; op1val:0x8001; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f26; dest:x26; op1val:0x83fe; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f25; dest:x25; op1val:0x3ff; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f24; dest:x24; op1val:0x83ff; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f23; dest:x23; op1val:0x400; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f22; dest:x22; op1val:0x8400; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f21; dest:x21; op1val:0x401; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f20; dest:x20; op1val:0x8455; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f19; dest:x19; op1val:0x7bff; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f18; dest:x18; op1val:0xfbff; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f17; dest:x17; op1val:0x7c00; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f16; dest:x16; op1val:0xfc00; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f15; dest:x15; op1val:0x7e00; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f14; dest:x14; op1val:0xfe00; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f13; dest:x13; op1val:0x7e01; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f12; dest:x12; op1val:0xfe55; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f11; dest:x11; op1val:0x7c01; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f10; dest:x10; op1val:0xfd55; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f9; dest:x9; op1val:0x3c00; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f8; dest:x8; op1val:0xbc00; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fclass.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fclass.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fclass.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fclass.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fclass.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fclass.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fclass.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fclass.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(1,16,FLEN)
|
||||
NAN_BOXED(32769,16,FLEN)
|
||||
NAN_BOXED(2,16,FLEN)
|
||||
NAN_BOXED(33790,16,FLEN)
|
||||
NAN_BOXED(1023,16,FLEN)
|
||||
NAN_BOXED(33791,16,FLEN)
|
||||
NAN_BOXED(1024,16,FLEN)
|
||||
NAN_BOXED(33792,16,FLEN)
|
||||
NAN_BOXED(1025,16,FLEN)
|
||||
NAN_BOXED(33877,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(31744,16,FLEN)
|
||||
NAN_BOXED(64512,16,FLEN)
|
||||
NAN_BOXED(32256,16,FLEN)
|
||||
NAN_BOXED(65024,16,FLEN)
|
||||
NAN_BOXED(32257,16,FLEN)
|
||||
NAN_BOXED(65109,16,FLEN)
|
||||
NAN_BOXED(31745,16,FLEN)
|
||||
NAN_BOXED(64853,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -1,320 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:39:52 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.w.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.h.w instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.w_b25 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.w_b25)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f31, x31, dyn, 0, 0, x3, 0*4, x4, x1, x2,lw)
|
||||
|
||||
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f30, x30, dyn, 0, 0, x3, 1*4, x4, x1, x2,lw)
|
||||
|
||||
inst_2:// rs1==x29, rd==f29,rs1_val == -1 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x29; dest:f29; op1val:-0x1; valaddr_reg:x3;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f29, x29, dyn, 0, 0, x3, 2*4, x4, x1, x2,lw)
|
||||
|
||||
inst_3:// rs1==x28, rd==f28,rs1_val == 2147483647 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x28; dest:f28; op1val:0x7fffffff; valaddr_reg:x3;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f28, x28, dyn, 0, 0, x3, 3*4, x4, x1, x2,lw)
|
||||
|
||||
inst_4:// rs1==x27, rd==f27,rs1_val == -2147483647 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x27; dest:f27; op1val:-0x7fffffff; valaddr_reg:x3;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f27, x27, dyn, 0, 0, x3, 4*4, x4, x1, x2,lw)
|
||||
|
||||
inst_5:// rs1==x26, rd==f26,rs1_val == 1227077728 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x26; dest:f26; op1val:0x4923b860; valaddr_reg:x3;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f26, x26, dyn, 0, 0, x3, 5*4, x4, x1, x2,lw)
|
||||
|
||||
inst_6:// rs1==x25, rd==f25,rs1_val == -1227077728 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x25; dest:f25; op1val:-0x4923b860; valaddr_reg:x3;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f25, x25, dyn, 0, 0, x3, 6*4, x4, x1, x2,lw)
|
||||
|
||||
inst_7:// rs1==x24, rd==f24,
|
||||
/* opcode: fcvt.h.w ; op1:x24; dest:f24; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f24, x24, dyn, 0, 0, x3, 7*4, x4, x1, x2,lw)
|
||||
|
||||
inst_8:// rs1==x23, rd==f23,
|
||||
/* opcode: fcvt.h.w ; op1:x23; dest:f23; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:8*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f23, x23, dyn, 0, 0, x3, 8*4, x4, x1, x2,lw)
|
||||
|
||||
inst_9:// rs1==x22, rd==f22,
|
||||
/* opcode: fcvt.h.w ; op1:x22; dest:f22; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:9*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f22, x22, dyn, 0, 0, x3, 9*4, x4, x1, x2,lw)
|
||||
|
||||
inst_10:// rs1==x21, rd==f21,
|
||||
/* opcode: fcvt.h.w ; op1:x21; dest:f21; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:10*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f21, x21, dyn, 0, 0, x3, 10*4, x4, x1, x2,lw)
|
||||
|
||||
inst_11:// rs1==x20, rd==f20,
|
||||
/* opcode: fcvt.h.w ; op1:x20; dest:f20; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:11*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f20, x20, dyn, 0, 0, x3, 11*4, x4, x1, x2,lw)
|
||||
|
||||
inst_12:// rs1==x19, rd==f19,
|
||||
/* opcode: fcvt.h.w ; op1:x19; dest:f19; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:12*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f19, x19, dyn, 0, 0, x3, 12*4, x4, x1, x2,lw)
|
||||
|
||||
inst_13:// rs1==x18, rd==f18,
|
||||
/* opcode: fcvt.h.w ; op1:x18; dest:f18; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:13*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f18, x18, dyn, 0, 0, x3, 13*4, x4, x1, x2,lw)
|
||||
|
||||
inst_14:// rs1==x17, rd==f17,
|
||||
/* opcode: fcvt.h.w ; op1:x17; dest:f17; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:14*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f17, x17, dyn, 0, 0, x3, 14*4, x4, x1, x2,lw)
|
||||
|
||||
inst_15:// rs1==x16, rd==f16,
|
||||
/* opcode: fcvt.h.w ; op1:x16; dest:f16; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:15*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f16, x16, dyn, 0, 0, x3, 15*4, x4, x1, x2,lw)
|
||||
|
||||
inst_16:// rs1==x15, rd==f15,
|
||||
/* opcode: fcvt.h.w ; op1:x15; dest:f15; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:16*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f15, x15, dyn, 0, 0, x3, 16*4, x4, x1, x2,lw)
|
||||
|
||||
inst_17:// rs1==x14, rd==f14,
|
||||
/* opcode: fcvt.h.w ; op1:x14; dest:f14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f14, x14, dyn, 0, 0, x3, 17*4, x4, x1, x2,lw)
|
||||
|
||||
inst_18:// rs1==x13, rd==f13,
|
||||
/* opcode: fcvt.h.w ; op1:x13; dest:f13; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:18*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f13, x13, dyn, 0, 0, x3, 18*4, x4, x1, x2,lw)
|
||||
|
||||
inst_19:// rs1==x12, rd==f12,
|
||||
/* opcode: fcvt.h.w ; op1:x12; dest:f12; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:19*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f12, x12, dyn, 0, 0, x3, 19*4, x4, x1, x2,lw)
|
||||
|
||||
inst_20:// rs1==x11, rd==f11,
|
||||
/* opcode: fcvt.h.w ; op1:x11; dest:f11; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:20*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f11, x11, dyn, 0, 0, x3, 20*4, x4, x1, x2,lw)
|
||||
|
||||
inst_21:// rs1==x10, rd==f10,
|
||||
/* opcode: fcvt.h.w ; op1:x10; dest:f10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f10, x10, dyn, 0, 0, x3, 21*4, x4, x1, x2,lw)
|
||||
|
||||
inst_22:// rs1==x9, rd==f9,
|
||||
/* opcode: fcvt.h.w ; op1:x9; dest:f9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f9, x9, dyn, 0, 0, x3, 22*4, x4, x1, x2,lw)
|
||||
|
||||
inst_23:// rs1==x8, rd==f8,
|
||||
/* opcode: fcvt.h.w ; op1:x8; dest:f8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f8, x8, dyn, 0, 0, x3, 23*4, x4, x1, x2,lw)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==x7, rd==f7,
|
||||
/* opcode: fcvt.h.w ; op1:x7; dest:f7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f7, x7, dyn, 0, 0, x8, 0*4, x9, x1, x2,lw)
|
||||
|
||||
inst_25:// rs1==x6, rd==f6,
|
||||
/* opcode: fcvt.h.w ; op1:x6; dest:f6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f6, x6, dyn, 0, 0, x8, 1*4, x9, x1, x2,lw)
|
||||
|
||||
inst_26:// rs1==x5, rd==f5,
|
||||
/* opcode: fcvt.h.w ; op1:x5; dest:f5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f5, x5, dyn, 0, 0, x8, 2*4, x9, x1, x6,lw)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==x4, rd==f4,
|
||||
/* opcode: fcvt.h.w ; op1:x4; dest:f4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f4, x4, dyn, 0, 0, x8, 3*4, x9, x5, x6,lw)
|
||||
|
||||
inst_28:// rs1==x3, rd==f3,
|
||||
/* opcode: fcvt.h.w ; op1:x3; dest:f3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f3, x3, dyn, 0, 0, x8, 4*4, x9, x5, x6,lw)
|
||||
|
||||
inst_29:// rs1==x2, rd==f2,
|
||||
/* opcode: fcvt.h.w ; op1:x2; dest:f2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f2, x2, dyn, 0, 0, x8, 5*4, x9, x5, x6,lw)
|
||||
|
||||
inst_30:// rs1==x1, rd==f1,
|
||||
/* opcode: fcvt.h.w ; op1:x1; dest:f1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f1, x1, dyn, 0, 0, x8, 6*4, x9, x5, x6,lw)
|
||||
|
||||
inst_31:// rs1==x0, rd==f0,
|
||||
/* opcode: fcvt.h.w ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f0, x0, dyn, 0, 0, x8, 7*4, x9, x5, x6,lw)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
.word 0;
|
||||
.word 1;
|
||||
.word -1;
|
||||
.word 2147483647;
|
||||
.word -2147483647;
|
||||
.word 1227077728;
|
||||
.word -1227077728;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
test_dataset_1:
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -1,327 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:39:52 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.w.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.h.w instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.w_b26 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.w_b26)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f31, x31, dyn, 0, 0, x3, 0*4, x4, x1, x2,lw)
|
||||
|
||||
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f30, x30, dyn, 0, 0, x3, 1*4, x4, x1, x2,lw)
|
||||
|
||||
inst_2:// rs1==x29, rd==f29,rs1_val == 2 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x29; dest:f29; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f29, x29, dyn, 0, 0, x3, 2*4, x4, x1, x2,lw)
|
||||
|
||||
inst_3:// rs1==x28, rd==f28,rs1_val == 7 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x28; dest:f28; op1val:0x7; valaddr_reg:x3;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f28, x28, dyn, 0, 0, x3, 3*4, x4, x1, x2,lw)
|
||||
|
||||
inst_4:// rs1==x27, rd==f27,rs1_val == 15 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x27; dest:f27; op1val:0xf; valaddr_reg:x3;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f27, x27, dyn, 0, 0, x3, 4*4, x4, x1, x2,lw)
|
||||
|
||||
inst_5:// rs1==x26, rd==f26,rs1_val == 16 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x26; dest:f26; op1val:0x10; valaddr_reg:x3;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f26, x26, dyn, 0, 0, x3, 5*4, x4, x1, x2,lw)
|
||||
|
||||
inst_6:// rs1==x25, rd==f25,rs1_val == 45 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x25; dest:f25; op1val:0x2d; valaddr_reg:x3;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f25, x25, dyn, 0, 0, x3, 6*4, x4, x1, x2,lw)
|
||||
|
||||
inst_7:// rs1==x24, rd==f24,rs1_val == 123 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x24; dest:f24; op1val:0x7b; valaddr_reg:x3;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f24, x24, dyn, 0, 0, x3, 7*4, x4, x1, x2,lw)
|
||||
|
||||
inst_8:// rs1==x23, rd==f23,rs1_val == 253 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x23; dest:f23; op1val:0xfd; valaddr_reg:x3;
|
||||
val_offset:8*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f23, x23, dyn, 0, 0, x3, 8*4, x4, x1, x2,lw)
|
||||
|
||||
inst_9:// rs1==x22, rd==f22,rs1_val == 398 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x22; dest:f22; op1val:0x18e; valaddr_reg:x3;
|
||||
val_offset:9*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f22, x22, dyn, 0, 0, x3, 9*4, x4, x1, x2,lw)
|
||||
|
||||
inst_10:// rs1==x21, rd==f21,rs1_val == 676 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x21; dest:f21; op1val:0x2a4; valaddr_reg:x3;
|
||||
val_offset:10*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f21, x21, dyn, 0, 0, x3, 10*4, x4, x1, x2,lw)
|
||||
|
||||
inst_11:// rs1==x20, rd==f20,rs1_val == 1094 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x20; dest:f20; op1val:0x446; valaddr_reg:x3;
|
||||
val_offset:11*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f20, x20, dyn, 0, 0, x3, 11*4, x4, x1, x2,lw)
|
||||
|
||||
inst_12:// rs1==x19, rd==f19,rs1_val == 4055 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x19; dest:f19; op1val:0xfd7; valaddr_reg:x3;
|
||||
val_offset:12*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f19, x19, dyn, 0, 0, x3, 12*4, x4, x1, x2,lw)
|
||||
|
||||
inst_13:// rs1==x18, rd==f18,rs1_val == 6781 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x18; dest:f18; op1val:0x1a7d; valaddr_reg:x3;
|
||||
val_offset:13*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f18, x18, dyn, 0, 0, x3, 13*4, x4, x1, x2,lw)
|
||||
|
||||
inst_14:// rs1==x17, rd==f17,rs1_val == 9438 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x17; dest:f17; op1val:0x24de; valaddr_reg:x3;
|
||||
val_offset:14*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f17, x17, dyn, 0, 0, x3, 14*4, x4, x1, x2,lw)
|
||||
|
||||
inst_15:// rs1==x16, rd==f16,rs1_val == 24575 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x16; dest:f16; op1val:0x5fff; valaddr_reg:x3;
|
||||
val_offset:15*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f16, x16, dyn, 0, 0, x3, 15*4, x4, x1, x2,lw)
|
||||
|
||||
inst_16:// rs1==x15, rd==f15,rs1_val == 56436 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x15; dest:f15; op1val:0xdc74; valaddr_reg:x3;
|
||||
val_offset:16*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f15, x15, dyn, 0, 0, x3, 16*4, x4, x1, x2,lw)
|
||||
|
||||
inst_17:// rs1==x14, rd==f14,rs1_val == 71376 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x14; dest:f14; op1val:0x116d0; valaddr_reg:x3;
|
||||
val_offset:17*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f14, x14, dyn, 0, 0, x3, 17*4, x4, x1, x2,lw)
|
||||
|
||||
inst_18:// rs1==x13, rd==f13,rs1_val == 241276 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x13; dest:f13; op1val:0x3ae7c; valaddr_reg:x3;
|
||||
val_offset:18*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f13, x13, dyn, 0, 0, x3, 18*4, x4, x1, x2,lw)
|
||||
|
||||
inst_19:// rs1==x12, rd==f12,rs1_val == 334857 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x12; dest:f12; op1val:0x51c09; valaddr_reg:x3;
|
||||
val_offset:19*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f12, x12, dyn, 0, 0, x3, 19*4, x4, x1, x2,lw)
|
||||
|
||||
inst_20:// rs1==x11, rd==f11,rs1_val == 896618 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x11; dest:f11; op1val:0xdae6a; valaddr_reg:x3;
|
||||
val_offset:20*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f11, x11, dyn, 0, 0, x3, 20*4, x4, x1, x2,lw)
|
||||
|
||||
inst_21:// rs1==x10, rd==f10,rs1_val == 1848861 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x10; dest:f10; op1val:0x1c361d; valaddr_reg:x3;
|
||||
val_offset:21*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f10, x10, dyn, 0, 0, x3, 21*4, x4, x1, x2,lw)
|
||||
|
||||
inst_22:// rs1==x9, rd==f9,rs1_val == 3864061 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x9; dest:f9; op1val:0x3af5fd; valaddr_reg:x3;
|
||||
val_offset:22*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f9, x9, dyn, 0, 0, x3, 22*4, x4, x1, x2,lw)
|
||||
|
||||
inst_23:// rs1==x8, rd==f8,rs1_val == 6573466 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x8; dest:f8; op1val:0x644d9a; valaddr_reg:x3;
|
||||
val_offset:23*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f8, x8, dyn, 0, 0, x3, 23*4, x4, x1, x2,lw)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==x7, rd==f7,rs1_val == 12789625 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x7; dest:f7; op1val:0xc32779; valaddr_reg:x8;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f7, x7, dyn, 0, 0, x8, 0*4, x9, x1, x2,lw)
|
||||
|
||||
inst_25:// rs1==x6, rd==f6,rs1_val == 32105925 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x6; dest:f6; op1val:0x1e9e5c5; valaddr_reg:x8;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f6, x6, dyn, 0, 0, x8, 1*4, x9, x1, x2,lw)
|
||||
|
||||
inst_26:// rs1==x5, rd==f5,rs1_val == 45276376 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x5; dest:f5; op1val:0x2b2dcd8; valaddr_reg:x8;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f5, x5, dyn, 0, 0, x8, 2*4, x9, x1, x6,lw)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==x4, rd==f4,rs1_val == 107790943 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x4; dest:f4; op1val:0x66cc25f; valaddr_reg:x8;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f4, x4, dyn, 0, 0, x8, 3*4, x9, x5, x6,lw)
|
||||
|
||||
inst_28:// rs1==x3, rd==f3,rs1_val == 231549045 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x3; dest:f3; op1val:0xdcd2875; valaddr_reg:x8;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f3, x3, dyn, 0, 0, x8, 4*4, x9, x5, x6,lw)
|
||||
|
||||
inst_29:// rs1==x2, rd==f2,rs1_val == 339827553 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x2; dest:f2; op1val:0x14415b61; valaddr_reg:x8;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f2, x2, dyn, 0, 0, x8, 5*4, x9, x5, x6,lw)
|
||||
|
||||
inst_30:// rs1==x1, rd==f1,rs1_val == 1027494066 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x1; dest:f1; op1val:0x3d3e50b2; valaddr_reg:x8;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f1, x1, dyn, 0, 0, x8, 6*4, x9, x5, x6,lw)
|
||||
|
||||
inst_31:// rs1==x0, rd==f0,rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f0, x0, dyn, 0, 0, x8, 7*4, x9, x5, x6,lw)
|
||||
|
||||
inst_32:// rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x31; dest:f31; op1val:0x5ea40361; valaddr_reg:x8;
|
||||
val_offset:8*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f31, x31, dyn, 0, 0, x8, 8*4, x9, x5, x6,lw)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
.word 0;
|
||||
.word 1;
|
||||
.word 2;
|
||||
.word 7;
|
||||
.word 15;
|
||||
.word 16;
|
||||
.word 45;
|
||||
.word 123;
|
||||
.word 253;
|
||||
.word 398;
|
||||
.word 676;
|
||||
.word 1094;
|
||||
.word 4055;
|
||||
.word 6781;
|
||||
.word 9438;
|
||||
.word 24575;
|
||||
.word 56436;
|
||||
.word 71376;
|
||||
.word 241276;
|
||||
.word 334857;
|
||||
.word 896618;
|
||||
.word 1848861;
|
||||
.word 3864061;
|
||||
.word 6573466;
|
||||
test_dataset_1:
|
||||
.word 12789625;
|
||||
.word 32105925;
|
||||
.word 45276376;
|
||||
.word 107790943;
|
||||
.word 231549045;
|
||||
.word 339827553;
|
||||
.word 1027494066;
|
||||
.word 0;
|
||||
.word 1587807073;
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 12*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -1,320 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:07 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.wu.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.h.wu instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.wu_b25 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.wu_b25)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f31, x31, dyn, 0, 0, x3, 0*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f30, x30, dyn, 0, 0, x3, 1*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_2:// rs1==x29, rd==f29,rs1_val == 4294967295 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x29; dest:f29; op1val:0xffffffff; valaddr_reg:x3;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f29, x29, dyn, 0, 0, x3, 2*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_3:// rs1==x28, rd==f28,rs1_val == 2454155456 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x28; dest:f28; op1val:0x924770c0; valaddr_reg:x3;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f28, x28, dyn, 0, 0, x3, 3*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_4:// rs1==x27, rd==f27,
|
||||
/* opcode: fcvt.h.wu ; op1:x27; dest:f27; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f27, x27, dyn, 0, 0, x3, 4*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_5:// rs1==x26, rd==f26,
|
||||
/* opcode: fcvt.h.wu ; op1:x26; dest:f26; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f26, x26, dyn, 0, 0, x3, 5*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_6:// rs1==x25, rd==f25,
|
||||
/* opcode: fcvt.h.wu ; op1:x25; dest:f25; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f25, x25, dyn, 0, 0, x3, 6*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_7:// rs1==x24, rd==f24,
|
||||
/* opcode: fcvt.h.wu ; op1:x24; dest:f24; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f24, x24, dyn, 0, 0, x3, 7*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_8:// rs1==x23, rd==f23,
|
||||
/* opcode: fcvt.h.wu ; op1:x23; dest:f23; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:8*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f23, x23, dyn, 0, 0, x3, 8*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_9:// rs1==x22, rd==f22,
|
||||
/* opcode: fcvt.h.wu ; op1:x22; dest:f22; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:9*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f22, x22, dyn, 0, 0, x3, 9*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_10:// rs1==x21, rd==f21,
|
||||
/* opcode: fcvt.h.wu ; op1:x21; dest:f21; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:10*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f21, x21, dyn, 0, 0, x3, 10*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_11:// rs1==x20, rd==f20,
|
||||
/* opcode: fcvt.h.wu ; op1:x20; dest:f20; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:11*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f20, x20, dyn, 0, 0, x3, 11*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_12:// rs1==x19, rd==f19,
|
||||
/* opcode: fcvt.h.wu ; op1:x19; dest:f19; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:12*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f19, x19, dyn, 0, 0, x3, 12*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_13:// rs1==x18, rd==f18,
|
||||
/* opcode: fcvt.h.wu ; op1:x18; dest:f18; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:13*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f18, x18, dyn, 0, 0, x3, 13*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_14:// rs1==x17, rd==f17,
|
||||
/* opcode: fcvt.h.wu ; op1:x17; dest:f17; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:14*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f17, x17, dyn, 0, 0, x3, 14*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_15:// rs1==x16, rd==f16,
|
||||
/* opcode: fcvt.h.wu ; op1:x16; dest:f16; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:15*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f16, x16, dyn, 0, 0, x3, 15*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_16:// rs1==x15, rd==f15,
|
||||
/* opcode: fcvt.h.wu ; op1:x15; dest:f15; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:16*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f15, x15, dyn, 0, 0, x3, 16*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_17:// rs1==x14, rd==f14,
|
||||
/* opcode: fcvt.h.wu ; op1:x14; dest:f14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f14, x14, dyn, 0, 0, x3, 17*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_18:// rs1==x13, rd==f13,
|
||||
/* opcode: fcvt.h.wu ; op1:x13; dest:f13; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:18*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f13, x13, dyn, 0, 0, x3, 18*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_19:// rs1==x12, rd==f12,
|
||||
/* opcode: fcvt.h.wu ; op1:x12; dest:f12; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:19*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f12, x12, dyn, 0, 0, x3, 19*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_20:// rs1==x11, rd==f11,
|
||||
/* opcode: fcvt.h.wu ; op1:x11; dest:f11; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:20*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f11, x11, dyn, 0, 0, x3, 20*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_21:// rs1==x10, rd==f10,
|
||||
/* opcode: fcvt.h.wu ; op1:x10; dest:f10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f10, x10, dyn, 0, 0, x3, 21*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_22:// rs1==x9, rd==f9,
|
||||
/* opcode: fcvt.h.wu ; op1:x9; dest:f9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f9, x9, dyn, 0, 0, x3, 22*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_23:// rs1==x8, rd==f8,
|
||||
/* opcode: fcvt.h.wu ; op1:x8; dest:f8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f8, x8, dyn, 0, 0, x3, 23*4, x4, x1, x2,LREGWU)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==x7, rd==f7,
|
||||
/* opcode: fcvt.h.wu ; op1:x7; dest:f7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f7, x7, dyn, 0, 0, x8, 0*4, x9, x1, x2,LREGWU)
|
||||
|
||||
inst_25:// rs1==x6, rd==f6,
|
||||
/* opcode: fcvt.h.wu ; op1:x6; dest:f6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f6, x6, dyn, 0, 0, x8, 1*4, x9, x1, x2,LREGWU)
|
||||
|
||||
inst_26:// rs1==x5, rd==f5,
|
||||
/* opcode: fcvt.h.wu ; op1:x5; dest:f5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f5, x5, dyn, 0, 0, x8, 2*4, x9, x1, x6,LREGWU)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==x4, rd==f4,
|
||||
/* opcode: fcvt.h.wu ; op1:x4; dest:f4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f4, x4, dyn, 0, 0, x8, 3*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_28:// rs1==x3, rd==f3,
|
||||
/* opcode: fcvt.h.wu ; op1:x3; dest:f3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f3, x3, dyn, 0, 0, x8, 4*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_29:// rs1==x2, rd==f2,
|
||||
/* opcode: fcvt.h.wu ; op1:x2; dest:f2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f2, x2, dyn, 0, 0, x8, 5*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_30:// rs1==x1, rd==f1,
|
||||
/* opcode: fcvt.h.wu ; op1:x1; dest:f1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f1, x1, dyn, 0, 0, x8, 6*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_31:// rs1==x0, rd==f0,
|
||||
/* opcode: fcvt.h.wu ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f0, x0, dyn, 0, 0, x8, 7*4, x9, x5, x6,LREGWU)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
.word 0;
|
||||
.word 1;
|
||||
.word 4294967295;
|
||||
.word 2454155456;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
test_dataset_1:
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -1,327 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:07 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.wu.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.h.wu instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.wu_b26 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.wu_b26)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f31, x31, dyn, 0, 0, x3, 0*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f30, x30, dyn, 0, 0, x3, 1*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_2:// rs1==x29, rd==f29,rs1_val == 2 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x29; dest:f29; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f29, x29, dyn, 0, 0, x3, 2*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_3:// rs1==x28, rd==f28,rs1_val == 7 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x28; dest:f28; op1val:0x7; valaddr_reg:x3;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f28, x28, dyn, 0, 0, x3, 3*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_4:// rs1==x27, rd==f27,rs1_val == 15 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x27; dest:f27; op1val:0xf; valaddr_reg:x3;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f27, x27, dyn, 0, 0, x3, 4*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_5:// rs1==x26, rd==f26,rs1_val == 16 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x26; dest:f26; op1val:0x10; valaddr_reg:x3;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f26, x26, dyn, 0, 0, x3, 5*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_6:// rs1==x25, rd==f25,rs1_val == 45 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x25; dest:f25; op1val:0x2d; valaddr_reg:x3;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f25, x25, dyn, 0, 0, x3, 6*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_7:// rs1==x24, rd==f24,rs1_val == 123 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x24; dest:f24; op1val:0x7b; valaddr_reg:x3;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f24, x24, dyn, 0, 0, x3, 7*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_8:// rs1==x23, rd==f23,rs1_val == 253 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x23; dest:f23; op1val:0xfd; valaddr_reg:x3;
|
||||
val_offset:8*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f23, x23, dyn, 0, 0, x3, 8*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_9:// rs1==x22, rd==f22,rs1_val == 398 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x22; dest:f22; op1val:0x18e; valaddr_reg:x3;
|
||||
val_offset:9*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f22, x22, dyn, 0, 0, x3, 9*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_10:// rs1==x21, rd==f21,rs1_val == 676 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x21; dest:f21; op1val:0x2a4; valaddr_reg:x3;
|
||||
val_offset:10*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f21, x21, dyn, 0, 0, x3, 10*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_11:// rs1==x20, rd==f20,rs1_val == 1094 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x20; dest:f20; op1val:0x446; valaddr_reg:x3;
|
||||
val_offset:11*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f20, x20, dyn, 0, 0, x3, 11*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_12:// rs1==x19, rd==f19,rs1_val == 4055 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x19; dest:f19; op1val:0xfd7; valaddr_reg:x3;
|
||||
val_offset:12*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f19, x19, dyn, 0, 0, x3, 12*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_13:// rs1==x18, rd==f18,rs1_val == 6781 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x18; dest:f18; op1val:0x1a7d; valaddr_reg:x3;
|
||||
val_offset:13*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f18, x18, dyn, 0, 0, x3, 13*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_14:// rs1==x17, rd==f17,rs1_val == 9438 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x17; dest:f17; op1val:0x24de; valaddr_reg:x3;
|
||||
val_offset:14*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f17, x17, dyn, 0, 0, x3, 14*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_15:// rs1==x16, rd==f16,rs1_val == 24575 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x16; dest:f16; op1val:0x5fff; valaddr_reg:x3;
|
||||
val_offset:15*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f16, x16, dyn, 0, 0, x3, 15*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_16:// rs1==x15, rd==f15,rs1_val == 56436 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x15; dest:f15; op1val:0xdc74; valaddr_reg:x3;
|
||||
val_offset:16*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f15, x15, dyn, 0, 0, x3, 16*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_17:// rs1==x14, rd==f14,rs1_val == 71376 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x14; dest:f14; op1val:0x116d0; valaddr_reg:x3;
|
||||
val_offset:17*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f14, x14, dyn, 0, 0, x3, 17*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_18:// rs1==x13, rd==f13,rs1_val == 241276 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x13; dest:f13; op1val:0x3ae7c; valaddr_reg:x3;
|
||||
val_offset:18*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f13, x13, dyn, 0, 0, x3, 18*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_19:// rs1==x12, rd==f12,rs1_val == 334857 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x12; dest:f12; op1val:0x51c09; valaddr_reg:x3;
|
||||
val_offset:19*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f12, x12, dyn, 0, 0, x3, 19*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_20:// rs1==x11, rd==f11,rs1_val == 896618 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x11; dest:f11; op1val:0xdae6a; valaddr_reg:x3;
|
||||
val_offset:20*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f11, x11, dyn, 0, 0, x3, 20*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_21:// rs1==x10, rd==f10,rs1_val == 1848861 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x10; dest:f10; op1val:0x1c361d; valaddr_reg:x3;
|
||||
val_offset:21*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f10, x10, dyn, 0, 0, x3, 21*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_22:// rs1==x9, rd==f9,rs1_val == 3864061 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x9; dest:f9; op1val:0x3af5fd; valaddr_reg:x3;
|
||||
val_offset:22*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f9, x9, dyn, 0, 0, x3, 22*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_23:// rs1==x8, rd==f8,rs1_val == 6573466 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x8; dest:f8; op1val:0x644d9a; valaddr_reg:x3;
|
||||
val_offset:23*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f8, x8, dyn, 0, 0, x3, 23*4, x4, x1, x2,LREGWU)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==x7, rd==f7,rs1_val == 12789625 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x7; dest:f7; op1val:0xc32779; valaddr_reg:x8;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f7, x7, dyn, 0, 0, x8, 0*4, x9, x1, x2,LREGWU)
|
||||
|
||||
inst_25:// rs1==x6, rd==f6,rs1_val == 32105925 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x6; dest:f6; op1val:0x1e9e5c5; valaddr_reg:x8;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f6, x6, dyn, 0, 0, x8, 1*4, x9, x1, x2,LREGWU)
|
||||
|
||||
inst_26:// rs1==x5, rd==f5,rs1_val == 45276376 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x5; dest:f5; op1val:0x2b2dcd8; valaddr_reg:x8;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f5, x5, dyn, 0, 0, x8, 2*4, x9, x1, x6,LREGWU)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==x4, rd==f4,rs1_val == 107790943 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x4; dest:f4; op1val:0x66cc25f; valaddr_reg:x8;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f4, x4, dyn, 0, 0, x8, 3*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_28:// rs1==x3, rd==f3,rs1_val == 231549045 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x3; dest:f3; op1val:0xdcd2875; valaddr_reg:x8;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f3, x3, dyn, 0, 0, x8, 4*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_29:// rs1==x2, rd==f2,rs1_val == 339827553 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x2; dest:f2; op1val:0x14415b61; valaddr_reg:x8;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f2, x2, dyn, 0, 0, x8, 5*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_30:// rs1==x1, rd==f1,rs1_val == 1027494066 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x1; dest:f1; op1val:0x3d3e50b2; valaddr_reg:x8;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f1, x1, dyn, 0, 0, x8, 6*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_31:// rs1==x0, rd==f0,rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f0, x0, dyn, 0, 0, x8, 7*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_32:// rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x31; dest:f31; op1val:0x5ea40361; valaddr_reg:x8;
|
||||
val_offset:8*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f31, x31, dyn, 0, 0, x8, 8*4, x9, x5, x6,LREGWU)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
.word 0;
|
||||
.word 1;
|
||||
.word 2;
|
||||
.word 7;
|
||||
.word 15;
|
||||
.word 16;
|
||||
.word 45;
|
||||
.word 123;
|
||||
.word 253;
|
||||
.word 398;
|
||||
.word 676;
|
||||
.word 1094;
|
||||
.word 4055;
|
||||
.word 6781;
|
||||
.word 9438;
|
||||
.word 24575;
|
||||
.word 56436;
|
||||
.word 71376;
|
||||
.word 241276;
|
||||
.word 334857;
|
||||
.word 896618;
|
||||
.word 1848861;
|
||||
.word 3864061;
|
||||
.word 6573466;
|
||||
test_dataset_1:
|
||||
.word 12789625;
|
||||
.word 32105925;
|
||||
.word 45276376;
|
||||
.word 107790943;
|
||||
.word 231549045;
|
||||
.word 339827553;
|
||||
.word 1027494066;
|
||||
.word 0;
|
||||
.word 1587807073;
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 12*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -1,320 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x8000; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x8001; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x83fe; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x3ff; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x83ff; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x400; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x8400; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x401; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x8455; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x7bff; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0xfbff; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x7c00; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0xfc00; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x7e00; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xfe00; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x7e01; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0xfe55; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x7c01; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0xfd55; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x3c00; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0xbc00; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(1,16,FLEN)
|
||||
NAN_BOXED(32769,16,FLEN)
|
||||
NAN_BOXED(2,16,FLEN)
|
||||
NAN_BOXED(33790,16,FLEN)
|
||||
NAN_BOXED(1023,16,FLEN)
|
||||
NAN_BOXED(33791,16,FLEN)
|
||||
NAN_BOXED(1024,16,FLEN)
|
||||
NAN_BOXED(33792,16,FLEN)
|
||||
NAN_BOXED(1025,16,FLEN)
|
||||
NAN_BOXED(33877,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(31744,16,FLEN)
|
||||
NAN_BOXED(64512,16,FLEN)
|
||||
NAN_BOXED(32256,16,FLEN)
|
||||
NAN_BOXED(65024,16,FLEN)
|
||||
NAN_BOXED(32257,16,FLEN)
|
||||
NAN_BOXED(65109,16,FLEN)
|
||||
NAN_BOXED(31745,16,FLEN)
|
||||
NAN_BOXED(64853,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -1,383 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b22 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b22)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x35b7; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x3a4f; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x3cd3; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x4340; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x474b; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x12 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0xca9d; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x13 and fm1 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x4ca4; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x5215; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x15 and fm1 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x554f; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 1 and fe1 == 0x16 and fm1 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0xd8ff; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x17 and fm1 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0xdfcf; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x18 and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x63fc; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x19 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x642d; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1a and fm1 == 0x370 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x6b70; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x1b and fm1 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x6e69; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x7186; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1d and fm1 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xf522; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x7ab3; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0x7bff; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x00 and fm1 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x82be; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x01 and fm1 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x86a5; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x02 and fm1 == 0x088 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x8888; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x03 and fm1 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x8f12; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x04 and fm1 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x93ed; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x05 and fm1 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x97e0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x06 and fm1 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x9a74; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x07 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x9c2d; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 1 and fe1 == 0x08 and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0xa004; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 1 and fe1 == 0x09 and fm1 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0xa489; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x0a and fm1 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0xabc3; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0xad36; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x176 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb176; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 1 and fe1 == 0x0d and fm1 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb797; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb941; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbe32; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xc1be; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xc442; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 1 and fe1 == 0x09 and fm1 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa656; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 1 and fe1 == 0x16 and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xda01; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xad36; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(13751,16,FLEN)
|
||||
NAN_BOXED(14927,16,FLEN)
|
||||
NAN_BOXED(15571,16,FLEN)
|
||||
NAN_BOXED(17216,16,FLEN)
|
||||
NAN_BOXED(18251,16,FLEN)
|
||||
NAN_BOXED(51869,16,FLEN)
|
||||
NAN_BOXED(19620,16,FLEN)
|
||||
NAN_BOXED(21013,16,FLEN)
|
||||
NAN_BOXED(21839,16,FLEN)
|
||||
NAN_BOXED(55551,16,FLEN)
|
||||
NAN_BOXED(57295,16,FLEN)
|
||||
NAN_BOXED(25596,16,FLEN)
|
||||
NAN_BOXED(25645,16,FLEN)
|
||||
NAN_BOXED(27504,16,FLEN)
|
||||
NAN_BOXED(28265,16,FLEN)
|
||||
NAN_BOXED(29062,16,FLEN)
|
||||
NAN_BOXED(62754,16,FLEN)
|
||||
NAN_BOXED(31411,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(33470,16,FLEN)
|
||||
NAN_BOXED(34469,16,FLEN)
|
||||
NAN_BOXED(34952,16,FLEN)
|
||||
NAN_BOXED(36626,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(37869,16,FLEN)
|
||||
NAN_BOXED(38880,16,FLEN)
|
||||
NAN_BOXED(39540,16,FLEN)
|
||||
NAN_BOXED(39981,16,FLEN)
|
||||
NAN_BOXED(40964,16,FLEN)
|
||||
NAN_BOXED(42121,16,FLEN)
|
||||
NAN_BOXED(43971,16,FLEN)
|
||||
NAN_BOXED(44342,16,FLEN)
|
||||
NAN_BOXED(45430,16,FLEN)
|
||||
NAN_BOXED(46999,16,FLEN)
|
||||
NAN_BOXED(47425,16,FLEN)
|
||||
NAN_BOXED(48690,16,FLEN)
|
||||
NAN_BOXED(49598,16,FLEN)
|
||||
NAN_BOXED(50242,16,FLEN)
|
||||
NAN_BOXED(42582,16,FLEN)
|
||||
NAN_BOXED(55809,16,FLEN)
|
||||
NAN_BOXED(44342,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 28*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -1,418 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b23 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b23)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x7800; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x7800; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x7800; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x7800; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x7800; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_41:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_42:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_43:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_45:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 38*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -1,838 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b24 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b24)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x2e66; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x2e66; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x2e66; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x2e66; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x2e66; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0xf0; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0xf0; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0xf0; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0xf0; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0xf0; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0xbb1e; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0xbb1e; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xbb1e; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0xbb1e; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0xbb1e; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x2f0a; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x2f0a; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x2f0a; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x2f0a; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x2f0a; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_41:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_42:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_43:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_44:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_45:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_46:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_47:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_48:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_49:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_50:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_51:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_52:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_53:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_54:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_55:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
|
||||
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_56:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
|
||||
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_57:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
|
||||
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_58:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
|
||||
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_59:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
|
||||
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_60:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_61:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_62:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_63:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_64:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_65:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_66:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_67:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_68:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_69:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_70:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
|
||||
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_71:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
|
||||
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_72:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
|
||||
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_73:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
|
||||
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_74:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
|
||||
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_75:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_76:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_77:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_78:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_79:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_80:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_81:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 57*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_82:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 58*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_83:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 59*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_84:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 60*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_85:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 61*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_86:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 62*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_87:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 63*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_88:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 64*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_89:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 65*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_90:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
|
||||
val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 66*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_91:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
|
||||
val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 67*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_92:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
|
||||
val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 68*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_93:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
|
||||
val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 69*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_94:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
|
||||
val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 70*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_95:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 71*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_96:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 72*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_97:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 73*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_98:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 74*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_99:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:75*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 75*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_100:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:76*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 76*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_101:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:77*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 77*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_102:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:78*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 78*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_103:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:79*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 79*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_104:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:80*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 80*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_105:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:81*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 81*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 158*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -1,320 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b27 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b27)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7c01; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0xfc01; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x7d55; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0xfd55; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x7e01; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0xfe01; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x7e55; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0xfe55; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(31745,16,FLEN)
|
||||
NAN_BOXED(64513,16,FLEN)
|
||||
NAN_BOXED(32085,16,FLEN)
|
||||
NAN_BOXED(64853,16,FLEN)
|
||||
NAN_BOXED(32257,16,FLEN)
|
||||
NAN_BOXED(65025,16,FLEN)
|
||||
NAN_BOXED(32341,16,FLEN)
|
||||
NAN_BOXED(65109,16,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -1,320 +0,0 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b28 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b28)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x3892; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x3c00; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x3d00; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x3e00; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x3f00; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x4000; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x4080; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x4100; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x4180; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x72dc; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x7c00; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x7c01; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x7e01; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x8000; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0xb6c0; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xbc00; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0xc180; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0xc100; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0xc080; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0xc000; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0xbf00; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0xbe00; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0xbd00; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0xf659; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0xf800; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0xfc00; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(14482,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15616,16,FLEN)
|
||||
NAN_BOXED(15872,16,FLEN)
|
||||
NAN_BOXED(16128,16,FLEN)
|
||||
NAN_BOXED(16384,16,FLEN)
|
||||
NAN_BOXED(16512,16,FLEN)
|
||||
NAN_BOXED(16640,16,FLEN)
|
||||
NAN_BOXED(16768,16,FLEN)
|
||||
NAN_BOXED(29404,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(31744,16,FLEN)
|
||||
NAN_BOXED(31745,16,FLEN)
|
||||
NAN_BOXED(32257,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(46784,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(49536,16,FLEN)
|
||||
NAN_BOXED(49408,16,FLEN)
|
||||
NAN_BOXED(49280,16,FLEN)
|
||||
NAN_BOXED(49152,16,FLEN)
|
||||
NAN_BOXED(48896,16,FLEN)
|
||||
NAN_BOXED(48640,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(48384,16,FLEN)
|
||||
NAN_BOXED(63065,16,FLEN)
|
||||
NAN_BOXED(63488,16,FLEN)
|
||||
NAN_BOXED(64512,16,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue