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Restored to original WALLY-init-lib beause new flavor is moved to cvw-arch-verif and the old is needed for PMP code coverage
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David Harris
parent
8e6170cc83
commit
4251f0c6a2
1 changed files with 22 additions and 43 deletions
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@ -7,20 +7,20 @@
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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@ -28,12 +28,6 @@
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// The PMP tests are sensitive to the exact addresses in this code, so unfortunately
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// modifying anything breaks those tests.
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// Provides simple firmware services through ecall. Place argument in a0 and issue ecall:
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// 0: change to user mode
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// 1: change to supervisor mode
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// 3: change to machine mode
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// 4: terminate program
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.section .text.init
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.global rvtest_entry_point
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@ -47,21 +41,21 @@ rvtest_entry_point:
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csrw medeleg, zero # Don't delegate exceptions
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# li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
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# li t1, 0x02004000 # MTIMECMP in CLINT
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# sd t0, 0(t1)
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li t0, 0x80
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# li t0, 0x00
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# sd t0, 0(t1)
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li t0, 0x80
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# li t0, 0x00
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csrw mie, t0 # Enable machine timer interrupt
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la t0, topoftrapstack
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la t0, topoftrapstack
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csrw mscratch, t0 # MSCRATCH holds trap stack pointer
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csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable
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# set up PMP so user and supervisor mode can access full address space
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csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX
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li t0, 0xFFFFFFFF
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li t0, 0xFFFFFFFF
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csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
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j main # Call main function in user test program
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done:
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li a0, 4 # argument to finish program
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li a0, 4 # argument to finish program
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ecall # system call to finish program
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j self_loop # wait forever (not taken)
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@ -75,11 +69,11 @@ trap_handler:
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csrr t1, mtval # And the trap value
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bgez t0, exception # if msb is clear, it is an exception
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interrupt: # must be a timer interrupt
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interrupt: # must be a timer interrupt
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li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
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li t1, 0x02004000 # MTIMECMP in CLINT
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sd t0, 0(t1)
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csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt
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li t1, 0x02004000 # MTIMECMP in CLIN
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sd t0, 0(t1)
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csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt
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li t0, 32
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csrc sip, t0 # clears stimer interrupt
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j trap_return # clean up and return
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@ -105,7 +99,7 @@ changeprivilege:
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trap_return: # return from trap handler
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csrr t0, mepc # get address of instruction that caused exception
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li t1, 0x20000
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li t1, 0x20000
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csrs mstatus, t1 # set mprv bit to fetch instruction with permission of code that trapped
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lh t0, 0(t0) # get instruction that caused exception
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csrc mstatus, t1 # clear mprv bit to restore normal operation
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@ -133,20 +127,8 @@ write_tohost:
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self_loop:
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j self_loop # wait
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// utility routines
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# put a 1 in msb of a0 (position XLEN-1); works for both RV32 and RV64
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setmsb:
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li a0, 0x80000000 # 1 in bit 31
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slli a1, a0, 1 # check if register is wider than 31 bits
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beqz a1, setmsbdone # yes, a0 has 1 in bit 31
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slli a0, a0, 16 # no: shift a0 to have 1 inn bit 63
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slli a0, a0, 16 # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64
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setmsbdone:
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ret # return to calller
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.section .tohost
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.section .tohost
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tohost: # write to HTIF
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.dword 0
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fromhost:
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@ -154,20 +136,17 @@ fromhost:
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.EQU XLEN,64
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begin_signature:
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.fill 6*(XLEN/32),4,0xdeadbeef #
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.fill 6*(XLEN/32),4,0xdeadbeef #
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end_signature:
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scratch:
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.fill 4,4,0x0
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# Initialize stack with room for 512 bytes
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.bss
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.space 512
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topofstack:
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# And another stack for the trap handler
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.bss
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.bss
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.space 512
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topoftrapstack:
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.align 4
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.section .text.main
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.section .text.main
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