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https://github.com/openhwgroup/cvw.git
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Merge pull request #891 from davidharrishmc/dev
Increased covergen.py functional coverage to 87.6%
This commit is contained in:
Rose Thompson
GitHub
commit
42f2469ea7
3 changed files with 105 additions and 34 deletions
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@ -288,7 +288,7 @@ def addLockstepTestsByDir(dir, config, sim):
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for file in os.listdir(dir):
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if file.endswith(".elf"):
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fullfile = os.path.join(dir, file)
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sim_log = sim_logdir + config + "_" + file
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sim_log = sim_logdir + config + "_" + file + ".log"
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grepstring = ""
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tc = TestCase(
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name=file,
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@ -48,32 +48,48 @@ def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, immval, rdval, test, xlen
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lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", x" + str(rs2) + " # perform operation\n"
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elif (test in shiftitype):
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lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n"
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lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + shiftImm(immval, xlen) + " # perform operation\n"
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if (test in shiftiwtype):
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lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + shiftImm(immval, 32) + " # perform operation\n"
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else:
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lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + shiftImm(immval, xlen) + " # perform operation\n"
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elif (test in itype):
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lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n"
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lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", " + signedImm12(immval) + " # perform operation\n"
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elif (test in loaditype):#["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]
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pass
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#lines = lines + "auipc x" + str(rs1) + ", 0x20" + " # add upper immediate value to pc \n"
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#lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(-immval) + " # add immediate to lower part of rs1\n"
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#lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation\n"
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if (rs1 != 0):
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lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n"
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lines = lines + "la x" + str(rs1) + ", scratch" + " # base address \n"
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lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(-immval) + " # sub immediate from rs1 to counter offset\n"
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if (xlen == 32):
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storeop = "sw"
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else:
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storeop = "sd"
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lines = lines + storeop + " x" + str(rs2) + ", " + signedImm12(immval) +" (x" + str(rs1) + ") # store value to put someting in memory\n"
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lines = lines + test + " x" + str(rd) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation\n"
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# lines = lines + test + " x" + str(rd) + ", 0(x" + str(rs1) + ") # perform operation\n"
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elif (test in stype):#["sb", "sh", "sw", "sd"]
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#lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
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#lines = lines + test + " x" + str(rs2) + ", " "0(x" + str(rs1) + ") # perform operation \n"
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#print("Error: %s type not implemented yet" % test)
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pass
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if (rs1 != 0):
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if (rs2 == rs1): # make sure registers are different so they don't conflict
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rs2 = (rs1 + 1) % 32
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if (rs2 == 0):
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rs2 = 1
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lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n"
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lines = lines + "la x" + str(rs1) + ", scratch" + " # base address \n"
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lines = lines + "addi x" + str(rs1) + ", x" + str(rs1) + ", " + signedImm12(-immval) + " # sub immediate from rs1 to counter offset\n"
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lines = lines + test + " x" + str(rs2) + ", " + signedImm12(immval) + "(x" + str(rs1) + ") # perform operation \n"
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elif (test in btype):#["beq", "bne", "blt", "bge", "bltu", "bgeu"]
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if (randint(1,100) > 50):
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rs1val = rs2val
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lines = lines + "# same values in both registers\n"
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lines = lines + "nop\n"
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lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n"
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lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n"
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lines = lines + test + " x" + str(rs1) + ", x" + str(rs2) + ", some_label_for_sb_types_" + str(immval) + "+4" + " # perform operation \n"
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lines = lines + "addi x0, x1, 1\n"
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lines = lines + "some_label_for_sb_types_" + str(immval) + ":\n"
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lines = lines + "addi x0, x2, 2\n"
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lines = lines + "nop\nnop\nnop\nnop\nnop\n"
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for same in range(2):
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if (same):
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rs1val = rs2val
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lines = lines + "# same values in both registers\n"
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lines = lines + "nop\n"
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lines = lines + "li x" + str(rs1) + ", " + formatstr.format(rs1val) + " # initialize rs1\n"
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lines = lines + "li x" + str(rs2) + ", " + formatstr.format(rs2val) + " # initialize rs2\n"
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lines = lines + test + " x" + str(rs1) + ", x" + str(rs2) + ", some_label_for_btype_" + str(immval) + str(same) + " # perform operation \n"
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lines = lines + "addi x0, x1, 1\n"
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lines = lines + "some_label_for_btype_" + str(immval)+ str(same) + ":\n"
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lines = lines + "addi x0, x2, 2\n"
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lines = lines + "nop\nnop\nnop\nnop\nnop\n"
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elif (test in jtype):#["jal"]
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lines = lines + "jal x" + str(rd) + ", 1f # perform operation\n"
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lines = lines + "nop\n"
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@ -151,7 +167,7 @@ def make_rd_rs1_rs2(test, xlen):
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def make_rs1_rs2(test, xlen):
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for r in range(32):
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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desc = "cmp_rd_rs1_rs2 (Test rs1 = rs2 = x" + str(r) + ")"
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desc = "cmp_rs1_rs2 (Test rs1 = rs2 = x" + str(r) + ")"
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writeCovVector(desc, r, r, rd, rs1val, rs2val, immval, rdval, test, xlen)
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def make_rs1_maxvals(test, xlen):
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@ -171,15 +187,15 @@ def make_rd_maxvals(test, xlen):
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# rs1 = 0, rs2 = v, others are random
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")"
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writeCovVector(desc, rs1, 0, rd, v, rs2val, immval, rdval, test, xlen)
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writeCovVector(desc, rs1, 0, rd, v, rs2val, 0, rdval, test, xlen)
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# rs1, rs2 = v, others are random
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")"
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writeCovVector(desc, rs1, rs2, rd, v, v, immval, rdval, test, xlen)
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writeCovVector(desc, rs1, rs2, rd, v, v, v, rdval, test, xlen)
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# rs1 = all 1s, rs2 = v, others are random
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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desc = "cp_rd_maxvals (Test rd value = " + hex(v) + ")"
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writeCovVector(desc, rs1, rs2, rd, -1, v, immval, rdval, test, xlen)
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writeCovVector(desc, rs1, rs2, rd, v, -1, -1, rdval, test, xlen)
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def make_rd_rs1_eqval(test, xlen):
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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@ -245,6 +261,53 @@ def make_imm_zero(test, xlen):
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desc = "cp_imm_zero"
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writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, 0, rdval, test, xlen)
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def make_j_imm_ones_zeros(test, xlen):
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for align in range(2,19):
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lines = "\n# Testcase cp_imm_ones_zeros " + str(align) + "\n"
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lines = lines + "li x1, " + formatstr.format(randint(0, 2**xlen-1)) + "\n"
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lines = lines + "jal x20, 1f # jump to aligned address to stress immediate\n"
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lines = lines + ".align " + str(align) + "\n"
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lines = lines + "1:\n"
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f.write(lines)
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def make_offset(test, xlen):
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if (test in btype):
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lines = "\n# Testcase cp_offset\n"
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lines = lines + "j 2f # jump past backward branch target\n"
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lines = lines + "1: j 3f # backward branch target: jump past backward branch\n"
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lines = lines + "2: " + test + " x0, x0, 1b # backward branch\n"
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lines = lines + "3: nop # done with sequence\n"
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f.write(lines)
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def make_mem_hazard(test, xlen):
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lines = "\n# Testcase mem_hazard (no dependency)\n"
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lines = lines + "la x1, scratch\n"
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lines = lines + test + " x2, 0(x1)\n"
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f.write(lines)
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def make_cr_rs1_imm(test, xlen):
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desc = "cp_cr_rs1_imm"
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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for s1 in range(2):
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for s2 in range(3):
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if (s1):
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rs1v = -abs(rs1val)
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else:
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rs1v = abs(rs1val)
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if (s2 == 0):
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immv = 0
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elif (s2 == 1):
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immv = abs(immval)
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else:
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immv = -abs(immval)
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writeCovVector(desc, rs1, rs2, rd, rs1v, rs2val, immv, rdval, test, xlen)
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def make_imm_shift(test, xlen):
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desc = "cp_imm_shift"
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for shift in range(0, xlen):
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[rs1, rs2, rd, rs1val, rs2val, immval, rdval] = randomize()
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writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, shift, rdval, test, xlen)
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def write_tests(coverpoints, test, xlen):
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for coverpoint in coverpoints:
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if (coverpoint == "cp_asm_count"):
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@ -298,23 +361,24 @@ def write_tests(coverpoints, test, xlen):
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elif (coverpoint == "cp_imm_sign"):
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make_imm_zero(test, xlen)
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elif (coverpoint == "cr_rs1_imm"):
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pass #TODO (not if crosses are not needed)
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make_cr_rs1_imm(test, xlen)
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elif (coverpoint == "cp_imm_ones_zeros"):
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pass #TODO
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if (test in jtype):
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make_j_imm_ones_zeros(test, xlen)
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elif (coverpoint == "cp_mem_hazard"):
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pass #TODO
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make_mem_hazard(test, xlen)
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elif (coverpoint == "cp_imm_zero"):
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make_imm_zero(test, xlen)
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elif (coverpoint == "cp_mem_unaligned"):
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pass #TODO
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pass # seems this should be part of privileged tests
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elif (coverpoint == "cp_offset"):
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pass #TODO
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make_offset(test, xlen)
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elif (coverpoint == "cr_nord_rs1_rs2"):
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pass #TODO (not if crosses are not needed)
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elif (coverpoint == "cp_imm_shift"):
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pass #TODO
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make_imm_shift(test, xlen)
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elif (coverpoint == "cp_rd_boolean"):
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pass #TODO
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pass # covered by other generators
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else:
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print("Warning: " + coverpoint + " not implemented yet for " + test)
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@ -352,8 +416,9 @@ rtype = ["add", "sub", "sll", "slt", "sltu", "xor", "srl", "sra", "or", "and",
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"mul", "mulh", "mulhsu", "mulhu", "div", "divu", "rem", "remu",
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"mulw", "divw", "divuw", "remw", "remuw"]
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loaditype = ["lb", "lh", "lw", "ld", "lbu", "lhu", "lwu"]
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shiftitype = ["slli", "srli", "srai"]
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itype = ["addi", "slti", "sltiu", "xori", "ori", "andi"]
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shiftitype = ["slli", "srli", "srai", "slliw", "srliw", "sraiw"]
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shiftiwtype = ["slliw", "srliw", "sraiw"]
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itype = ["addi", "slti", "sltiu", "xori", "ori", "andi", "addiw"]
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stype = ["sb", "sh", "sw", "sd"]
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btype = ["beq", "bne", "blt", "bge", "bltu", "bgeu"]
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jtype = ["jal"]
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@ -2,4 +2,10 @@
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self_loop:
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j self_loop
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.data
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.align 4
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scratch:
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.bss 8
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.end
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