github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-04-24 05:47:16 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

minor interrupt syntax fix

Browse source
This commit is contained in:
bbracker 2022-02-09 02:56:39 +00:00
parent 789ce53355
commit 440cac9f77
1 changed files with 2 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

3
linux/testvector-generation/parseGDBtoTrace.py
View file

@ -164,7 +164,8 @@ for line in fileinput.input('-'):
interrupts.write(str(numInstrs)+'\n')
# Convert line to rows of info for easier Verilog parsing
vals=line.strip('riscv_cpu_do_interrupt: ').strip('\n').split(',')
vals=[val.split(':')[-1].strip(' ').strip('desc=') for val in vals]
vals=[val.split(':')[-1].strip(' ') for val in vals]
vals=[val.split('=')[-1].strip(' ') for val in vals]
for val in vals:
interrupts.write(val+'\n')
continue