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Updated Fetch Buffer
Co-authored-by: Jordan Carlin <jcarlin@hmc.edu> Co-authored-by: Corey Hickson <chickson@hmc.edu>
This commit is contained in:
Vikram Krishna
parent
3dfb954947
commit
45427c393e
1 changed files with 74 additions and 89 deletions
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@ -26,114 +26,99 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fetchbuffer import cvw::*; #(parameter cvw_t P) (
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input logic clk, reset,
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input logic disableRead, disableWrite,
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input logic [P.XLEN-1:0] PCF, // PC of the instruction
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input logic [P.XLEN-1:0] PCCacheF, // Address of the instruction
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input logic [P.LINELEN-1:0] fetchData, // Data fetched from memory
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output logic empty, full,
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output logic FetchBufferStallD,
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output logic [31:0] InstrD, // Instruction to be decoded
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output logic [P.XLEN-1:0] PCD // PC of the instruction to be decoded
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input logic clk, reset,
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input logic DisableRead, DisableWrite,
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input logic [P.XLEN-1:0] PCF, // PC of the instruction
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input logic [P.XLEN-1:0] PCCacheF, // Address of the instruction
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input logic [P.ICACHE_LINELENINBITS-1:0] FetchData, // Data fetched from memory
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output logic Empty, Full,
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output logic FetchBufferStallD,
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output logic [31:0] InstrD, // Instruction to be decoded
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output logic [P.XLEN-1:0] PCD // PC of the instruction to be decoded
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);
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localparam ENTRY_INDEX_BITS = $clog2(P.ICACHE_LINELENINBITS/8);
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localparam TAG_BITS = P.XLEN - ENTRY_INDEX_BITS;
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localparam nop = 32'h00000013;
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logic readPtr, writePtr;
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logic prevReadPtr; // used to invalidate old cacheline
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logic spill;
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logic [5:0] PCF_6; // used to get the last 6 bits of PCF
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logic ReadPtr, WritePtr
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logic PrevReadPtr; // used to invalidate old cacheline
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// TODO: Check if we still need PrevReadPtr
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logic Spill;
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logic InstrMissing;
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logic valid [1:0];
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logic [P.XLEN-1-6:0] PCTag [1:0];
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logic [P.LINELEN-1:0] data [1:0];
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logic [P.XLEN-1:ENTRY_INDEX_BITS] PCFTag;
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logic [ENTRY_INDEX_BITS-1:0] EntryIndex; // used to get the last 6 bits of PCF
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assign writePtr = ~readPtr;
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assign full = valid[0] & valid[1];
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assign FetchBufferStallD = empty | (spill & ~full);
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assign PCF_6 = PCF[5:0];
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logic Valid [1:0];
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logic [TAG_BITS-1:0] PCTag [1:0];
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logic [P.ICACHE_LINELENINBITS-1:0] Data [1:0];
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always_comb begin : readPtrLogic
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if (reset) begin
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readPtr = 1'b1;
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empty = 1'b1;
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end else if (disableRead) begin
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readPtr = readPtr;
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empty = empty;
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end else if (PCF[P.XLEN-1:6] == PCTag[0]) begin
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readPtr = 1'b0;
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empty = 1'b0;
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end else if (PCF[P.XLEN-1:6] == PCTag[1]) begin
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readPtr = 1'b1;
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empty = 1'b0;
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end else begin
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readPtr = readPtr;
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empty = 1'b1; // think this was an easier way to handle empty, but should be checked
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end
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end
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assign {PCFTag, EntryIndex} = PCF;
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always_ff @( posedge clk ) begin : readPtrFsm
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if (reset) prevReadPtr <= 1'b1;
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else prevReadPtr <= readPtr;
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end
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assign WritePtr = ~ReadPtr;
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assign Full = Valid[0] & Valid[1];
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assign Empty = ~Valid[0] & ~Valid[1];
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assign InstrMissing = ~((PCFTag == PCTag[0]) | (PCFTag == PCTag[1]))
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assign FetchBufferStallD = Empty | (Spill & ~Full) | InstrMissing;
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// Don't care if it tag doesn't match either, as InstrMissing will be 1
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assign ReadPtr = (PCFTag == PCTag[1]) ? 1'b1 : 1'b0;
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flopr #(1) PrevReadPtrReg (clk, reset, ReadPtr, PrevReadPtr);
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// The priority for writing is:
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// 1. If the buffer is empty, write the new data
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// 2. If the buffer is not empty, check if the new data isn't already in the buffer
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// 3. If the new data is not in the buffer, always write to writePtr
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// 4. If the new data is already in the buffer, check readPtr to invalidate the old data
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always_ff @( posedge clk ) begin : writeLogic
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if (reset) valid <= 2'b0;
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else if (~disableWrite & empty) begin
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valid[writePtr] <= 1'b1;
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PCTag[writePtr] <= PCCacheF[P.XLEN-1:6];
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data[writePtr] <= fetchData;
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end else if (~disableWrite & (prevReadPtr != readPtr))
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valid[prevReadPtr] <= 1'b0;
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else begin
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valid[writePtr] <= valid[writePtr];
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PCTag[writePtr] <= PCTag[writePtr];
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data[writePtr] <= data[writePtr];
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end
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end
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// 1. If the buffer is Empty, write the new Data
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// 2. If the buffer is not Empty, check if the new Data isn't already in the buffer
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// 3. If the new Data is not in the buffer, always write to WritePtr
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// 4. If the new Data is already in the buffer, check ReadPtr to invalidate the old Data
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always_ff @( posedge clk )
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if (reset) Valid <= 2'b0;
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else if (~DisableWrite & (~Full | InstrMissing)) begin
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Valid[WritePtr] <= 1'b1;
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PCTag[WritePtr] <= PCCacheF[P.XLEN-1:ENTRY_INDEX_BITS];
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Data[WritePtr] <= FetchData;
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end else if (~DisableWrite & (PrevReadPtr != ReadPtr))
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Valid[PrevReadPtr] <= 1'b0;
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// TODO: Check if we need to keep the old data in the buffer
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// else begin
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// Valid <= Valid;
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// PCTag <= PCTag;
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// Data <= Data;
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// end
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// Decode Logic:
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always_ff @( posedge clk ) begin : decodeLogic
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always_ff @( posedge clk )
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if (reset) begin
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InstrD <= 32'b0;
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PCD <= P.XLEN'b0;
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spill <= 1'b0;
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end else if (disableRead) begin
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InstrD <= nop;
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PCD <= PCF;
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Spill <= 1'b0;
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end else if (DisableRead | Empty) begin
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InstrD <= InstrD;
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PCD <= PCD;
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spill <= spill;
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end else if (empty) begin
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InstrD <= 32'b0;
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PCD <= P.XLEN'b0;
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spill <= 1'b0;
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Spill <= Spill;
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end else begin
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PCD <= PCF;
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// spill logic
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if (PCF_6 == (P.LINELEN/8-2)) begin
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if (PCTag[~readPtr] == PCTag[readPtr]+1) begin
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// next cacheline holds the spill
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spill <= 1'b0;
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InstrD <= {data[~readPtr][15:0], data[readPtr][P.LINELEN-1:P.LINELEN-16]};
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end else if (data[readPtr][P.LINELEN-15:P.LINELEN-16] == 2'b11) begin
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// next cacheline doesn't hold spill but instruction is compressed so doesn't spill over
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spill <= 1'b0;
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InstrD <= {16'b0, data[readPtr][P.LINELEN-1:P.LINELEN-16]};
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// Spill logic
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if (EntryIndex[ENTRY_INDEX_BITS-1:1] == '1) begin
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if (Full) begin
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// next cacheline holds the Spill
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Spill <= 1'b0;
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InstrD <= {Data[~ReadPtr][15:0], Data[ReadPtr][P.ICACHE_LINELENINBITS-1:P.ICACHE_LINELENINBITS-16]};
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end else if (Data[ReadPtr][P.ICACHE_LINELENINBITS-15:P.ICACHE_LINELENINBITS-16] != 2'b11) begin
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// next cacheline doesn't hold Spill but instruction is compressed so doesn't Spill over
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Spill <= 1'b0;
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InstrD <= {16'b0, Data[ReadPtr][P.ICACHE_LINELENINBITS-1:P.ICACHE_LINELENINBITS-16]};
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end else begin
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// next cacheline doesn't hold spill, but it is needed as the instruction is not compressed
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spill <= 1'b1;
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InstrD <= P.XLEN'b0;
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// next cacheline doesn't hold Spill, but it is needed as the instruction is not compressed
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Spill <= 1'b1;
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InstrD <= InstrD;
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end
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end
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else begin
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end else begin
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// fetch instruction from the cacheline as needed
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spill <= 1'b0;
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InstrD <= data[readPtr][PCF_6*8 + 31:PCF_6*8];
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Spill <= 1'b0;
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InstrD <= Data[ReadPtr][EntryIndex*8 + 31:EntryIndex*8];
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end
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end
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end
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endmodule
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