Merge pull request #159 from ross144/main

Renamed signal to match book

src/cache/cacheway.sv

@@ -86,8 +86,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   assign SelNonHit = FlushWayEn | SetValid | SelWriteback;
   
   mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
-  //assign SelTag = VictimWay | FlushWay;
-  //assign SelData = HitWay | FlushWayEn | VictimWayEn;
   
   mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData);
 
@@ -95,10 +93,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   // Write Enable demux
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  // RT: Can we merge these two muxes?  This is also shared in cacheLRU.
-  //mux3 #(1) selectwaymux(HitWay, VictimWay, FlushWay,     {SelFlush, SetValid}, SelData);
-  //mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelNonHit}, SelData);
-
   assign SetValidWay = SetValid & SelData;
   assign ClearValidWay = ClearValid & SelData;
   assign SetDirtyWay = SetDirty & SelData;
@@ -117,8 +111,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
     .addr(CacheSet), .dout(ReadTag), .bwe('1),
     .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN));
 
-  
-
   // AND portion of distributed tag multiplexer
   assign TagWay = SelTag ? ReadTag : '0; // AND part of AOMux
   assign DirtyWay = SelTag & Dirty & ValidWay;

src/ebu/ahbinterface.sv

@@ -53,7 +53,6 @@ module ahbinterface #(
 );
   
   logic                                 CaptureEn;
-
   localparam                            LEN = (LSU ? `XLEN : 32);   // 32 bits for IFU, XLEN for LSU
   
   flopen #(LEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA[LEN-1:0]), .q(FetchBuffer));
@@ -70,4 +69,5 @@ module ahbinterface #(
   busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW,
     .BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY,
     .HTRANS, .HWRITE);
+
 endmodule

src/ebu/ebu.sv

@@ -66,7 +66,6 @@ module ebu (
   output logic                HMASTLOCK  // AHB master lock.  Wally does not use
 );
 
-
   logic                       LSUDisable;
   logic                       LSUSelect;
   logic                       IFUSave;
@@ -89,8 +88,6 @@ module ebu (
   logic                       IFUReq;
   logic                       LSUReq;
 
-  
-  
   assign HCLK = clk;
   assign HRESETn = ~reset;
 

src/ebu/ebufsmarb.sv

@@ -41,7 +41,6 @@ module ebufsmarb (
   input  logic       LSUReq,
   input  logic       IFUReq,
   
-  
   output logic       IFUSave,
   output logic       IFURestore,
   output logic       IFUDisable,
@@ -57,7 +56,7 @@ module ebufsmarb (
   logic              FinalBeat, FinalBeatD;      // Indicates the last beat of a burst
   logic              BeatCntEn;
   logic [3:0]        BeatCount;   // Position within a burst transfer
-  logic 	     CntReset;
+  logic              BeatCntReset;
   logic [3:0]        Threshold;                  // Number of beats derived from HBURST
 
   ////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -98,29 +97,26 @@ module ebufsmarb (
   // Burst mode logic
   ////////////////////////////////////////////////////////////////////////////////////////////////////
 
-  assign CntReset = NextState == IDLE;
+  assign BeatCntReset = NextState == IDLE;
   assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access.
+  // Counting the beats in the EBU is only necessary when both the LSU and IFU request concurrently.  
+  // LSU has priority. HREADY serves double duty during a burst transaction.  It indicates when the
+  // beat completes and when the transaction finishes.  However there is nothing external to
+  // differentiate them.  The EBU counts the HREADY beats so it knows when to switch to the IFU's 
+  // request.
   assign BeatCntEn = (NextState == ARBITRATE) & HREADY; 
-  counter #(4) BeatCounter(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, BeatCount);  
+  counter #(4) BeatCounter(HCLK, ~HRESETn | BeatCntReset | FinalBeat, BeatCntEn, BeatCount);  
  
   // Used to store data from data phase of AHB.
-  flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | CntReset, BeatCntEn, FinalBeat, FinalBeatD);
+  flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, FinalBeat, FinalBeatD);
 
-  // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST.
+  // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST, Threshold = num beats - 1.
-  //  HBURST[2:1] Beats
+  //  HBURST[2:1] Beats  threshold
-  //  00          1
+  //  00          1      0
-  //  01          4
+  //  01          4      3
-  //  10          8
+  //  10          8      7
-  //  11          16
+  //  11          16     15
   always_comb 
     if (HBURST[2:1] == 2'b00) Threshold = 4'b0000;
     else                      Threshold = (2 << HBURST[2:1]) - 1;
-/*    case(HBURST)
-      0:        Threshold = 4'b0000;
-      3:        Threshold = 4'b0011; // INCR4
-      5:        Threshold = 4'b0111; // INCR8
-      7:        Threshold = 4'b1111; // INCR16
-      default:  Threshold = 4'b0000; // INCR without end.
-    endcase
-  end */
 endmodule

src/generic/mem/ram1p1rwbe.sv

@@ -94,7 +94,6 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) (
      always_ff @(posedge clk) 
      if(ce) dout <= #1 mem[addr]; */
 
-
     // Write divided into part for bytes and part for extra msbs
     // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff.
     // Therefore these always blocks use the older always @(posedge clk) 

src/generic/mem/ram2p1r1wbe.sv

@@ -85,7 +85,6 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
     logic [SRAMWIDTH-1:0]     SRAMBitMask;      
     logic [$clog2(DEPTH)-1:0] RA1Q;
     
-      
     onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre);      
     genvar                    index;
     for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux
@@ -133,7 +132,6 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
       always @(posedge clk) 
         if (ce2 & we2 & bwe2[WIDTH/8])
           mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
-
   end
   
 endmodule

src/ifu/bpred/bpred.sv

@@ -97,8 +97,6 @@ module bpred (
   logic                    BPReturnWrongD;
   logic [`XLEN-1:0]        BPBTAE;
   
-  
-  
   // Part 1 branch direction prediction
   // look into the 2 port Sram model. something is wrong. 
   if (`BPRED_TYPE == "BP_TWOBIT") begin:Predictor

src/ifu/bpred/btb.sv

@@ -111,5 +111,4 @@ module btb #(parameter Depth = 10 ) (
   flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
   flopenr #(`XLEN) IEUAdrWReg(clk, reset, ~StallW, IEUAdrM, IEUAdrW);
 
-
 endmodule

src/ifu/spill.sv

@@ -51,8 +51,9 @@ module spill #(
 
   // Spill threshold occurs when all the cache offset PC bits are 1 (except [0]).  Without a cache this is just PCF[1]
   typedef enum logic [1:0]     {STATE_READY, STATE_SPILL} statetype;
-  statetype            CurrState, NextState;
   localparam           SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1; 
+
+  statetype         CurrState, NextState;
   logic [`XLEN-1:0] PCPlus2F;         
   logic             TakeSpillF;
   logic             SpillF;

src/uncore/ram_ahb.sv

@@ -109,6 +109,5 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
     assign DelayReady = 0;
   end
 
-  
 endmodule
   

src/wally/wallypipelinedcore.sv

@@ -247,20 +247,10 @@ module wallypipelinedcore (
     ebu ebu(// IFU connections
       .clk, .reset,
       // IFU interface
-      .IFUHADDR,
+      .IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHSIZE,
-      .IFUHBURST, 
-      .IFUHTRANS, 
-      .IFUHREADY,
-      .IFUHSIZE,
       // LSU interface
-      .LSUHADDR,
+      .LSUHADDR, .LSUHWDATA, .LSUHWSTRB, .LSUHSIZE, .LSUHBURST,
-      .LSUHWDATA,
+      .LSUHTRANS, .LSUHWRITE, .LSUHREADY,
-      .LSUHWSTRB,
-      .LSUHSIZE,
-      .LSUHBURST,
-      .LSUHTRANS,
-      .LSUHWRITE,
-      .LSUHREADY,
       // BUS interface
       .HREADY, .HRESP, .HCLK, .HRESETn,
       .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,