mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-23 13:27:16 -04:00
Added Zfh and Zfa tests to wally-riscv-arch-test until they are accepted in riscv-arch-test repo
This commit is contained in:
David Harris
parent
d1be588fff
commit
48799aa87c
245 changed files with 1733109 additions and 2 deletions
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@ -48,7 +48,7 @@ sudo apt update -y
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sudo apt upgrade -y
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sudo apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev automake autotools-dev libmpc-dev libmpfr-dev gperf libtool patchutils bc
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# Other python libraries used through the book.
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sudo pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief
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sudo pip3 install sphinx sphinx_rtd_theme matplotlib scipy scikit-learn adjustText lief markdown
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# needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3.
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if ! command -v python &> /dev/null
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@ -1,5 +1,5 @@
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all: riscoftests memfiles coveragetests deriv benchmarks
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all: riscoftests memfiles coveragetests deriv
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# *** Build old tests/imperas-riscv-tests for now;
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# Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test
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# DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired
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@ -0,0 +1,320 @@
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// -----------
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// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
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// version : 0.10.3
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// timestamp : Mon May 22 12:18:53 2023 GMT
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// usage : riscv_ctg \
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// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
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// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
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\
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// -- xlen 32 \
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// -----------
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//
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// -----------
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// Copyright (c) 2020. RISC-V International. All rights reserved.
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// SPDX-License-Identifier: BSD-3-Clause
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// -----------
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//
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// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b1 covergroup.
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//
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b1)
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RVTEST_FP_ENABLE()
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RVTEST_VALBASEUPD(x3,test_dataset_0)
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RVTEST_SIGBASE(x1,signature_x1_1)
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inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
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val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
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inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x8000000000000000; valaddr_reg:x3;
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val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
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inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
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val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
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inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x8000000000000001; valaddr_reg:x3;
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val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
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inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
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val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
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inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x8000000000000002; valaddr_reg:x3;
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val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
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inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0xfffffffffffff; valaddr_reg:x3;
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val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
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inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x800fffffffffffff; valaddr_reg:x3;
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val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
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inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x10000000000000; valaddr_reg:x3;
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val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
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inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x8010000000000000; valaddr_reg:x3;
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val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
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inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x10000000000002; valaddr_reg:x3;
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val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
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inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x8010000000000002; valaddr_reg:x3;
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val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
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inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x7fefffffffffffff; valaddr_reg:x3;
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val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
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inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0xffefffffffffffff; valaddr_reg:x3;
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val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
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inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x7ff0000000000000; valaddr_reg:x3;
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val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
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inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0xfff0000000000000; valaddr_reg:x3;
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val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
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inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0x7ff8000000000000; valaddr_reg:x3;
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val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
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inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0xfff8000000000000; valaddr_reg:x3;
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val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
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inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x7ff8000000000001; valaddr_reg:x3;
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val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
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inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0xfff8000000000001; valaddr_reg:x3;
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val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
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inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x7ff0000000000001; valaddr_reg:x3;
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val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
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inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0xfff0000000000001; valaddr_reg:x3;
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val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
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inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x3ff0000000000000; valaddr_reg:x3;
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val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
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inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
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/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0xbf80000000000000; valaddr_reg:x3;
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val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
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RVTEST_VALBASEUPD(x8,test_dataset_1)
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inst_24:// rs1==f7, rd==x7,
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/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
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val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
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inst_25:// rs1==f6, rd==x6,
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/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
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val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
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inst_26:// rs1==f5, rd==x5,
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/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
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val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
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RVTEST_SIGBASE(x5,signature_x5_0)
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inst_27:// rs1==f4, rd==x4,
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/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
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val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
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inst_28:// rs1==f3, rd==x3,
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/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
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val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
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inst_29:// rs1==f2, rd==x2,
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/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
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val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
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fcsr_val:0*/
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TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
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inst_30:// rs1==f1, rd==x1,
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/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(9223372036854775808,64,FLEN)
|
||||
NAN_BOXED(1,64,FLEN)
|
||||
NAN_BOXED(9223372036854775809,64,FLEN)
|
||||
NAN_BOXED(2,64,FLEN)
|
||||
NAN_BOXED(9223372036854775810,64,FLEN)
|
||||
NAN_BOXED(4503599627370495,64,FLEN)
|
||||
NAN_BOXED(9227875636482146303,64,FLEN)
|
||||
NAN_BOXED(4503599627370496,64,FLEN)
|
||||
NAN_BOXED(9227875636482146304,64,FLEN)
|
||||
NAN_BOXED(4503599627370498,64,FLEN)
|
||||
NAN_BOXED(9227875636482146306,64,FLEN)
|
||||
NAN_BOXED(9218868437227405311,64,FLEN)
|
||||
NAN_BOXED(18442240474082181119,64,FLEN)
|
||||
NAN_BOXED(9218868437227405312,64,FLEN)
|
||||
NAN_BOXED(18442240474082181120,64,FLEN)
|
||||
NAN_BOXED(9221120237041090560,64,FLEN)
|
||||
NAN_BOXED(18444492273895866368,64,FLEN)
|
||||
NAN_BOXED(9221120237041090561,64,FLEN)
|
||||
NAN_BOXED(18444492273895866369,64,FLEN)
|
||||
NAN_BOXED(9218868437227405313,64,FLEN)
|
||||
NAN_BOXED(18442240474082181121,64,FLEN)
|
||||
NAN_BOXED(4607182418800017408,64,FLEN)
|
||||
NAN_BOXED(13799029258263199744,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,383 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:53 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b22 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b22)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08577924770d3 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08577924770d3; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fd and fm1 == 0x93fdc7b89296c and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x3fd93fdc7b89296c; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 1 and fe1 == 0x3fe and fm1 == 0x766ba34c2da80 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0xbfe766ba34c2da80; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xd2d6b7dc59a3a and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x3ffd2d6b7dc59a3a; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x400 and fm1 == 0xcf84ba749f9c5 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x400cf84ba749f9c5; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x401 and fm1 == 0x854a908ceac39 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x401854a908ceac39; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x402 and fm1 == 0x137a953e8eb43 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x402137a953e8eb43; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x403 and fm1 == 0xf3ebcf3d06f86 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0xc03f3ebcf3d06f86; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x404 and fm1 == 0x5c74eff1e5bef and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x4045c74eff1e5bef; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x405 and fm1 == 0xdc3386b9f15c4 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x405dc3386b9f15c4; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x406 and fm1 == 0x5ae6a9a6ab329 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x4065ae6a9a6ab329; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x407 and fm1 == 0x489b36bd7f503 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0xc07489b36bd7f503; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x408 and fm1 == 0x43277acca7f0d and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x40843277acca7f0d; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x409 and fm1 == 0xaf9492cb7362c and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x409af9492cb7362c; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x40a and fm1 == 0x5cd28a96ec2b3 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x40a5cd28a96ec2b3; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x40b and fm1 == 0xc491074f942cb and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0xc0bc491074f942cb; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x40c and fm1 == 0x3d480fb7f6f5d and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0xc0c3d480fb7f6f5d; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x40d and fm1 == 0x9d02f708cc1b6 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0x40d9d02f708cc1b6; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x40e and fm1 == 0x953b00b54aa22 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x40e953b00b54aa22; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x40f and fm1 == 0x224c03c53d0e3 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0x40f224c03c53d0e3; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x410 and fm1 == 0xe8dacf0e58650 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x410e8dacf0e58650; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x411 and fm1 == 0x5dbbb894deab4 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0xc115dbbb894deab4; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x412 and fm1 == 0x3d7c9e5f0307e and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x4123d7c9e5f0307e; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x413 and fm1 == 0x8c8a1aaac3142 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0x4138c8a1aaac3142; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x414 and fm1 == 0x785036f9fb997 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x414785036f9fb997; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x415 and fm1 == 0x95a4da7298c66 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x41595a4da7298c66; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x416 and fm1 == 0x807dad814d575 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x416807dad814d575; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x417 and fm1 == 0x396bad798c9cf and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0xc17396bad798c9cf; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x418 and fm1 == 0x3d06169b1dcbf and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x4183d06169b1dcbf; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x419 and fm1 == 0x7f21608208d09 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x4197f21608208d09; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x41a and fm1 == 0x9b4f3d167533a and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0xc1a9b4f3d167533a; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x41b and fm1 == 0x889261270dee2 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0xc1b889261270dee2; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 0 and fe1 == 0x41c and fm1 == 0x14b91dae98554 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x41c14b91dae98554; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 1 and fe1 == 0x41d and fm1 == 0x9136562694646 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc1d9136562694646; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 1 and fe1 == 0x41e and fm1 == 0xe9b7e5fc9eba4 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc1ee9b7e5fc9eba4; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 1 and fe1 == 0x41f and fm1 == 0x1ce80265039f6 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc1f1ce80265039f6; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 0 and fe1 == 0x420 and fm1 == 0xc5ec6c6880007 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x420c5ec6c6880007; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 1 and fe1 == 0x421 and fm1 == 0x2a96d71097999 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc212a96d71097999; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 0 and fe1 == 0x3ca and fm1 == 0x30e08ceb506f6 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ca30e08ceb506f6; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 0 and fe1 == 0x5ca and fm1 == 0xf871c6ee84270 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x5caf871c6ee84270; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 1 and fe1 == 0x41b and fm1 == 0x889261270dee2 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xc1b889261270dee2; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(4593818368519663827,64,FLEN)
|
||||
NAN_BOXED(4600778710533613932,64,FLEN)
|
||||
NAN_BOXED(13828134130799532672,64,FLEN)
|
||||
NAN_BOXED(4610891533192108602,64,FLEN)
|
||||
NAN_BOXED(4615336721960794565,64,FLEN)
|
||||
NAN_BOXED(4618534502842412089,64,FLEN)
|
||||
NAN_BOXED(4621035893055613763,64,FLEN)
|
||||
NAN_BOXED(13852859960080232326,64,FLEN)
|
||||
NAN_BOXED(4631326933921979375,64,FLEN)
|
||||
NAN_BOXED(4638077838352651716,64,FLEN)
|
||||
NAN_BOXED(4640306763955614505,64,FLEN)
|
||||
NAN_BOXED(13867860556282066179,64,FLEN)
|
||||
NAN_BOXED(4648896204934643469,64,FLEN)
|
||||
NAN_BOXED(4655307257518962220,64,FLEN)
|
||||
NAN_BOXED(4658354964109640371,64,FLEN)
|
||||
NAN_BOXED(13888055685934564043,64,FLEN)
|
||||
NAN_BOXED(13890179326181076829,64,FLEN)
|
||||
NAN_BOXED(4672994990543913398,64,FLEN)
|
||||
NAN_BOXED(4677361703570418210,64,FLEN)
|
||||
NAN_BOXED(4679843370855813347,64,FLEN)
|
||||
NAN_BOXED(4687840036054730320,64,FLEN)
|
||||
NAN_BOXED(13913268222339967668,64,FLEN)
|
||||
NAN_BOXED(4693832498796310654,64,FLEN)
|
||||
NAN_BOXED(4699726807839813954,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(4703874585615907223,64,FLEN)
|
||||
NAN_BOXED(4708894174956063846,64,FLEN)
|
||||
NAN_BOXED(4713025646552733045,64,FLEN)
|
||||
NAN_BOXED(13939651000867015119,64,FLEN)
|
||||
NAN_BOXED(4720845951218080959,64,FLEN)
|
||||
NAN_BOXED(4726512510388178185,64,FLEN)
|
||||
NAN_BOXED(13954883879667454778,64,FLEN)
|
||||
NAN_BOXED(13959057841646001890,64,FLEN)
|
||||
NAN_BOXED(4738151372785550676,64,FLEN)
|
||||
NAN_BOXED(13968217045429995078,64,FLEN)
|
||||
NAN_BOXED(13974277660852480932,64,FLEN)
|
||||
NAN_BOXED(13975178168501287414,64,FLEN)
|
||||
NAN_BOXED(4759283114051108871,64,FLEN)
|
||||
NAN_BOXED(13984426080451787161,64,FLEN)
|
||||
NAN_BOXED(4369351494470010614,64,FLEN)
|
||||
NAN_BOXED(6678705328603284080,64,FLEN)
|
||||
NAN_BOXED(13959057841646001890,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 28*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,418 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:53 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b23 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b23)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43dffffffffffffc; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x43dffffffffffffc; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x43dffffffffffffc; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x43dffffffffffffc; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x43dffffffffffffc; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x43dffffffffffffd; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x43dffffffffffffd; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x43dffffffffffffd; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x43dffffffffffffd; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x43dffffffffffffd; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x43dffffffffffffe; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x43dffffffffffffe; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x43dffffffffffffe; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x43dffffffffffffe; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x43dffffffffffffe; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0x43dfffffffffffff; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0x43dfffffffffffff; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0x43dfffffffffffff; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x43dfffffffffffff; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0x43dfffffffffffff; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x43e0000000000000; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0x43e0000000000000; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x43e0000000000000; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0x43e0000000000000; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x43e0000000000000; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x43e0000000000001; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x43e0000000000001; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x43e0000000000001; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x43e0000000000001; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x43e0000000000001; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x43e0000000000002; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x43e0000000000002; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_41:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
|
||||
val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_42:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
|
||||
val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_43:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
|
||||
val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_44:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x8;
|
||||
val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_45:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x8;
|
||||
val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(4890909195324358652,64,FLEN)
|
||||
NAN_BOXED(4890909195324358652,64,FLEN)
|
||||
NAN_BOXED(4890909195324358652,64,FLEN)
|
||||
NAN_BOXED(4890909195324358652,64,FLEN)
|
||||
NAN_BOXED(4890909195324358652,64,FLEN)
|
||||
NAN_BOXED(4890909195324358653,64,FLEN)
|
||||
NAN_BOXED(4890909195324358653,64,FLEN)
|
||||
NAN_BOXED(4890909195324358653,64,FLEN)
|
||||
NAN_BOXED(4890909195324358653,64,FLEN)
|
||||
NAN_BOXED(4890909195324358653,64,FLEN)
|
||||
NAN_BOXED(4890909195324358654,64,FLEN)
|
||||
NAN_BOXED(4890909195324358654,64,FLEN)
|
||||
NAN_BOXED(4890909195324358654,64,FLEN)
|
||||
NAN_BOXED(4890909195324358654,64,FLEN)
|
||||
NAN_BOXED(4890909195324358654,64,FLEN)
|
||||
NAN_BOXED(4890909195324358655,64,FLEN)
|
||||
NAN_BOXED(4890909195324358655,64,FLEN)
|
||||
NAN_BOXED(4890909195324358655,64,FLEN)
|
||||
NAN_BOXED(4890909195324358655,64,FLEN)
|
||||
NAN_BOXED(4890909195324358655,64,FLEN)
|
||||
NAN_BOXED(4890909195324358656,64,FLEN)
|
||||
NAN_BOXED(4890909195324358656,64,FLEN)
|
||||
NAN_BOXED(4890909195324358656,64,FLEN)
|
||||
NAN_BOXED(4890909195324358656,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(4890909195324358656,64,FLEN)
|
||||
NAN_BOXED(4890909195324358657,64,FLEN)
|
||||
NAN_BOXED(4890909195324358657,64,FLEN)
|
||||
NAN_BOXED(4890909195324358657,64,FLEN)
|
||||
NAN_BOXED(4890909195324358657,64,FLEN)
|
||||
NAN_BOXED(4890909195324358657,64,FLEN)
|
||||
NAN_BOXED(4890909195324358658,64,FLEN)
|
||||
NAN_BOXED(4890909195324358658,64,FLEN)
|
||||
NAN_BOXED(4890909195324358658,64,FLEN)
|
||||
NAN_BOXED(4890909195324358658,64,FLEN)
|
||||
NAN_BOXED(4890909195324358658,64,FLEN)
|
||||
NAN_BOXED(4890909195324358659,64,FLEN)
|
||||
NAN_BOXED(4890909195324358659,64,FLEN)
|
||||
NAN_BOXED(4890909195324358659,64,FLEN)
|
||||
NAN_BOXED(4890909195324358659,64,FLEN)
|
||||
NAN_BOXED(4890909195324358659,64,FLEN)
|
||||
NAN_BOXED(4890909195324358660,64,FLEN)
|
||||
NAN_BOXED(4890909195324358660,64,FLEN)
|
||||
NAN_BOXED(4890909195324358660,64,FLEN)
|
||||
NAN_BOXED(4890909195324358660,64,FLEN)
|
||||
NAN_BOXED(4890909195324358660,64,FLEN)
|
||||
NAN_BOXED(4890909195324358658,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 38*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,838 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:53 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b24 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b24)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0xbfb999999999999a; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0xbfb999999999999a; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0xbfb999999999999a; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0xbfb999999999999a; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0xbfb999999999999a; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0xbff0000000000000; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0xbff0000000000000; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_41:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
|
||||
val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_42:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
|
||||
val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_43:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
|
||||
val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_44:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x8;
|
||||
val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_45:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
|
||||
val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_46:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
|
||||
val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_47:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
|
||||
val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_48:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
|
||||
val_offset:24*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_49:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x8;
|
||||
val_offset:25*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_50:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
|
||||
val_offset:26*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_51:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
|
||||
val_offset:27*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_52:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
|
||||
val_offset:28*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_53:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
|
||||
val_offset:29*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_54:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x8;
|
||||
val_offset:30*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_55:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x8;
|
||||
val_offset:31*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_56:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x8;
|
||||
val_offset:32*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_57:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x8;
|
||||
val_offset:33*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_58:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x8;
|
||||
val_offset:34*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_59:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x8;
|
||||
val_offset:35*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_60:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3feccccccccccccd; valaddr_reg:x8;
|
||||
val_offset:36*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_61:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3feccccccccccccd; valaddr_reg:x8;
|
||||
val_offset:37*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_62:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3feccccccccccccd; valaddr_reg:x8;
|
||||
val_offset:38*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_63:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3feccccccccccccd; valaddr_reg:x8;
|
||||
val_offset:39*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_64:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3feccccccccccccd; valaddr_reg:x8;
|
||||
val_offset:40*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_65:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x8;
|
||||
val_offset:41*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_66:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x8;
|
||||
val_offset:42*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_67:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x8;
|
||||
val_offset:43*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_68:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x8;
|
||||
val_offset:44*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_69:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x8;
|
||||
val_offset:45*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_70:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
|
||||
val_offset:46*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_71:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
|
||||
val_offset:47*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_72:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
|
||||
val_offset:48*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_73:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
|
||||
val_offset:49*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_74:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x8;
|
||||
val_offset:50*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_75:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
|
||||
val_offset:51*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_76:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
|
||||
val_offset:52*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_77:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
|
||||
val_offset:53*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_78:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
|
||||
val_offset:54*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_79:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x8;
|
||||
val_offset:55*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_80:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:56*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_81:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:57*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 57*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_82:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:58*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 58*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_83:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:59*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 59*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_84:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:60*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 60*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_85:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x8;
|
||||
val_offset:61*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 61*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_86:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x8;
|
||||
val_offset:62*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 62*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_87:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x8;
|
||||
val_offset:63*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 63*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_88:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x8;
|
||||
val_offset:64*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 64*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_89:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x8;
|
||||
val_offset:65*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 65*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_90:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:66*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 66*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_91:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:67*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 67*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_92:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:68*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 68*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_93:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:69*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 69*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_94:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x8;
|
||||
val_offset:70*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 70*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_95:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
|
||||
val_offset:71*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 71*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_96:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
|
||||
val_offset:72*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 72*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_97:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
|
||||
val_offset:73*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 73*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_98:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
|
||||
val_offset:74*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 74*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_99:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fb999999999999a; valaddr_reg:x8;
|
||||
val_offset:75*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 75*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_100:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
|
||||
val_offset:76*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 76*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_101:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
|
||||
val_offset:77*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 77*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_102:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
|
||||
val_offset:78*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 78*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_103:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
|
||||
val_offset:79*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 79*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_104:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x8;
|
||||
val_offset:80*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 80*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_105:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x8;
|
||||
val_offset:81*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 81*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(4606191626881995899,64,FLEN)
|
||||
NAN_BOXED(4606191626881995899,64,FLEN)
|
||||
NAN_BOXED(4606191626881995899,64,FLEN)
|
||||
NAN_BOXED(4606191626881995899,64,FLEN)
|
||||
NAN_BOXED(4606191626881995899,64,FLEN)
|
||||
NAN_BOXED(4576918229304087675,64,FLEN)
|
||||
NAN_BOXED(4576918229304087675,64,FLEN)
|
||||
NAN_BOXED(4576918229304087675,64,FLEN)
|
||||
NAN_BOXED(4576918229304087675,64,FLEN)
|
||||
NAN_BOXED(4576918229304087675,64,FLEN)
|
||||
NAN_BOXED(4607677814759028163,64,FLEN)
|
||||
NAN_BOXED(4607677814759028163,64,FLEN)
|
||||
NAN_BOXED(4607677814759028163,64,FLEN)
|
||||
NAN_BOXED(4607677814759028163,64,FLEN)
|
||||
NAN_BOXED(4607677814759028163,64,FLEN)
|
||||
NAN_BOXED(13815962792862112809,64,FLEN)
|
||||
NAN_BOXED(13815962792862112809,64,FLEN)
|
||||
NAN_BOXED(13815962792862112809,64,FLEN)
|
||||
NAN_BOXED(13815962792862112809,64,FLEN)
|
||||
NAN_BOXED(13815962792862112809,64,FLEN)
|
||||
NAN_BOXED(13815242216921733530,64,FLEN)
|
||||
NAN_BOXED(13815242216921733530,64,FLEN)
|
||||
NAN_BOXED(13815242216921733530,64,FLEN)
|
||||
NAN_BOXED(13815242216921733530,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(13815242216921733530,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(13830554455654793216,64,FLEN)
|
||||
NAN_BOXED(13830554455654793216,64,FLEN)
|
||||
NAN_BOXED(13830554455654793216,64,FLEN)
|
||||
NAN_BOXED(13830554455654793216,64,FLEN)
|
||||
NAN_BOXED(13830554455654793216,64,FLEN)
|
||||
NAN_BOXED(4607227454796291113,64,FLEN)
|
||||
NAN_BOXED(4607227454796291113,64,FLEN)
|
||||
NAN_BOXED(4607227454796291113,64,FLEN)
|
||||
NAN_BOXED(4607227454796291113,64,FLEN)
|
||||
NAN_BOXED(4607227454796291113,64,FLEN)
|
||||
NAN_BOXED(13829563663736771707,64,FLEN)
|
||||
NAN_BOXED(13829563663736771707,64,FLEN)
|
||||
NAN_BOXED(13829563663736771707,64,FLEN)
|
||||
NAN_BOXED(13829563663736771707,64,FLEN)
|
||||
NAN_BOXED(13829563663736771707,64,FLEN)
|
||||
NAN_BOXED(13831004815617530266,64,FLEN)
|
||||
NAN_BOXED(13831004815617530266,64,FLEN)
|
||||
NAN_BOXED(13831004815617530266,64,FLEN)
|
||||
NAN_BOXED(13831004815617530266,64,FLEN)
|
||||
NAN_BOXED(13831004815617530266,64,FLEN)
|
||||
NAN_BOXED(4607182418800017408,64,FLEN)
|
||||
NAN_BOXED(4607182418800017408,64,FLEN)
|
||||
NAN_BOXED(4607182418800017408,64,FLEN)
|
||||
NAN_BOXED(4607182418800017408,64,FLEN)
|
||||
NAN_BOXED(4607182418800017408,64,FLEN)
|
||||
NAN_BOXED(13800290266158863483,64,FLEN)
|
||||
NAN_BOXED(13800290266158863483,64,FLEN)
|
||||
NAN_BOXED(13800290266158863483,64,FLEN)
|
||||
NAN_BOXED(13800290266158863483,64,FLEN)
|
||||
NAN_BOXED(13800290266158863483,64,FLEN)
|
||||
NAN_BOXED(4606281698874543309,64,FLEN)
|
||||
NAN_BOXED(4606281698874543309,64,FLEN)
|
||||
NAN_BOXED(4606281698874543309,64,FLEN)
|
||||
NAN_BOXED(4606281698874543309,64,FLEN)
|
||||
NAN_BOXED(4606281698874543309,64,FLEN)
|
||||
NAN_BOXED(13830464383662245806,64,FLEN)
|
||||
NAN_BOXED(13830464383662245806,64,FLEN)
|
||||
NAN_BOXED(13830464383662245806,64,FLEN)
|
||||
NAN_BOXED(13830464383662245806,64,FLEN)
|
||||
NAN_BOXED(13830464383662245806,64,FLEN)
|
||||
NAN_BOXED(4607632778762754458,64,FLEN)
|
||||
NAN_BOXED(4607632778762754458,64,FLEN)
|
||||
NAN_BOXED(4607632778762754458,64,FLEN)
|
||||
NAN_BOXED(4607632778762754458,64,FLEN)
|
||||
NAN_BOXED(4607632778762754458,64,FLEN)
|
||||
NAN_BOXED(13831049851613803971,64,FLEN)
|
||||
NAN_BOXED(13831049851613803971,64,FLEN)
|
||||
NAN_BOXED(13831049851613803971,64,FLEN)
|
||||
NAN_BOXED(13831049851613803971,64,FLEN)
|
||||
NAN_BOXED(13831049851613803971,64,FLEN)
|
||||
NAN_BOXED(4592590756007337001,64,FLEN)
|
||||
NAN_BOXED(4592590756007337001,64,FLEN)
|
||||
NAN_BOXED(4592590756007337001,64,FLEN)
|
||||
NAN_BOXED(4592590756007337001,64,FLEN)
|
||||
NAN_BOXED(4592590756007337001,64,FLEN)
|
||||
NAN_BOXED(4607092346807469998,64,FLEN)
|
||||
NAN_BOXED(4607092346807469998,64,FLEN)
|
||||
NAN_BOXED(4607092346807469998,64,FLEN)
|
||||
NAN_BOXED(4607092346807469998,64,FLEN)
|
||||
NAN_BOXED(4607092346807469998,64,FLEN)
|
||||
NAN_BOXED(13830599491651066921,64,FLEN)
|
||||
NAN_BOXED(13830599491651066921,64,FLEN)
|
||||
NAN_BOXED(13830599491651066921,64,FLEN)
|
||||
NAN_BOXED(13830599491651066921,64,FLEN)
|
||||
NAN_BOXED(13830599491651066921,64,FLEN)
|
||||
NAN_BOXED(4591870180066957722,64,FLEN)
|
||||
NAN_BOXED(4591870180066957722,64,FLEN)
|
||||
NAN_BOXED(4591870180066957722,64,FLEN)
|
||||
NAN_BOXED(4591870180066957722,64,FLEN)
|
||||
NAN_BOXED(4591870180066957722,64,FLEN)
|
||||
NAN_BOXED(13829653735729319117,64,FLEN)
|
||||
NAN_BOXED(13829653735729319117,64,FLEN)
|
||||
NAN_BOXED(13829653735729319117,64,FLEN)
|
||||
NAN_BOXED(13829653735729319117,64,FLEN)
|
||||
NAN_BOXED(13829653735729319117,64,FLEN)
|
||||
NAN_BOXED(13830554455654793216,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 158*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:53 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b27 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b27)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x7ff0000000000001; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0xfff0000000000001; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x7ff4aaaaaaaaaaaa; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0xfff4aaaaaaaaaaaa; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x7ff8000000000001; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0xfff8000000000001; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x7ffc000000000001; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0xfffc000000000001; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,
|
||||
/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,
|
||||
/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,
|
||||
/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,
|
||||
/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,
|
||||
/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,
|
||||
/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,
|
||||
/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,
|
||||
/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,
|
||||
/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,
|
||||
/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,
|
||||
/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,
|
||||
/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,
|
||||
/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,
|
||||
/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,
|
||||
/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,
|
||||
/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(9218868437227405313,64,FLEN)
|
||||
NAN_BOXED(18442240474082181121,64,FLEN)
|
||||
NAN_BOXED(9220181987118721706,64,FLEN)
|
||||
NAN_BOXED(18443554023973497514,64,FLEN)
|
||||
NAN_BOXED(9221120237041090561,64,FLEN)
|
||||
NAN_BOXED(18444492273895866369,64,FLEN)
|
||||
NAN_BOXED(9222246136947933185,64,FLEN)
|
||||
NAN_BOXED(18445618173802708993,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:53 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b28 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b28)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x3fe248ee18215dfa; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x3ff0000000000000; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x3ff4000000000000; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x3ff8000000000000; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x3ffc000000000000; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x4000000000000000; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x4002000000000000; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x4004000000000000; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x4006000000000000; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x43cb72eb13dc494a; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x43e0000000000000; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x7ff0000000000000; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x7ff0000000000001; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x7ff8000000000001; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0x8000000000000000; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0xbfdb008d57e19f88; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0xbf80000000000000; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0xc006000000000000; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0xc004000000000000; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0xc002000000000000; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0xc000000000000000; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0xbffc000000000000; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0xbff8000000000000; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0xbff4000000000000; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0xc3d967a4ae26514c; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0xc3e0000000000000; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0xfff0000000000000; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(4603321956570324474,64,FLEN)
|
||||
NAN_BOXED(4607182418800017408,64,FLEN)
|
||||
NAN_BOXED(4608308318706860032,64,FLEN)
|
||||
NAN_BOXED(4609434218613702656,64,FLEN)
|
||||
NAN_BOXED(4610560118520545280,64,FLEN)
|
||||
NAN_BOXED(4611686018427387904,64,FLEN)
|
||||
NAN_BOXED(4612248968380809216,64,FLEN)
|
||||
NAN_BOXED(4612811918334230528,64,FLEN)
|
||||
NAN_BOXED(4613374868287651840,64,FLEN)
|
||||
NAN_BOXED(4885124574789519690,64,FLEN)
|
||||
NAN_BOXED(4890909195324358656,64,FLEN)
|
||||
NAN_BOXED(9218868437227405312,64,FLEN)
|
||||
NAN_BOXED(9218868437227405313,64,FLEN)
|
||||
NAN_BOXED(9221120237041090561,64,FLEN)
|
||||
NAN_BOXED(9223372036854775808,64,FLEN)
|
||||
NAN_BOXED(13824644088208662408,64,FLEN)
|
||||
NAN_BOXED(13799029258263199744,64,FLEN)
|
||||
NAN_BOXED(13836746905142427648,64,FLEN)
|
||||
NAN_BOXED(13836183955189006336,64,FLEN)
|
||||
NAN_BOXED(13835621005235585024,64,FLEN)
|
||||
NAN_BOXED(13835058055282163712,64,FLEN)
|
||||
NAN_BOXED(13833932155375321088,64,FLEN)
|
||||
NAN_BOXED(13832806255468478464,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(13831680355561635840,64,FLEN)
|
||||
NAN_BOXED(14112424864336204108,64,FLEN)
|
||||
NAN_BOXED(14114281232179134464,64,FLEN)
|
||||
NAN_BOXED(18442240474082181120,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,663 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:53 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fcvtmod.w.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvtmod.w.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fcvtmod.w.d_b29 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fcvtmod.w.d_b29)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b8698; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f30; dest:x30; op1val:0x3fc08574923b8698; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x30, f30, rtz, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f29; dest:x29; op1val:0x3fc08574923b8698; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x29, f29, rtz, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f28; dest:x28; op1val:0x3fc08574923b8698; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x28, f28, rtz, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f27; dest:x27; op1val:0x3fc08574923b8698; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x27, f27, rtz, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f26; dest:x26; op1val:0x3fc08574923b8699; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x26, f26, rtz, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f25; dest:x25; op1val:0x3fc08574923b8699; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x25, f25, rtz, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f24; dest:x24; op1val:0x3fc08574923b8699; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x24, f24, rtz, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f23; dest:x23; op1val:0x3fc08574923b8699; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x23, f23, rtz, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f22; dest:x22; op1val:0x3fc08574923b8699; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x22, f22, rtz, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f21; dest:x21; op1val:0x3fc08574923b869a; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x21, f21, rtz, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f20; dest:x20; op1val:0x3fc08574923b869a; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x20, f20, rtz, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f19; dest:x19; op1val:0x3fc08574923b869a; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x19, f19, rtz, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f18; dest:x18; op1val:0x3fc08574923b869a; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x18, f18, rtz, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f17; dest:x17; op1val:0x3fc08574923b869a; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x17, f17, rtz, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f16; dest:x16; op1val:0x3fc08574923b869b; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x16, f16, rtz, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f15; dest:x15; op1val:0x3fc08574923b869b; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x15, f15, rtz, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f14; dest:x14; op1val:0x3fc08574923b869b; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x14, f14, rtz, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f13; dest:x13; op1val:0x3fc08574923b869b; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x13, f13, rtz, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f12; dest:x12; op1val:0x3fc08574923b869b; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x12, f12, rtz, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f11; dest:x11; op1val:0x3fc08574923b869c; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x11, f11, rtz, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f10; dest:x10; op1val:0x3fc08574923b869c; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x10, f10, rtz, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f9; dest:x9; op1val:0x3fc08574923b869c; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x9, f9, rtz, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f8; dest:x8; op1val:0x3fc08574923b869c; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x8, f8, rtz, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f7; dest:x7; op1val:0x3fc08574923b869c; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x7, f7, rtz, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f6; dest:x6; op1val:0x3fc08574923b869d; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:rtz; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x6, f6, rtz, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f5; dest:x5; op1val:0x3fc08574923b869d; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x5, f5, rtz, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f4; dest:x4; op1val:0x3fc08574923b869d; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x4, f4, rtz, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f3; dest:x3; op1val:0x3fc08574923b869d; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x3, f3, rtz, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f2; dest:x2; op1val:0x3fc08574923b869d; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x2, f2, rtz, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f1; dest:x1; op1val:0x3fc08574923b869e; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x1, f1, rtz, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f0; dest:x0; op1val:0x3fc08574923b869e; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x0, f0, rtz, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_41:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
|
||||
val_offset:17*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_42:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
|
||||
val_offset:18*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_43:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
|
||||
val_offset:19*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_44:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x8;
|
||||
val_offset:20*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_45:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
|
||||
val_offset:21*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_46:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
|
||||
val_offset:22*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_47:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
|
||||
val_offset:23*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_48:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
|
||||
val_offset:24*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_49:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x8;
|
||||
val_offset:25*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_50:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
|
||||
val_offset:26*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_51:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
|
||||
val_offset:27*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_52:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
|
||||
val_offset:28*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_53:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
|
||||
val_offset:29*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_54:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x8;
|
||||
val_offset:30*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_55:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
|
||||
val_offset:31*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_56:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
|
||||
val_offset:32*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_57:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
|
||||
val_offset:33*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_58:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
|
||||
val_offset:34*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_59:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x8;
|
||||
val_offset:35*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_60:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
|
||||
val_offset:36*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_61:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
|
||||
val_offset:37*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_62:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
|
||||
val_offset:38*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_63:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
|
||||
val_offset:39*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_64:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x8;
|
||||
val_offset:40*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_65:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
|
||||
val_offset:41*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_66:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
|
||||
val_offset:42*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_67:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
|
||||
val_offset:43*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_68:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
|
||||
val_offset:44*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_69:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x8;
|
||||
val_offset:45*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_70:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
|
||||
val_offset:46*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_71:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
|
||||
val_offset:47*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_72:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
|
||||
val_offset:48*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_73:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
|
||||
val_offset:49*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_74:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x8;
|
||||
val_offset:50*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_75:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
|
||||
val_offset:51*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_76:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
|
||||
val_offset:52*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_77:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x40 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
|
||||
val_offset:53*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_78:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x60 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
|
||||
val_offset:54*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_79:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x80 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x8;
|
||||
val_offset:55*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_80:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x20 and rm_val == 7
|
||||
/* opcode: fcvtmod.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x8;
|
||||
val_offset:56*FLEN/8; rmval:rtz; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvtmod.w.d, x31, f31, rtz, 32, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(4593818355633981080,64,FLEN)
|
||||
NAN_BOXED(4593818355633981080,64,FLEN)
|
||||
NAN_BOXED(4593818355633981080,64,FLEN)
|
||||
NAN_BOXED(4593818355633981080,64,FLEN)
|
||||
NAN_BOXED(4593818355633981080,64,FLEN)
|
||||
NAN_BOXED(4593818355633981081,64,FLEN)
|
||||
NAN_BOXED(4593818355633981081,64,FLEN)
|
||||
NAN_BOXED(4593818355633981081,64,FLEN)
|
||||
NAN_BOXED(4593818355633981081,64,FLEN)
|
||||
NAN_BOXED(4593818355633981081,64,FLEN)
|
||||
NAN_BOXED(4593818355633981082,64,FLEN)
|
||||
NAN_BOXED(4593818355633981082,64,FLEN)
|
||||
NAN_BOXED(4593818355633981082,64,FLEN)
|
||||
NAN_BOXED(4593818355633981082,64,FLEN)
|
||||
NAN_BOXED(4593818355633981082,64,FLEN)
|
||||
NAN_BOXED(4593818355633981083,64,FLEN)
|
||||
NAN_BOXED(4593818355633981083,64,FLEN)
|
||||
NAN_BOXED(4593818355633981083,64,FLEN)
|
||||
NAN_BOXED(4593818355633981083,64,FLEN)
|
||||
NAN_BOXED(4593818355633981083,64,FLEN)
|
||||
NAN_BOXED(4593818355633981084,64,FLEN)
|
||||
NAN_BOXED(4593818355633981084,64,FLEN)
|
||||
NAN_BOXED(4593818355633981084,64,FLEN)
|
||||
NAN_BOXED(4593818355633981084,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(4593818355633981084,64,FLEN)
|
||||
NAN_BOXED(4593818355633981085,64,FLEN)
|
||||
NAN_BOXED(4593818355633981085,64,FLEN)
|
||||
NAN_BOXED(4593818355633981085,64,FLEN)
|
||||
NAN_BOXED(4593818355633981085,64,FLEN)
|
||||
NAN_BOXED(4593818355633981085,64,FLEN)
|
||||
NAN_BOXED(4593818355633981086,64,FLEN)
|
||||
NAN_BOXED(4593818355633981086,64,FLEN)
|
||||
NAN_BOXED(4593818355633981086,64,FLEN)
|
||||
NAN_BOXED(4593818355633981086,64,FLEN)
|
||||
NAN_BOXED(4593818355633981086,64,FLEN)
|
||||
NAN_BOXED(4593818355633981087,64,FLEN)
|
||||
NAN_BOXED(4593818355633981087,64,FLEN)
|
||||
NAN_BOXED(4593818355633981087,64,FLEN)
|
||||
NAN_BOXED(4593818355633981087,64,FLEN)
|
||||
NAN_BOXED(4593818355633981087,64,FLEN)
|
||||
NAN_BOXED(13817190392488756888,64,FLEN)
|
||||
NAN_BOXED(13817190392488756888,64,FLEN)
|
||||
NAN_BOXED(13817190392488756888,64,FLEN)
|
||||
NAN_BOXED(13817190392488756888,64,FLEN)
|
||||
NAN_BOXED(13817190392488756888,64,FLEN)
|
||||
NAN_BOXED(13817190392488756889,64,FLEN)
|
||||
NAN_BOXED(13817190392488756889,64,FLEN)
|
||||
NAN_BOXED(13817190392488756889,64,FLEN)
|
||||
NAN_BOXED(13817190392488756889,64,FLEN)
|
||||
NAN_BOXED(13817190392488756889,64,FLEN)
|
||||
NAN_BOXED(13817190392488756890,64,FLEN)
|
||||
NAN_BOXED(13817190392488756890,64,FLEN)
|
||||
NAN_BOXED(13817190392488756890,64,FLEN)
|
||||
NAN_BOXED(13817190392488756890,64,FLEN)
|
||||
NAN_BOXED(13817190392488756890,64,FLEN)
|
||||
NAN_BOXED(13817190392488756891,64,FLEN)
|
||||
NAN_BOXED(13817190392488756891,64,FLEN)
|
||||
NAN_BOXED(13817190392488756891,64,FLEN)
|
||||
NAN_BOXED(13817190392488756891,64,FLEN)
|
||||
NAN_BOXED(13817190392488756891,64,FLEN)
|
||||
NAN_BOXED(13817190392488756892,64,FLEN)
|
||||
NAN_BOXED(13817190392488756892,64,FLEN)
|
||||
NAN_BOXED(13817190392488756892,64,FLEN)
|
||||
NAN_BOXED(13817190392488756892,64,FLEN)
|
||||
NAN_BOXED(13817190392488756892,64,FLEN)
|
||||
NAN_BOXED(13817190392488756893,64,FLEN)
|
||||
NAN_BOXED(13817190392488756893,64,FLEN)
|
||||
NAN_BOXED(13817190392488756893,64,FLEN)
|
||||
NAN_BOXED(13817190392488756893,64,FLEN)
|
||||
NAN_BOXED(13817190392488756893,64,FLEN)
|
||||
NAN_BOXED(13817190392488756894,64,FLEN)
|
||||
NAN_BOXED(13817190392488756894,64,FLEN)
|
||||
NAN_BOXED(13817190392488756894,64,FLEN)
|
||||
NAN_BOXED(13817190392488756894,64,FLEN)
|
||||
NAN_BOXED(13817190392488756894,64,FLEN)
|
||||
NAN_BOXED(13817190392488756895,64,FLEN)
|
||||
NAN_BOXED(13817190392488756895,64,FLEN)
|
||||
NAN_BOXED(13817190392488756895,64,FLEN)
|
||||
NAN_BOXED(13817190392488756895,64,FLEN)
|
||||
NAN_BOXED(13817190392488756895,64,FLEN)
|
||||
NAN_BOXED(4593818355633981086,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 108*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,368 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:12:39 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.s.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fleq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f29; op2:f29; dest:x30; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f30; op2:f31; dest:x29; op1val:0x0; op2val:0x1;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x80000001;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x807ffffe;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0x7fffff;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x807fffff;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x800000;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x80800000;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x800001;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x80855555;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xff7fffff;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7f800000;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xff800000;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7fc00000;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xffc00000;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7fc00001;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xffc55555;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7f800001;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xffaaaaaa;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3f800000;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x9,test_dataset_1)
|
||||
|
||||
inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf800000;
|
||||
valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
|
||||
|
||||
inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f7; op2:f8; dest:x7; op1val:0x80000000; op2val:0x0;
|
||||
valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f6; op2:f5; dest:x6; op1val:0x80000000; op2val:0x80000000;
|
||||
valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
|
||||
RVTEST_SIGBASE(x6,signature_x6_0)
|
||||
|
||||
inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f5; op2:f6; dest:x5; op1val:0x80000000; op2val:0x1;
|
||||
valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f4; op2:f3; dest:x4; op1val:0x80000000; op2val:0x80000001;
|
||||
valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f3; op2:f4; dest:x3; op1val:0x80000000; op2val:0x2;
|
||||
valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f2; op2:f1; dest:x2; op1val:0x80000000; op2val:0x807ffffe;
|
||||
valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f1; op2:f2; dest:x1; op1val:0x80000000; op2val:0x7fffff;
|
||||
valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f0; op2:f31; dest:x31; op1val:0x80000000; op2val:0x807fffff;
|
||||
valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f31; op2:f0; dest:x31; op1val:0x80000000; op2val:0x800000;
|
||||
valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_33:// rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f31; op2:f30; dest:x0; op1val:0x80000000; op2val:0x80800000;
|
||||
valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(1,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2147483649,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2155872254,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(8388607,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2155872255,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(8388608,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2155872256,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(8388609,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2156221781,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4286578687,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2139095040,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4286578688,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2143289344,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4290772992,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2143289345,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4291122517,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2139095041,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4289374890,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(1065353216,32,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(3212836864,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(1,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2147483649,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2155872254,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(8388607,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2155872255,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(8388608,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2155872256,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 52*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x6_0:
|
||||
.fill 16*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,368 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:12:39 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fleq.s.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fleq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fleq_b19 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fleq_b19)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7e36c1bf; op2val:0x7e36c1bf;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f29; op2:f29; dest:x30; op1val:0x7e36c1bf; op2val:0x7e36c1bf;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x4038a5 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f30; op2:f31; dest:x29; op1val:0x7f7fffff; op2val:0x7d4038a5;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0xfa and fm1 == 0x4038a5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f28; op2:f27; dest:x28; op1val:0x7d4038a5; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x7046ce and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f27; op2:f28; dest:x27; op1val:0x7f7fffff; op2val:0x7ef046ce;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f26; op2:f25; dest:x26; op1val:0x7e36c1bf; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfc and fm2 == 0x472f12 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f25; op2:f26; dest:x25; op1val:0x7e36c1bf; op2val:0x7e472f12;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0xfc and fm1 == 0x472f12 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f24; op2:f23; dest:x24; op1val:0x7e472f12; op2val:0x7e36c1bf;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f23; op2:f24; dest:x23; op1val:0x7e36c1bf; op2val:0x7f2099c0;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x007b00 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f22; op2:f21; dest:x22; op1val:0x7f7fffff; op2val:0x7d807b00;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0xfb and fm1 == 0x007b00 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f21; op2:f22; dest:x21; op1val:0x7d807b00; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2099c0 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f20; op2:f19; dest:x20; op1val:0x7f7fffff; op2val:0x7f2099c0;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f19; op2:f20; dest:x19; op1val:0x7e36c1bf; op2val:0x7ef3c956;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x430778 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f18; op2:f17; dest:x18; op1val:0x7f7fffff; op2val:0x7d430778;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0xfa and fm1 == 0x430778 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f17; op2:f18; dest:x17; op1val:0x7d430778; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x73c956 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f16; op2:f15; dest:x16; op1val:0x7f7fffff; op2val:0x7ef3c956;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f15; op2:f16; dest:x15; op1val:0x7e36c1bf; op2val:0xfeaf0416;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x0c0345 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f14; op2:f13; dest:x14; op1val:0x7f7fffff; op2val:0xfd0c0345;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 1 and fe1 == 0xfa and fm1 == 0x0c0345 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f13; op2:f14; dest:x13; op1val:0xfd0c0345; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0416 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f12; op2:f11; dest:x12; op1val:0x7f7fffff; op2val:0xfeaf0416;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f11; op2:f12; dest:x11; op1val:0x7e36c1bf; op2val:0xff336b1f;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x0f88e6 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f10; op2:f9; dest:x10; op1val:0x7f7fffff; op2val:0xfd8f88e6;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 1 and fe1 == 0xfb and fm1 == 0x0f88e6 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f9; op2:f10; dest:x9; op1val:0xfd8f88e6; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x9,test_dataset_1)
|
||||
|
||||
inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x336b1f and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f8; op2:f7; dest:x8; op1val:0x7f7fffff; op2val:0xff336b1f;
|
||||
valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
|
||||
|
||||
inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f7; op2:f8; dest:x7; op1val:0x7e36c1bf; op2val:0xff130229;
|
||||
valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x6b36a9 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f6; op2:f5; dest:x6; op1val:0x7f7fffff; op2val:0xfd6b36a9;
|
||||
valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
|
||||
RVTEST_SIGBASE(x6,signature_x6_0)
|
||||
|
||||
inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0xfa and fm1 == 0x6b36a9 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f5; op2:f6; dest:x5; op1val:0xfd6b36a9; op2val:0x7f7fffff;
|
||||
valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x130229 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f4; op2:f3; dest:x4; op1val:0x7f7fffff; op2val:0xff130229;
|
||||
valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f3; op2:f4; dest:x3; op1val:0x7e36c1bf; op2val:0xfec91492;
|
||||
valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x20dd41 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f2; op2:f1; dest:x2; op1val:0x7f7fffff; op2val:0xfd20dd41;
|
||||
valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0xfa and fm1 == 0x20dd41 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f1; op2:f2; dest:x1; op1val:0xfd20dd41; op2val:0x7f7fffff;
|
||||
valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_31:// rs1==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x491492 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f0; op2:f31; dest:x31; op1val:0x7f7fffff; op2val:0xfec91492;
|
||||
valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_32:// rs2==f0,fs1 == 0 and fe1 == 0xfc and fm1 == 0x36c1bf and fs2 == 1 and fe2 == 0xfb and fm2 == 0x4aaeb1 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f31; op2:f0; dest:x31; op1val:0x7e36c1bf; op2val:0xfdcaaeb1;
|
||||
valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_33:// rd==x0,fs1 == 1 and fe1 == 0xfb and fm1 == 0x4aaeb1 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x36c1bf and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fleq.s ; op1:f31; op2:f30; dest:x0; op1val:0xfdcaaeb1; op2val:0x7e36c1bf;
|
||||
valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fleq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2101360805,32,FLEN)
|
||||
NAN_BOXED(2101360805,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2129675982,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(2118594322,32,FLEN)
|
||||
NAN_BOXED(2118594322,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(2132842944,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2105572096,32,FLEN)
|
||||
NAN_BOXED(2105572096,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2132842944,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(2129906006,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2101544824,32,FLEN)
|
||||
NAN_BOXED(2101544824,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2129906006,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(4272882710,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4245422917,32,FLEN)
|
||||
NAN_BOXED(4245422917,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4272882710,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(4281559839,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4254042342,32,FLEN)
|
||||
NAN_BOXED(4254042342,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4281559839,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(4279435817,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4251661993,32,FLEN)
|
||||
NAN_BOXED(4251661993,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4279435817,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(4274590866,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4246789441,32,FLEN)
|
||||
NAN_BOXED(4246789441,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4274590866,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
NAN_BOXED(4257918641,32,FLEN)
|
||||
NAN_BOXED(4257918641,32,FLEN)
|
||||
NAN_BOXED(2117517759,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 52*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x6_0:
|
||||
.fill 16*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,204 @@
|
|||
// Copyright (c) 2023. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fli.d instruction
|
||||
// for the following ISA configurations:
|
||||
// * RV32ID_Zfa
|
||||
// * RV64ID_Zfa
|
||||
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
|
||||
RVTEST_ISA("RV32ID_Zfa,RV64ID_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
|
||||
RVMODEL_BOOT
|
||||
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fli.d)
|
||||
|
||||
// Registers with a special purpose
|
||||
#define SIG_BASEREG x1
|
||||
#define FCSR_REG x2
|
||||
#define DATA_BASEREG x3
|
||||
|
||||
// Initialize the FPU
|
||||
RVTEST_FP_ENABLE()
|
||||
// Prepare the DATA_BASEREG register
|
||||
RVTEST_VALBASEUPD(DATA_BASEREG, dataset_tc1)
|
||||
// Prepare the SIG_BASEREG register
|
||||
RVTEST_SIGBASE(SIG_BASEREG, signature_tc1)
|
||||
|
||||
// FLI.D loads a pre-defined constant into a FP register.
|
||||
// FLI.D has the following inputs and outputs:
|
||||
// - input rs1: 5-bit immediate holding the constants ID
|
||||
// - output fld: FP register
|
||||
|
||||
// TEST_CASE_FLI_D executes a FLI.D insn and stores the result in the sig
|
||||
// 1) the FCSR_OLD value will be store into FCSR using FCSR_REG
|
||||
// 2) fli.d is executed using FLD as dest register and FLI_CONST as constant
|
||||
// 3) The constents of FLD and FCSR are stored in the signature
|
||||
#define TEST_CASE_FLI_D(fld, fli_const, fcsr_old, fcsr_reg) \
|
||||
li fcsr_reg, fcsr_old ;\
|
||||
csrw fcsr, fcsr_reg ;\
|
||||
fli.d fld, fli_const ;\
|
||||
csrr fcsr_reg, fcsr ;\
|
||||
RVTEST_SIGUPD_F(SIG_BASEREG, fld, fcsr_reg) ;\
|
||||
|
||||
// Below we have one instruction test per constant
|
||||
|
||||
inst_0:
|
||||
TEST_CASE_FLI_D(f16, -0x1p+0, 0, FCSR_REG)
|
||||
|
||||
inst_1:
|
||||
TEST_CASE_FLI_D(f17, min, 0, FCSR_REG)
|
||||
|
||||
inst_2:
|
||||
TEST_CASE_FLI_D(f18, 0x1p-16, 0, FCSR_REG)
|
||||
|
||||
inst_3:
|
||||
TEST_CASE_FLI_D(f19, 0x1p-15, 0, FCSR_REG)
|
||||
|
||||
inst_4:
|
||||
TEST_CASE_FLI_D(f20, 0x1p-8, 0, FCSR_REG)
|
||||
|
||||
inst_5:
|
||||
TEST_CASE_FLI_D(f21, 0x1p-7, 0, FCSR_REG)
|
||||
|
||||
inst_6:
|
||||
TEST_CASE_FLI_D(f22, 0x1p-4, 0, FCSR_REG)
|
||||
|
||||
inst_7:
|
||||
TEST_CASE_FLI_D(f23, 0x1p-3, 0, FCSR_REG)
|
||||
|
||||
inst_8:
|
||||
TEST_CASE_FLI_D(f24, 0x1p-2, 0, FCSR_REG)
|
||||
|
||||
inst_9:
|
||||
TEST_CASE_FLI_D(f25, 0x1.4p-2, 0, FCSR_REG)
|
||||
|
||||
inst_10:
|
||||
TEST_CASE_FLI_D(f26, 0x1.8p-2, 0, FCSR_REG)
|
||||
|
||||
inst_11:
|
||||
TEST_CASE_FLI_D(f27, 0x1.cp-2, 0, FCSR_REG)
|
||||
|
||||
inst_12:
|
||||
TEST_CASE_FLI_D(f28, 0x1p-1, 0, FCSR_REG)
|
||||
|
||||
inst_13:
|
||||
TEST_CASE_FLI_D(f29, 0x1.4p-1, 0, FCSR_REG)
|
||||
|
||||
inst_14:
|
||||
TEST_CASE_FLI_D(f30, 0x1.8p-1, 0, FCSR_REG)
|
||||
|
||||
inst_15:
|
||||
TEST_CASE_FLI_D(f31, 0x1.cp-1, 0, FCSR_REG)
|
||||
|
||||
inst_16:
|
||||
TEST_CASE_FLI_D(f0, 0x1p0, 0, FCSR_REG)
|
||||
|
||||
inst_17:
|
||||
TEST_CASE_FLI_D(f1, 0x1.4p+0, 0, FCSR_REG)
|
||||
|
||||
inst_18:
|
||||
TEST_CASE_FLI_D(f2, 0x1.8p+0, 0, FCSR_REG)
|
||||
|
||||
inst_19:
|
||||
TEST_CASE_FLI_D(f3, 0x1.cp+0, 0, FCSR_REG)
|
||||
|
||||
inst_20:
|
||||
TEST_CASE_FLI_D(f4, 0x1p+1, 0, FCSR_REG)
|
||||
|
||||
inst_21:
|
||||
TEST_CASE_FLI_D(f5, 0x1.4p+1, 0, FCSR_REG)
|
||||
|
||||
inst_22:
|
||||
TEST_CASE_FLI_D(f6, 0x1.8p+1, 0, FCSR_REG)
|
||||
|
||||
inst_23:
|
||||
TEST_CASE_FLI_D(f7, 0x1p+2, 0, FCSR_REG)
|
||||
|
||||
inst_24:
|
||||
TEST_CASE_FLI_D(f8, 0x1p+3, 0, FCSR_REG)
|
||||
|
||||
inst_25:
|
||||
TEST_CASE_FLI_D(f9, 0x1p+4, 0, FCSR_REG)
|
||||
|
||||
inst_26:
|
||||
TEST_CASE_FLI_D(f10, 0x1p+7, 0, FCSR_REG)
|
||||
|
||||
inst_27:
|
||||
TEST_CASE_FLI_D(f11, 0x1p+8, 0, FCSR_REG)
|
||||
|
||||
inst_28:
|
||||
TEST_CASE_FLI_D(f12, 0x1p+15, 0, FCSR_REG)
|
||||
|
||||
inst_29:
|
||||
TEST_CASE_FLI_D(f13, 0x1p+16, 0, FCSR_REG)
|
||||
|
||||
inst_30:
|
||||
TEST_CASE_FLI_D(f14, inf, 0, FCSR_REG)
|
||||
|
||||
inst_31:
|
||||
TEST_CASE_FLI_D(f15, nan, 0, FCSR_REG)
|
||||
|
||||
#endif // TEST_CASE_1
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.word 0xbabecafe // trapreg_sv
|
||||
.word 0xabecafeb // tramptbl_sv
|
||||
.word 0xbecafeba // mtvec_save
|
||||
.word 0xecafebab // mscratch_save
|
||||
dataset_tc1:
|
||||
/* empty */
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
signature_tc1:
|
||||
// We have 32 test cases and store for each test case:
|
||||
// - 32-bit FP register (fld)
|
||||
// - 32-bit FCSR content after the instruction
|
||||
.fill 64*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
mtrap_sigptr:
|
||||
.fill 64*(XLEN/32),4,0xdeadbeef
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
|
||||
#endif // rvtest_mtrap_routine
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif // rvtest_gpr_save
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,368 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:16:00 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.s.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fltq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fltq_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f29; op2:f29; dest:x30; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f30; op2:f31; dest:x29; op1val:0x0; op2val:0x1;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f28; op2:f27; dest:x28; op1val:0x0; op2val:0x80000001;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f27; op2:f28; dest:x27; op1val:0x0; op2val:0x2;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f26; op2:f25; dest:x26; op1val:0x0; op2val:0x807ffffe;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f25; op2:f26; dest:x25; op1val:0x0; op2val:0x7fffff;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f24; op2:f23; dest:x24; op1val:0x0; op2val:0x807fffff;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f23; op2:f24; dest:x23; op1val:0x0; op2val:0x800000;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f22; op2:f21; dest:x22; op1val:0x0; op2val:0x80800000;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f21; op2:f22; dest:x21; op1val:0x0; op2val:0x800001;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f20; op2:f19; dest:x20; op1val:0x0; op2val:0x80855555;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f19; op2:f20; dest:x19; op1val:0x0; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f18; op2:f17; dest:x18; op1val:0x0; op2val:0xff7fffff;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f17; op2:f18; dest:x17; op1val:0x0; op2val:0x7f800000;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f16; op2:f15; dest:x16; op1val:0x0; op2val:0xff800000;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f15; op2:f16; dest:x15; op1val:0x0; op2val:0x7fc00000;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f14; op2:f13; dest:x14; op1val:0x0; op2val:0xffc00000;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f13; op2:f14; dest:x13; op1val:0x0; op2val:0x7fc00001;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f12; op2:f11; dest:x12; op1val:0x0; op2val:0xffc55555;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f11; op2:f12; dest:x11; op1val:0x0; op2val:0x7f800001;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f10; op2:f9; dest:x10; op1val:0x0; op2val:0xffaaaaaa;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f9; op2:f10; dest:x9; op1val:0x0; op2val:0x3f800000;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x9,test_dataset_1)
|
||||
|
||||
inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f8; op2:f7; dest:x8; op1val:0x0; op2val:0xbf800000;
|
||||
valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
|
||||
|
||||
inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f7; op2:f8; dest:x7; op1val:0x80000000; op2val:0x0;
|
||||
valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f6; op2:f5; dest:x6; op1val:0x80000000; op2val:0x80000000;
|
||||
valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
|
||||
RVTEST_SIGBASE(x6,signature_x6_0)
|
||||
|
||||
inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f5; op2:f6; dest:x5; op1val:0x80000000; op2val:0x1;
|
||||
valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f4; op2:f3; dest:x4; op1val:0x80000000; op2val:0x80000001;
|
||||
valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f3; op2:f4; dest:x3; op1val:0x80000000; op2val:0x2;
|
||||
valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f2; op2:f1; dest:x2; op1val:0x80000000; op2val:0x807ffffe;
|
||||
valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f1; op2:f2; dest:x1; op1val:0x80000000; op2val:0x7fffff;
|
||||
valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_31:// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f0; op2:f31; dest:x31; op1val:0x80000000; op2val:0x807fffff;
|
||||
valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f31; op2:f0; dest:x31; op1val:0x80000000; op2val:0x800000;
|
||||
valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_33:// rd==x0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f31; op2:f30; dest:x0; op1val:0x80000000; op2val:0x80800000;
|
||||
valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(1,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2147483649,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2155872254,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(8388607,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2155872255,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(8388608,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2155872256,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(8388609,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2156221781,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4286578687,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2139095040,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4286578688,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2143289344,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4290772992,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2143289345,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4291122517,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2139095041,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4289374890,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(1065353216,32,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(3212836864,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(1,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2147483649,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2155872254,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(8388607,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2155872255,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(8388608,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2155872256,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 52*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x6_0:
|
||||
.fill 16*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,368 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:16:00 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fltq.s.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fltq.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fltq_b19 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fltq_b19)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1 != rs2, rs1==f31, rs2==f30, rd==x31,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f31; op2:f30; dest:x31; op1val:0x7f378efe; op2val:0x7f378efe;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1 == rs2, rs1==f29, rs2==f29, rd==x30,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x206a70 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f29; op2:f29; dest:x30; op1val:0x7f378efe; op2val:0x7f378efe;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f30, rs2==f31, rd==x29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x206a70 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f30; op2:f31; dest:x29; op1val:0x7f206a70; op2val:0x7f378efe;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x29, f30, f31, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rs2==f27, rd==x28,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfd and fm2 == 0x68aebb and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f28; op2:f27; dest:x28; op1val:0x7f378efe; op2val:0x7ee8aebb;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x28, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rs2==f28, rd==x27,fs1 == 0 and fe1 == 0xfd and fm1 == 0x68aebb and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f27; op2:f28; dest:x27; op1val:0x7ee8aebb; op2val:0x7f378efe;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x27, f27, f28, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rs2==f25, rd==x26,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfd and fm2 == 0x25608b and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f26; op2:f25; dest:x26; op1val:0x7f378efe; op2val:0x7ea5608b;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x26, f26, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rs2==f26, rd==x25,fs1 == 0 and fe1 == 0xfd and fm1 == 0x25608b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f25; op2:f26; dest:x25; op1val:0x7ea5608b; op2val:0x7f378efe;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x25, f25, f26, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rs2==f23, rd==x24,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfe and fm2 == 0x3648af and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f24; op2:f23; dest:x24; op1val:0x7f378efe; op2val:0x7f3648af;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x24, f24, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rs2==f24, rd==x23,fs1 == 0 and fe1 == 0xfe and fm1 == 0x3648af and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f23; op2:f24; dest:x23; op1val:0x7f3648af; op2val:0x7f378efe;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x23, f23, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rs2==f21, rd==x22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f22; op2:f21; dest:x22; op1val:0x7f378efe; op2val:0xfd204621;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x22, f22, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rs2==f22, rd==x21,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfd and fm2 == 0x4857aa and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f21; op2:f22; dest:x21; op1val:0x7d92d8cb; op2val:0xfec857aa;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x21, f21, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rs2==f19, rd==x20,fs1 == 1 and fe1 == 0xfd and fm1 == 0x4857aa and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f20; op2:f19; dest:x20; op1val:0xfec857aa; op2val:0x7d92d8cb;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x20, f20, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rs2==f20, rd==x19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfa and fm2 == 0x204621 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f19; op2:f20; dest:x19; op1val:0x7d92d8cb; op2val:0xfd204621;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x19, f19, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rs2==f17, rd==x18,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f18; op2:f17; dest:x18; op1val:0x7f378efe; op2val:0x7d92d8cb;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x18, f18, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rs2==f18, rd==x17,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f17; op2:f18; dest:x17; op1val:0x7f378efe; op2val:0xfe4ac669;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x17, f17, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rs2==f15, rd==x16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f16; op2:f15; dest:x16; op1val:0x7d92d8cb; op2val:0xff7fffff;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x16, f16, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rs2==f16, rd==x15,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x12d8cb and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f15; op2:f16; dest:x15; op1val:0xff7fffff; op2val:0x7d92d8cb;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x15, f15, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rs2==f13, rd==x14,fs1 == 0 and fe1 == 0xfb and fm1 == 0x12d8cb and fs2 == 1 and fe2 == 0xfc and fm2 == 0x4ac669 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f14; op2:f13; dest:x14; op1val:0x7d92d8cb; op2val:0xfe4ac669;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x14, f14, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rs2==f14, rd==x13,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x16fcf5 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f13; op2:f14; dest:x13; op1val:0x7f378efe; op2val:0xfe96fcf5;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x13, f13, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rs2==f11, rd==x12,fs1 == 1 and fe1 == 0xfd and fm1 == 0x16fcf5 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f12; op2:f11; dest:x12; op1val:0xfe96fcf5; op2val:0x7f378efe;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x12, f12, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rs2==f12, rd==x11,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x68e23e and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f11; op2:f12; dest:x11; op1val:0x7f378efe; op2val:0xfee8e23e;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x11, f11, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rs2==f9, rd==x10,fs1 == 1 and fe1 == 0xfd and fm1 == 0x68e23e and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f10; op2:f9; dest:x10; op1val:0xfee8e23e; op2val:0x7f378efe;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x10, f10, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rs2==f10, rd==x9,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 1 and fe2 == 0xfd and fm2 == 0x2f0937 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f9; op2:f10; dest:x9; op1val:0x7f378efe; op2val:0xfeaf0937;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x9, f9, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x9,test_dataset_1)
|
||||
|
||||
inst_23:// rs1==f8, rs2==f7, rd==x8,fs1 == 1 and fe1 == 0xfd and fm1 == 0x2f0937 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x378efe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f8; op2:f7; dest:x8; op1val:0xfeaf0937; op2val:0x7f378efe;
|
||||
valaddr_reg:x9; val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x8, f8, f7, 0, 0, x9, 0*FLEN/8, x10, x1, x2)
|
||||
|
||||
inst_24:// rs1==f7, rs2==f8, rd==x7,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f7; op2:f8; dest:x7; op1val:0x7f378efe; op2val:0x39e8a;
|
||||
valaddr_reg:x9; val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x7, f7, f8, 0, 0, x9, 2*FLEN/8, x10, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rs2==f5, rd==x6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a825 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7a0dff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f6; op2:f5; dest:x6; op1val:0x2a825; op2val:0x7f7a0dff;
|
||||
valaddr_reg:x9; val_offset:4*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x6, f6, f5, 0, 0, x9, 4*FLEN/8, x10, x1, x7)
|
||||
RVTEST_SIGBASE(x6,signature_x6_0)
|
||||
|
||||
inst_26:// rs1==f5, rs2==f6, rd==x5,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7a0dff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a825 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f5; op2:f6; dest:x5; op1val:0x7f7a0dff; op2val:0x2a825;
|
||||
valaddr_reg:x9; val_offset:6*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x5, f5, f6, 0, 0, x9, 6*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_27:// rs1==f4, rs2==f3, rd==x4,fs1 == 0 and fe1 == 0x00 and fm1 == 0x02a825 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x039e8a and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f4; op2:f3; dest:x4; op1val:0x2a825; op2val:0x39e8a;
|
||||
valaddr_reg:x9; val_offset:8*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x4, f4, f3, 0, 0, x9, 8*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_28:// rs1==f3, rs2==f4, rd==x3,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02a825 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f3; op2:f4; dest:x3; op1val:0x7f378efe; op2val:0x2a825;
|
||||
valaddr_reg:x9; val_offset:10*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x3, f3, f4, 0, 0, x9, 10*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_29:// rs1==f2, rs2==f1, rd==x2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f2; op2:f1; dest:x2; op1val:0x7f378efe; op2val:0x2adcdc;
|
||||
valaddr_reg:x9; val_offset:12*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x2, f2, f1, 0, 0, x9, 12*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_30:// rs1==f1, rs2==f2, rd==x1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f1; op2:f2; dest:x1; op1val:0x1a917b; op2val:0x7f7fffff;
|
||||
valaddr_reg:x9; val_offset:14*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x1, f1, f2, 0, 0, x9, 14*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_31:// rs1==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f0; op2:f31; dest:x31; op1val:0x7f7fffff; op2val:0x1a917b;
|
||||
valaddr_reg:x9; val_offset:16*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x31, f0, f31, 0, 0, x9, 16*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_32:// rs2==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x1a917b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x2adcdc and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f31; op2:f0; dest:x31; op1val:0x1a917b; op2val:0x2adcdc;
|
||||
valaddr_reg:x9; val_offset:18*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x31, f31, f0, 0, 0, x9, 18*FLEN/8, x10, x6, x7)
|
||||
|
||||
inst_33:// rd==x0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x378efe and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1a917b and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fltq.s ; op1:f31; op2:f30; dest:x0; op1val:0x7f378efe; op2val:0x1a917b;
|
||||
valaddr_reg:x9; val_offset:20*FLEN/8; correctval:??; testreg:x7;
|
||||
fcsr_val: 0*/
|
||||
TEST_FCMP_OP(fltq.s, x0, f31, f30, 0, 0, x9, 20*FLEN/8, x10, x6, x7)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2132830832,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2129178299,32,FLEN)
|
||||
NAN_BOXED(2129178299,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2124767371,32,FLEN)
|
||||
NAN_BOXED(2124767371,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2134263983,32,FLEN)
|
||||
NAN_BOXED(2134263983,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(4246750753,32,FLEN)
|
||||
NAN_BOXED(2106775755,32,FLEN)
|
||||
NAN_BOXED(4274542506,32,FLEN)
|
||||
NAN_BOXED(4274542506,32,FLEN)
|
||||
NAN_BOXED(2106775755,32,FLEN)
|
||||
NAN_BOXED(2106775755,32,FLEN)
|
||||
NAN_BOXED(4246750753,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2106775755,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(4266313321,32,FLEN)
|
||||
NAN_BOXED(2106775755,32,FLEN)
|
||||
NAN_BOXED(4286578687,32,FLEN)
|
||||
NAN_BOXED(4286578687,32,FLEN)
|
||||
NAN_BOXED(2106775755,32,FLEN)
|
||||
NAN_BOXED(2106775755,32,FLEN)
|
||||
NAN_BOXED(4266313321,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(4271308021,32,FLEN)
|
||||
NAN_BOXED(4271308021,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(4276675134,32,FLEN)
|
||||
NAN_BOXED(4276675134,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(4272884023,32,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(4272884023,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(237194,32,FLEN)
|
||||
NAN_BOXED(174117,32,FLEN)
|
||||
NAN_BOXED(2138705407,32,FLEN)
|
||||
NAN_BOXED(2138705407,32,FLEN)
|
||||
NAN_BOXED(174117,32,FLEN)
|
||||
NAN_BOXED(174117,32,FLEN)
|
||||
NAN_BOXED(237194,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(174117,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(2809052,32,FLEN)
|
||||
NAN_BOXED(1741179,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(1741179,32,FLEN)
|
||||
NAN_BOXED(1741179,32,FLEN)
|
||||
NAN_BOXED(2809052,32,FLEN)
|
||||
NAN_BOXED(2134347518,32,FLEN)
|
||||
NAN_BOXED(1741179,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 52*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x6_0:
|
||||
.fill 16*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,449 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:05:51 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.s.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fmaxm.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:
|
||||
// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f31; op2:f31; dest:f31; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:
|
||||
// rs1 == rs2 != rd, rs1==f29, rs2==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f29; op2:f29; dest:f30; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:
|
||||
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f30, rs2==f28, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f30; op2:f28; dest:f29; op1val:0x0; op2val:0x1;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f29, f30, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:
|
||||
// rs2 == rd != rs1, rs1==f28, rs2==f27, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f28; op2:f27; dest:f27; op1val:0x0; op2val:0x80000001;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f27, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:
|
||||
// rs1 == rd != rs2, rs1==f26, rs2==f30, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f26; op2:f30; dest:f26; op1val:0x0; op2val:0x2;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f26, f26, f30, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:
|
||||
// rs1==f27, rs2==f26, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f27; op2:f26; dest:f28; op1val:0x0; op2val:0x807ffffe;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f28, f27, f26, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:
|
||||
// rs1==f24, rs2==f23, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f24; op2:f23; dest:f25; op1val:0x0; op2val:0x7fffff;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f25, f24, f23, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:
|
||||
// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f23; op2:f25; dest:f24; op1val:0x0; op2val:0x807fffff;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f24, f23, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:
|
||||
// rs1==f25, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f25; op2:f24; dest:f23; op1val:0x0; op2val:0x800000;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f23, f25, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:
|
||||
// rs1==f21, rs2==f20, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f21; op2:f20; dest:f22; op1val:0x0; op2val:0x80800000;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f22, f21, f20, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:
|
||||
// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x800001;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:
|
||||
// rs1==f22, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f22; op2:f21; dest:f20; op1val:0x0; op2val:0x80855555;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f20, f22, f21, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:
|
||||
// rs1==f18, rs2==f17, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f18; op2:f17; dest:f19; op1val:0x0; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f19, f18, f17, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:
|
||||
// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f17; op2:f19; dest:f18; op1val:0x0; op2val:0xff7fffff;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f18, f17, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:
|
||||
// rs1==f19, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f19; op2:f18; dest:f17; op1val:0x0; op2val:0x7f800000;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f17, f19, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:
|
||||
// rs1==f15, rs2==f14, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f15; op2:f14; dest:f16; op1val:0x0; op2val:0xff800000;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f16, f15, f14, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:
|
||||
// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x7fc00000;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:
|
||||
// rs1==f16, rs2==f15, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f16; op2:f15; dest:f14; op1val:0x0; op2val:0xffc00000;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f14, f16, f15, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:
|
||||
// rs1==f12, rs2==f11, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f12; op2:f11; dest:f13; op1val:0x0; op2val:0x7fc00001;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f13, f12, f11, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:
|
||||
// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f11; op2:f13; dest:f12; op1val:0x0; op2val:0xffc55555;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f12, f11, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:
|
||||
// rs1==f13, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f13; op2:f12; dest:f11; op1val:0x0; op2val:0x7f800001;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f11, f13, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:
|
||||
// rs1==f9, rs2==f8, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f9; op2:f8; dest:f10; op1val:0x0; op2val:0xffaaaaaa;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f10, f9, f8, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:
|
||||
// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x3f800000;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:
|
||||
// rs1==f10, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f10; op2:f9; dest:f8; op1val:0x0; op2val:0xbf800000;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f8, f10, f9, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:
|
||||
// rs1==f6, rs2==f5, rd==f7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f6; op2:f5; dest:f7; op1val:0x80000000; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f7, f6, f5, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:
|
||||
// rs1==f5, rs2==f7, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f5; op2:f7; dest:f6; op1val:0x80000000; op2val:0x80000000;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f6, f5, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:
|
||||
// rs1==f7, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f7; op2:f6; dest:f5; op1val:0x80000000; op2val:0x1;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f5, f7, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:
|
||||
// rs1==f3, rs2==f2, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f3; op2:f2; dest:f4; op1val:0x80000000; op2val:0x80000001;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f4, f3, f2, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:
|
||||
// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f2; op2:f4; dest:f3; op1val:0x80000000; op2val:0x2;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:
|
||||
// rs1==f4, rs2==f3, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f4; op2:f3; dest:f2; op1val:0x80000000; op2val:0x807ffffe;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f2, f4, f3, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:
|
||||
// rs1==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f1; op2:f30; dest:f31; op1val:0x80000000; op2val:0x7fffff;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f31, f1, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:
|
||||
// rs1==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f0; op2:f30; dest:f31; op1val:0x80000000; op2val:0x807fffff;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f31, f0, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:
|
||||
// rs2==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f30; op2:f1; dest:f31; op1val:0x80000000; op2val:0x800000;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f1, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:
|
||||
// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f30; op2:f0; dest:f31; op1val:0x80000000; op2val:0x80800000;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f0, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_34:
|
||||
// rd==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f1; op1val:0x80000000; op2val:0x800001;
|
||||
valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f1, f31, f30, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_35:
|
||||
// rd==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f0; op1val:0x80000000; op2val:0x80855555;
|
||||
valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f0, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(1,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2147483649,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2155872254,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(8388607,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2155872255,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(8388608,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2155872256,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(8388609,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2156221781,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4286578687,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2139095040,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4286578688,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2143289344,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4290772992,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2143289345,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4291122517,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2139095041,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4289374890,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(1065353216,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(3212836864,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(1,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2147483649,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2155872254,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(8388607,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2155872255,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(8388608,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2155872256,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(8388609,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2156221781,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 72*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,449 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:05:51 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmaxm.s.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fmaxm.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fmaxm_b19 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fmaxm_b19)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:
|
||||
// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f31; op2:f31; dest:f31; op1val:0x7dce622b; op2val:0x7dce622b;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f31, f31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:
|
||||
// rs1 == rs2 != rd, rs1==f29, rs2==f29, rd==f30,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f29; op2:f29; dest:f30; op1val:0x7dce622b; op2val:0x7dce622b;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f30, f29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:
|
||||
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f30, rs2==f28, rd==f29,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x183299 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f30; op2:f28; dest:f29; op1val:0x7f7fffff; op2val:0x7d183299;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f29, f30, f28, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:
|
||||
// rs2 == rd != rs1, rs1==f28, rs2==f27, rd==f27,fs1 == 0 and fe1 == 0xfa and fm1 == 0x183299 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f28; op2:f27; dest:f27; op1val:0x7d183299; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f27, f28, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:
|
||||
// rs1 == rd != rs2, rs1==f26, rs2==f30, rd==f26,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfd and fm2 == 0x3e3f3f and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f26; op2:f30; dest:f26; op1val:0x7f7fffff; op2val:0x7ebe3f3f;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f26, f26, f30, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:
|
||||
// rs1==f27, rs2==f26, rd==f28,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f27; op2:f26; dest:f28; op1val:0x7dce622b; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f28, f27, f26, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:
|
||||
// rs1==f24, rs2==f23, rd==f25,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x102b16 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f24; op2:f23; dest:f25; op1val:0x7dce622b; op2val:0x7d902b16;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f25, f24, f23, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:
|
||||
// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0xfb and fm1 == 0x102b16 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f23; op2:f25; dest:f24; op1val:0x7d902b16; op2val:0x7dce622b;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f24, f23, f25, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:
|
||||
// rs1==f25, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f25; op2:f24; dest:f23; op1val:0x7dce622b; op2val:0x7f125b96;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f23, f25, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:
|
||||
// rs1==f21, rs2==f20, rd==f22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfa and fm2 == 0x6a2c24 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f21; op2:f20; dest:f22; op1val:0x7f7fffff; op2val:0x7d6a2c24;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f22, f21, f20, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:
|
||||
// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0xfa and fm1 == 0x6a2c24 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f20; op2:f22; dest:f21; op1val:0x7d6a2c24; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:
|
||||
// rs1==f22, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfe and fm2 == 0x125b96 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f22; op2:f21; dest:f20; op1val:0x7f7fffff; op2val:0x7f125b96;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f20, f22, f21, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:
|
||||
// rs1==f18, rs2==f17, rd==f19,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0xfc and fm2 == 0x2fb07b and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f18; op2:f17; dest:f19; op1val:0x7dce622b; op2val:0x7e2fb07b;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f19, f18, f17, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:
|
||||
// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0xfc and fm1 == 0x2fb07b and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f17; op2:f19; dest:f18; op1val:0x7e2fb07b; op2val:0x7dce622b;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f18, f17, f19, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:
|
||||
// rs1==f19, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfb and fm2 == 0x6a577e and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f19; op2:f18; dest:f17; op1val:0x7dce622b; op2val:0xfdea577e;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f17, f19, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:
|
||||
// rs1==f15, rs2==f14, rd==f16,fs1 == 1 and fe1 == 0xfb and fm1 == 0x6a577e and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f15; op2:f14; dest:f16; op1val:0xfdea577e; op2val:0x7dce622b;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f16, f15, f14, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:
|
||||
// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f14; op2:f16; dest:f15; op1val:0x7dce622b; op2val:0xfed3653a;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:
|
||||
// rs1==f16, rs2==f15, rd==f14,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfa and fm2 == 0x291dc8 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f16; op2:f15; dest:f14; op1val:0x7f7fffff; op2val:0xfd291dc8;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f14, f16, f15, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:
|
||||
// rs1==f12, rs2==f11, rd==f13,fs1 == 1 and fe1 == 0xfa and fm1 == 0x291dc8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f12; op2:f11; dest:f13; op1val:0xfd291dc8; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f13, f12, f11, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:
|
||||
// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfd and fm2 == 0x53653a and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f11; op2:f13; dest:f12; op1val:0x7f7fffff; op2val:0xfed3653a;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f12, f11, f13, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:
|
||||
// rs1==f13, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f13; op2:f12; dest:f11; op1val:0x7dce622b; op2val:0xff3a8ea9;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f11, f13, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:
|
||||
// rs1==f9, rs2==f8, rd==f10,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x153eee and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f9; op2:f8; dest:f10; op1val:0x7f7fffff; op2val:0xfd953eee;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f10, f9, f8, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:
|
||||
// rs1==f8, rs2==f10, rd==f9,fs1 == 1 and fe1 == 0xfb and fm1 == 0x153eee and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f8; op2:f10; dest:f9; op1val:0xfd953eee; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:
|
||||
// rs1==f10, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3a8ea9 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f10; op2:f9; dest:f8; op1val:0x7f7fffff; op2val:0xff3a8ea9;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f8, f10, f9, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:
|
||||
// rs1==f6, rs2==f5, rd==f7,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f6; op2:f5; dest:f7; op1val:0x7dce622b; op2val:0xff3f987b;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f7, f6, f5, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:
|
||||
// rs1==f5, rs2==f7, rd==f6,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfb and fm2 == 0x1946c8 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f5; op2:f7; dest:f6; op1val:0x7f7fffff; op2val:0xfd9946c8;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f6, f5, f7, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:
|
||||
// rs1==f7, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0xfb and fm1 == 0x1946c8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f7; op2:f6; dest:f5; op1val:0xfd9946c8; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f5, f7, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:
|
||||
// rs1==f3, rs2==f2, rd==f4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 1 and fe2 == 0xfe and fm2 == 0x3f987b and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f3; op2:f2; dest:f4; op1val:0x7f7fffff; op2val:0xff3f987b;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f4, f3, f2, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:
|
||||
// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 1 and fe2 == 0xfa and fm2 == 0x2820df and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f2; op2:f4; dest:f3; op1val:0x7dce622b; op2val:0xfd2820df;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:
|
||||
// rs1==f4, rs2==f3, rd==f2,fs1 == 1 and fe1 == 0xfa and fm1 == 0x2820df and fs2 == 0 and fe2 == 0xfb and fm2 == 0x4e622b and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f4; op2:f3; dest:f2; op1val:0xfd2820df; op2val:0x7dce622b;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f2, f4, f3, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:
|
||||
// rs1==f1,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f1; op2:f30; dest:f31; op1val:0x7dce622b; op2val:0x30e1ae;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f31, f1, f30, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:
|
||||
// rs1==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x07167c and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f0; op2:f30; dest:f31; op1val:0x255707; op2val:0x7e07167c;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f31, f0, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:
|
||||
// rs2==f1,fs1 == 0 and fe1 == 0xfc and fm1 == 0x07167c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f30; op2:f1; dest:f31; op1val:0x7e07167c; op2val:0x255707;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f1, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:
|
||||
// rs2==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x255707 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x30e1ae and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f30; op2:f0; dest:f31; op1val:0x255707; op2val:0x30e1ae;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f31, f30, f0, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_34:
|
||||
// rd==f1,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x255707 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f1; op1val:0x7dce622b; op2val:0x255707;
|
||||
valaddr_reg:x3; val_offset:68*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f1, f31, f30, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_35:
|
||||
// rd==f0,fs1 == 0 and fe1 == 0xfb and fm1 == 0x4e622b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x29b3b2 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fmaxm.s ; op1:f31; op2:f30; dest:f0; op1val:0x7dce622b; op2val:0x29b3b2;
|
||||
valaddr_reg:x3; val_offset:70*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fmaxm.s, f0, f31, f30, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2098737817,32,FLEN)
|
||||
NAN_BOXED(2098737817,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2126397247,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2106600214,32,FLEN)
|
||||
NAN_BOXED(2106600214,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2131909526,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2104110116,32,FLEN)
|
||||
NAN_BOXED(2104110116,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2131909526,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2117054587,32,FLEN)
|
||||
NAN_BOXED(2117054587,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(4259993470,32,FLEN)
|
||||
NAN_BOXED(4259993470,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(4275266874,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4247330248,32,FLEN)
|
||||
NAN_BOXED(4247330248,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4275266874,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(4282027689,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4254416622,32,FLEN)
|
||||
NAN_BOXED(4254416622,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4282027689,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(4282357883,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4254680776,32,FLEN)
|
||||
NAN_BOXED(4254680776,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4282357883,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(4247265503,32,FLEN)
|
||||
NAN_BOXED(4247265503,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(3203502,32,FLEN)
|
||||
NAN_BOXED(2447111,32,FLEN)
|
||||
NAN_BOXED(2114393724,32,FLEN)
|
||||
NAN_BOXED(2114393724,32,FLEN)
|
||||
NAN_BOXED(2447111,32,FLEN)
|
||||
NAN_BOXED(2447111,32,FLEN)
|
||||
NAN_BOXED(3203502,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2447111,32,FLEN)
|
||||
NAN_BOXED(2110677547,32,FLEN)
|
||||
NAN_BOXED(2732978,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 72*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,429 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:08:59 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.s.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fminm.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fminm_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:
|
||||
// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f31; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:
|
||||
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f29, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f29; op2:f31; dest:f30; op1val:0x0; op2val:0x80000000;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f30, f29, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:
|
||||
// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f30; op2:f29; dest:f29; op1val:0x0; op2val:0x1;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f29, f30, f29, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:
|
||||
// rs1 == rs2 != rd, rs1==f27, rs2==f27, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f27; op2:f27; dest:f28; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f28, f27, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:
|
||||
// rs1 == rs2 == rd, rs1==f26, rs2==f26, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f26; op2:f26; dest:f26; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f26, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:
|
||||
// rs1==f28, rs2==f25, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f28; op2:f25; dest:f27; op1val:0x0; op2val:0x807ffffe;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f27, f28, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:
|
||||
// rs1==f24, rs2==f28, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f24; op2:f28; dest:f25; op1val:0x0; op2val:0x7fffff;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f25, f24, f28, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:
|
||||
// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x807fffff;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:
|
||||
// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x800000;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:
|
||||
// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x80800000;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:
|
||||
// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x800001;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:
|
||||
// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x055555 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x80855555;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:
|
||||
// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:
|
||||
// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0xff7fffff;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:
|
||||
// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x7f800000;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:
|
||||
// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0xff800000;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:
|
||||
// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x7fc00000;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:
|
||||
// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x400000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0xffc00000;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:
|
||||
// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x400001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x7fc00001;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:
|
||||
// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x455555 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0xffc55555;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:
|
||||
// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0xff and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x7f800001;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:
|
||||
// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0xff and fm2 == 0x2aaaaa and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0xffaaaaaa;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:
|
||||
// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x7f and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x3f800000;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:
|
||||
// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x7f and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0xbf800000;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:
|
||||
// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f6; op2:f8; dest:f7; op1val:0x80000000; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:
|
||||
// rs1==f7, rs2==f5, rd==f6,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f7; op2:f5; dest:f6; op1val:0x80000000; op2val:0x80000000;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:
|
||||
// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f4; op2:f6; dest:f5; op1val:0x80000000; op2val:0x1;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:
|
||||
// rs1==f5, rs2==f3, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000001 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f5; op2:f3; dest:f4; op1val:0x80000000; op2val:0x80000001;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:
|
||||
// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000002 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f2; op2:f4; dest:f3; op1val:0x80000000; op2val:0x2;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:
|
||||
// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7ffffe and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f3; op2:f1; dest:f2; op1val:0x80000000; op2val:0x807ffffe;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:
|
||||
// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f0; op2:f2; dest:f1; op1val:0x80000000; op2val:0x7fffff;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:
|
||||
// rs1==f1,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f1; op2:f30; dest:f31; op1val:0x80000000; op2val:0x807fffff;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:
|
||||
// rs2==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 0 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f30; op2:f0; dest:f31; op1val:0x80000000; op2val:0x800000;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:
|
||||
// rd==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fs2 == 1 and fe2 == 0x01 and fm2 == 0x000000 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f31; op2:f30; dest:f0; op1val:0x80000000; op2val:0x80800000;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(1,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2155872254,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(8388607,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2155872255,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(8388608,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2155872256,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(8388609,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2156221781,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4286578687,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2139095040,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4286578688,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2143289344,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4290772992,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2143289345,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4291122517,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2139095041,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(4289374890,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(1065353216,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(3212836864,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(1,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2147483649,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2155872254,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(8388607,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2155872255,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(8388608,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(2155872256,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 68*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,429 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:08:59 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fminm.s.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fminm.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fminm_b19 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fminm_b19)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:
|
||||
// rs1 == rd != rs2, rs1==f31, rs2==f30, rd==f31,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f31; op2:f30; dest:f31; op1val:0x7f222105; op2val:0x7f222105;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f31, f31, f30, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:
|
||||
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f29, rs2==f31, rd==f30,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x445459 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f29; op2:f31; dest:f30; op1val:0x7f222105; op2val:0x7ec45459;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f30, f29, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:
|
||||
// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0xfd and fm1 == 0x445459 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f30; op2:f29; dest:f29; op1val:0x7ec45459; op2val:0x7f222105;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f29, f30, f29, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:
|
||||
// rs1 == rs2 != rd, rs1==f27, rs2==f27, rd==f28,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfd and fm2 == 0x370362 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f27; op2:f27; dest:f28; op1val:0x7f222105; op2val:0x7f222105;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f28, f27, f27, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:
|
||||
// rs1 == rs2 == rd, rs1==f26, rs2==f26, rd==f26,fs1 == 0 and fe1 == 0xfd and fm1 == 0x370362 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f26; op2:f26; dest:f26; op1val:0x7eb70362; op2val:0x7eb70362;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f26, f26, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:
|
||||
// rs1==f28, rs2==f25, rd==f27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f28; op2:f25; dest:f27; op1val:0x7f222105; op2val:0x7e587392;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f27, f28, f25, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:
|
||||
// rs1==f24, rs2==f28, rd==f25,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f24; op2:f28; dest:f25; op1val:0x7d81b404; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f25, f24, f28, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:
|
||||
// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f25; op2:f23; dest:f24; op1val:0x7f7fffff; op2val:0x7d81b404;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f24, f25, f23, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:
|
||||
// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 0 and fe2 == 0xfc and fm2 == 0x587392 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f22; op2:f24; dest:f23; op1val:0x7d81b404; op2val:0x7e587392;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f23, f22, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:
|
||||
// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f23; op2:f21; dest:f22; op1val:0x7f222105; op2val:0x7d81b404;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f22, f23, f21, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:
|
||||
// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x2eabd8 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f20; op2:f22; dest:f21; op1val:0x7f222105; op2val:0x7f2eabd8;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f21, f20, f22, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:
|
||||
// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0xfe and fm1 == 0x2eabd8 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f21; op2:f19; dest:f20; op1val:0x7f2eabd8; op2val:0x7f222105;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f20, f21, f19, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:
|
||||
// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f18; op2:f20; dest:f19; op1val:0x7f222105; op2val:0xfe39e419;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f19, f18, f20, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:
|
||||
// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f19; op2:f17; dest:f18; op1val:0x7d81b404; op2val:0xff7fffff;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f18, f19, f17, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:
|
||||
// rs1==f16, rs2==f18, rd==f17,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xfb and fm2 == 0x01b404 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f16; op2:f18; dest:f17; op1val:0xff7fffff; op2val:0x7d81b404;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f17, f16, f18, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:
|
||||
// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x39e419 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f17; op2:f15; dest:f16; op1val:0x7d81b404; op2val:0xfe39e419;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f16, f17, f15, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:
|
||||
// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x64815a and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f14; op2:f16; dest:f15; op1val:0x7f222105; op2val:0xfee4815a;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f15, f14, f16, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:
|
||||
// rs1==f15, rs2==f13, rd==f14,fs1 == 1 and fe1 == 0xfd and fm1 == 0x64815a and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f15; op2:f13; dest:f14; op1val:0xfee4815a; op2val:0x7f222105;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f14, f15, f13, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:
|
||||
// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfd and fm2 == 0x1ffb35 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f12; op2:f14; dest:f13; op1val:0x7f222105; op2val:0xfe9ffb35;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f13, f12, f14, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:
|
||||
// rs1==f13, rs2==f11, rd==f12,fs1 == 1 and fe1 == 0xfd and fm1 == 0x1ffb35 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x222105 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f13; op2:f11; dest:f12; op1val:0xfe9ffb35; op2val:0x7f222105;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f12, f13, f11, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:
|
||||
// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f10; op2:f12; dest:f11; op1val:0x7f222105; op2val:0xfe3b8ad8;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f11, f10, f12, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:
|
||||
// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0xfb and fm1 == 0x01b404 and fs2 == 1 and fe2 == 0xfc and fm2 == 0x3b8ad8 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f11; op2:f9; dest:f10; op1val:0x7d81b404; op2val:0xfe3b8ad8;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f10, f11, f9, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:
|
||||
// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f8; op2:f10; dest:f9; op1val:0x7f222105; op2val:0xfc538835;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f9, f8, f10, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:
|
||||
// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0xf7 and fm1 == 0x4f866d and fs2 == 1 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f9; op2:f7; dest:f8; op1val:0x7bcf866d; op2val:0xff7fffff;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f8, f9, f7, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:
|
||||
// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x4f866d and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f6; op2:f8; dest:f7; op1val:0xff7fffff; op2val:0x7bcf866d;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f7, f6, f8, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:
|
||||
// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0xf7 and fm1 == 0x4f866d and fs2 == 1 and fe2 == 0xf8 and fm2 == 0x538835 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f7; op2:f5; dest:f6; op1val:0x7bcf866d; op2val:0xfc538835;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f6, f7, f5, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:
|
||||
// rs1==f4, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0xf7 and fm2 == 0x4f866d and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f4; op2:f6; dest:f5; op1val:0x7f222105; op2val:0x7bcf866d;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f5, f4, f6, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:
|
||||
// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f5; op2:f3; dest:f4; op1val:0x7f222105; op2val:0x1aeaa5;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f4, f5, f3, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:
|
||||
// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x39f704 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f2; op2:f4; dest:f3; op1val:0x177770; op2val:0x7f39f704;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f3, f2, f4, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:
|
||||
// rs1==f3, rs2==f1, rd==f2,fs1 == 0 and fe1 == 0xfe and fm1 == 0x39f704 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f3; op2:f1; dest:f2; op1val:0x7f39f704; op2val:0x177770;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f2, f3, f1, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:
|
||||
// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x1aeaa5 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f0; op2:f2; dest:f1; op1val:0x177770; op2val:0x1aeaa5;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f1, f0, f2, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:
|
||||
// rs1==f1,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x177770 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f1; op2:f30; dest:f31; op1val:0x7f222105; op2val:0x177770;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f31, f1, f30, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:
|
||||
// rs2==f0,fs1 == 0 and fe1 == 0xfe and fm1 == 0x222105 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x3229c1 and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f30; op2:f0; dest:f31; op1val:0x7f222105; op2val:0x3229c1;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f31, f30, f0, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:
|
||||
// rd==f0,fs1 == 0 and fe1 == 0x00 and fm1 == 0x177770 and fs2 == 0 and fe2 == 0xfe and fm2 == 0x7fffff and fcsr == 0 and rs1_nan_prefix == 0xffffffff and rs2_nan_prefix == 0xffffffff
|
||||
/* opcode: fminm.s ; op1:f31; op2:f30; dest:f0; op1val:0x177770; op2val:0x7f7fffff;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP_NRM(fminm.s, f0, f31, f30, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2126795865,32,FLEN)
|
||||
NAN_BOXED(2126795865,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2125923170,32,FLEN)
|
||||
NAN_BOXED(2125923170,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2119725970,32,FLEN)
|
||||
NAN_BOXED(2105652228,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(2105652228,32,FLEN)
|
||||
NAN_BOXED(2105652228,32,FLEN)
|
||||
NAN_BOXED(2119725970,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2105652228,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2133765080,32,FLEN)
|
||||
NAN_BOXED(2133765080,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(4265206809,32,FLEN)
|
||||
NAN_BOXED(2105652228,32,FLEN)
|
||||
NAN_BOXED(4286578687,32,FLEN)
|
||||
NAN_BOXED(4286578687,32,FLEN)
|
||||
NAN_BOXED(2105652228,32,FLEN)
|
||||
NAN_BOXED(2105652228,32,FLEN)
|
||||
NAN_BOXED(4265206809,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(4276388186,32,FLEN)
|
||||
NAN_BOXED(4276388186,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(4271897397,32,FLEN)
|
||||
NAN_BOXED(4271897397,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(4265315032,32,FLEN)
|
||||
NAN_BOXED(2105652228,32,FLEN)
|
||||
NAN_BOXED(4265315032,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(4233332789,32,FLEN)
|
||||
NAN_BOXED(2077197933,32,FLEN)
|
||||
NAN_BOXED(4286578687,32,FLEN)
|
||||
NAN_BOXED(4286578687,32,FLEN)
|
||||
NAN_BOXED(2077197933,32,FLEN)
|
||||
NAN_BOXED(2077197933,32,FLEN)
|
||||
NAN_BOXED(4233332789,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(2077197933,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(1764005,32,FLEN)
|
||||
NAN_BOXED(1537904,32,FLEN)
|
||||
NAN_BOXED(2134505220,32,FLEN)
|
||||
NAN_BOXED(2134505220,32,FLEN)
|
||||
NAN_BOXED(1537904,32,FLEN)
|
||||
NAN_BOXED(1537904,32,FLEN)
|
||||
NAN_BOXED(1764005,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(1537904,32,FLEN)
|
||||
NAN_BOXED(2132943109,32,FLEN)
|
||||
NAN_BOXED(3287489,32,FLEN)
|
||||
NAN_BOXED(1537904,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 68*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:48 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0x8000000000000000; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0x8000000000000001; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0x8000000000000002; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0xfffffffffffff; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0x800fffffffffffff; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0x10000000000000; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0x8010000000000000; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0x10000000000002; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0x8010000000000002; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0x7fefffffffffffff; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0xffefffffffffffff; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0x7ff0000000000000; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0xfff0000000000000; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0x7ff8000000000000; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0xfff8000000000000; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0x7ff8000000000001; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0xfff8000000000001; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0x7ff0000000000001; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0xfff0000000000001; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0x3ff0000000000000; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0xbf80000000000000; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(9223372036854775808,64,FLEN)
|
||||
NAN_BOXED(1,64,FLEN)
|
||||
NAN_BOXED(9223372036854775809,64,FLEN)
|
||||
NAN_BOXED(2,64,FLEN)
|
||||
NAN_BOXED(9223372036854775810,64,FLEN)
|
||||
NAN_BOXED(4503599627370495,64,FLEN)
|
||||
NAN_BOXED(9227875636482146303,64,FLEN)
|
||||
NAN_BOXED(4503599627370496,64,FLEN)
|
||||
NAN_BOXED(9227875636482146304,64,FLEN)
|
||||
NAN_BOXED(4503599627370498,64,FLEN)
|
||||
NAN_BOXED(9227875636482146306,64,FLEN)
|
||||
NAN_BOXED(9218868437227405311,64,FLEN)
|
||||
NAN_BOXED(18442240474082181119,64,FLEN)
|
||||
NAN_BOXED(9218868437227405312,64,FLEN)
|
||||
NAN_BOXED(18442240474082181120,64,FLEN)
|
||||
NAN_BOXED(9221120237041090560,64,FLEN)
|
||||
NAN_BOXED(18444492273895866368,64,FLEN)
|
||||
NAN_BOXED(9221120237041090561,64,FLEN)
|
||||
NAN_BOXED(18444492273895866369,64,FLEN)
|
||||
NAN_BOXED(9218868437227405313,64,FLEN)
|
||||
NAN_BOXED(18442240474082181121,64,FLEN)
|
||||
NAN_BOXED(4607182418800017408,64,FLEN)
|
||||
NAN_BOXED(13799029258263199744,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:48 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b22 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b22)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08577924770d3 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0x3fc08577924770d3; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fd and fm1 == 0x93fdc7b89296c and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0x3fd93fdc7b89296c; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 1 and fe1 == 0x3fe and fm1 == 0x766ba34c2da80 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0xbfe766ba34c2da80; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xd2d6b7dc59a3a and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0x3ffd2d6b7dc59a3a; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x400 and fm1 == 0xcf84ba749f9c5 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x400cf84ba749f9c5; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x401 and fm1 == 0x854a908ceac39 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0x401854a908ceac39; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x0ff and fm1 == 0x137a953e8eb43 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0x8ff137a953e8eb43; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xbedc2f3ebcf12 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0x7febedc2f3ebcf12; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,
|
||||
/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,
|
||||
/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,
|
||||
/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,
|
||||
/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,
|
||||
/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,
|
||||
/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,
|
||||
/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,
|
||||
/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,
|
||||
/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,
|
||||
/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,
|
||||
/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,
|
||||
/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,
|
||||
/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,
|
||||
/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,
|
||||
/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,
|
||||
/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(4593818368519663827,64,FLEN)
|
||||
NAN_BOXED(4600778710533613932,64,FLEN)
|
||||
NAN_BOXED(13828134130799532672,64,FLEN)
|
||||
NAN_BOXED(4610891533192108602,64,FLEN)
|
||||
NAN_BOXED(4615336721960794565,64,FLEN)
|
||||
NAN_BOXED(4618534502842412089,64,FLEN)
|
||||
NAN_BOXED(10372132617207737155,64,FLEN)
|
||||
NAN_BOXED(9217722483915607826,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:48 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b23 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b23)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0x43dffffffffffffc; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0x43dffffffffffffd; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0x43dffffffffffffe; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0x43dfffffffffffff; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x43e0000000000000; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0x43e0000000000001; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0x43e0000000000002; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0x43e0000000000003; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0x43e0000000000004; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,
|
||||
/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,
|
||||
/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,
|
||||
/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,
|
||||
/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,
|
||||
/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,
|
||||
/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,
|
||||
/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,
|
||||
/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,
|
||||
/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,
|
||||
/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,
|
||||
/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,
|
||||
/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,
|
||||
/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,
|
||||
/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,
|
||||
/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(4890909195324358652,64,FLEN)
|
||||
NAN_BOXED(4890909195324358653,64,FLEN)
|
||||
NAN_BOXED(4890909195324358654,64,FLEN)
|
||||
NAN_BOXED(4890909195324358655,64,FLEN)
|
||||
NAN_BOXED(4890909195324358656,64,FLEN)
|
||||
NAN_BOXED(4890909195324358657,64,FLEN)
|
||||
NAN_BOXED(4890909195324358658,64,FLEN)
|
||||
NAN_BOXED(4890909195324358659,64,FLEN)
|
||||
NAN_BOXED(4890909195324358660,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:48 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b24 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b24)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0xbff028f5c28f5c29; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0xbff199999999999a; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x3fb999999999999a; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0x3fefae147ae147ae; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0xbfb999999999999a; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0xbff0000000000000; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0x3ff199999999999a; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0x3ff0000000000000; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0xbf847ae147ae147b; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0xbfeccccccccccccd; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0x3feccccccccccccd; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0xbfefae147ae147ae; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0x3ff028f5c28f5c29; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,
|
||||
/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,
|
||||
/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,
|
||||
/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(13829563663736771707,64,FLEN)
|
||||
NAN_BOXED(4576918229304087675,64,FLEN)
|
||||
NAN_BOXED(13830599491651066921,64,FLEN)
|
||||
NAN_BOXED(13831004815617530266,64,FLEN)
|
||||
NAN_BOXED(4591870180066957722,64,FLEN)
|
||||
NAN_BOXED(4607092346807469998,64,FLEN)
|
||||
NAN_BOXED(13815242216921733530,64,FLEN)
|
||||
NAN_BOXED(13830554455654793216,64,FLEN)
|
||||
NAN_BOXED(4606191626881995899,64,FLEN)
|
||||
NAN_BOXED(4607632778762754458,64,FLEN)
|
||||
NAN_BOXED(4607182418800017408,64,FLEN)
|
||||
NAN_BOXED(13800290266158863483,64,FLEN)
|
||||
NAN_BOXED(13829653735729319117,64,FLEN)
|
||||
NAN_BOXED(13831049851613803971,64,FLEN)
|
||||
NAN_BOXED(4607677814759028163,64,FLEN)
|
||||
NAN_BOXED(4592590756007337001,64,FLEN)
|
||||
NAN_BOXED(4606281698874543309,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(13815962792862112809,64,FLEN)
|
||||
NAN_BOXED(13830464383662245806,64,FLEN)
|
||||
NAN_BOXED(4607227454796291113,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:48 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b27 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b27)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0x7ff0000000000001; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0xfff0000000000001; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0x7ff4aaaaaaaaaaaa; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0xfff4aaaaaaaaaaaa; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x7ff8000000000001; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0xfff8000000000001; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0x7ffc000000000001; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0xfffc000000000001; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,
|
||||
/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,
|
||||
/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,
|
||||
/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,
|
||||
/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,
|
||||
/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,
|
||||
/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,
|
||||
/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,
|
||||
/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,
|
||||
/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,
|
||||
/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,
|
||||
/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,
|
||||
/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,
|
||||
/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,
|
||||
/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,
|
||||
/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,
|
||||
/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(9218868437227405313,64,FLEN)
|
||||
NAN_BOXED(18442240474082181121,64,FLEN)
|
||||
NAN_BOXED(9220181987118721706,64,FLEN)
|
||||
NAN_BOXED(18443554023973497514,64,FLEN)
|
||||
NAN_BOXED(9221120237041090561,64,FLEN)
|
||||
NAN_BOXED(18444492273895866369,64,FLEN)
|
||||
NAN_BOXED(9222246136947933185,64,FLEN)
|
||||
NAN_BOXED(18445618173802708993,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:48 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b28 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b28)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0x3fe248ee18215dfa; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0x3ff0000000000000; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0x3ff4000000000000; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x3ff8000000000000; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0x3ffc000000000000; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0x4000000000000000; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0x4002000000000000; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0x4004000000000000; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0x4006000000000000; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0x43cb72eb13dc494a; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0x43e0000000000000; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0x7ff0000000000000; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0x7ff0000000000001; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0x7ff8000000000001; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0x8000000000000000; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0xbfdb008d57e19f88; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0xbf80000000000000; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0xc006000000000000; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0xc004000000000000; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0xc002000000000000; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0xc000000000000000; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0xbffc000000000000; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0xbff8000000000000; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0xbff4000000000000; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0xc3d967a4ae26514c; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0xc3e0000000000000; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0xfff0000000000000; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(4603321956570324474,64,FLEN)
|
||||
NAN_BOXED(4607182418800017408,64,FLEN)
|
||||
NAN_BOXED(4608308318706860032,64,FLEN)
|
||||
NAN_BOXED(4609434218613702656,64,FLEN)
|
||||
NAN_BOXED(4610560118520545280,64,FLEN)
|
||||
NAN_BOXED(4611686018427387904,64,FLEN)
|
||||
NAN_BOXED(4612248968380809216,64,FLEN)
|
||||
NAN_BOXED(4612811918334230528,64,FLEN)
|
||||
NAN_BOXED(4613374868287651840,64,FLEN)
|
||||
NAN_BOXED(4885124574789519690,64,FLEN)
|
||||
NAN_BOXED(4890909195324358656,64,FLEN)
|
||||
NAN_BOXED(9218868437227405312,64,FLEN)
|
||||
NAN_BOXED(9218868437227405313,64,FLEN)
|
||||
NAN_BOXED(9221120237041090561,64,FLEN)
|
||||
NAN_BOXED(9223372036854775808,64,FLEN)
|
||||
NAN_BOXED(13824644088208662408,64,FLEN)
|
||||
NAN_BOXED(13799029258263199744,64,FLEN)
|
||||
NAN_BOXED(13836746905142427648,64,FLEN)
|
||||
NAN_BOXED(13836183955189006336,64,FLEN)
|
||||
NAN_BOXED(13835621005235585024,64,FLEN)
|
||||
NAN_BOXED(13835058055282163712,64,FLEN)
|
||||
NAN_BOXED(13833932155375321088,64,FLEN)
|
||||
NAN_BOXED(13832806255468478464,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(13831680355561635840,64,FLEN)
|
||||
NAN_BOXED(14112424864336204108,64,FLEN)
|
||||
NAN_BOXED(14114281232179134464,64,FLEN)
|
||||
NAN_BOXED(18442240474082181120,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:18:48 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fmvh.x.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fmvh.x.d instruction of the RISC-V RV32FD_Zicsr_Zfa extension for the fmvh.x.d_b29 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*RV32.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fmvh.x.d_b29)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f31; dest:x31; op1val:0x3fc08574923b8698; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f30; dest:x30; op1val:0x3fc08574923b8699; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f29; dest:x29; op1val:0x3fc08574923b869a; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f28; dest:x28; op1val:0x3fc08574923b869b; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f27; dest:x27; op1val:0x3fc08574923b869c; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f26; dest:x26; op1val:0x3fc08574923b869d; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f25; dest:x25; op1val:0x3fc08574923b869e; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f24; dest:x24; op1val:0x3fc08574923b869f; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f23; dest:x23; op1val:0xbfc08574923b8698; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f22; dest:x22; op1val:0xbfc08574923b8699; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f21; dest:x21; op1val:0xbfc08574923b869a; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f20; dest:x20; op1val:0xbfc08574923b869b; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f19; dest:x19; op1val:0xbfc08574923b869c; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f18; dest:x18; op1val:0xbfc08574923b869d; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f17; dest:x17; op1val:0xbfc08574923b869e; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0
|
||||
/* opcode: fmvh.x.d ; op1:f16; dest:x16; op1val:0xbfc08574923b869f; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,
|
||||
/* opcode: fmvh.x.d ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,
|
||||
/* opcode: fmvh.x.d ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,
|
||||
/* opcode: fmvh.x.d ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,
|
||||
/* opcode: fmvh.x.d ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,
|
||||
/* opcode: fmvh.x.d ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,
|
||||
/* opcode: fmvh.x.d ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,
|
||||
/* opcode: fmvh.x.d ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,
|
||||
/* opcode: fmvh.x.d ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fmvh.x.d ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fmvh.x.d ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fmvh.x.d ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fmvh.x.d ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fmvh.x.d ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fmvh.x.d ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fmvh.x.d ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fmvh.x.d ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fmvh.x.d, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(4593818355633981080,64,FLEN)
|
||||
NAN_BOXED(4593818355633981081,64,FLEN)
|
||||
NAN_BOXED(4593818355633981082,64,FLEN)
|
||||
NAN_BOXED(4593818355633981083,64,FLEN)
|
||||
NAN_BOXED(4593818355633981084,64,FLEN)
|
||||
NAN_BOXED(4593818355633981085,64,FLEN)
|
||||
NAN_BOXED(4593818355633981086,64,FLEN)
|
||||
NAN_BOXED(4593818355633981087,64,FLEN)
|
||||
NAN_BOXED(13817190392488756888,64,FLEN)
|
||||
NAN_BOXED(13817190392488756889,64,FLEN)
|
||||
NAN_BOXED(13817190392488756890,64,FLEN)
|
||||
NAN_BOXED(13817190392488756891,64,FLEN)
|
||||
NAN_BOXED(13817190392488756892,64,FLEN)
|
||||
NAN_BOXED(13817190392488756893,64,FLEN)
|
||||
NAN_BOXED(13817190392488756894,64,FLEN)
|
||||
NAN_BOXED(13817190392488756895,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,353 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:11:52 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fround.d.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fround.d instruction of the RISC-V RV32FD_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fround.d_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IFD_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*Zfa.*);def TEST_CASE_1=True;",fround.d_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:
|
||||
// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:
|
||||
// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f29; dest:f30; op1val:0x8000000000000000; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f30, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:
|
||||
// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f29, f30, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:
|
||||
// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f27; dest:f28; op1val:0x8000000000000001; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f28, f27, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:
|
||||
// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f27, f28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:
|
||||
// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f25; dest:f26; op1val:0x8000000000000002; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:
|
||||
// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f26; dest:f25; op1val:0xfffffffffffff; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f25, f26, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:
|
||||
// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f23; dest:f24; op1val:0x800fffffffffffff; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f24, f23, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:
|
||||
// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f24; dest:f23; op1val:0x10000000000000; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f23, f24, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:
|
||||
// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f21; dest:f22; op1val:0x8010000000000000; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f22, f21, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:
|
||||
// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f22; dest:f21; op1val:0x10000000000002; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:
|
||||
// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f19; dest:f20; op1val:0x8010000000000002; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f20, f19, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:
|
||||
// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f20; dest:f19; op1val:0x7fefffffffffffff; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f19, f20, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:
|
||||
// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f17; dest:f18; op1val:0xffefffffffffffff; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f18, f17, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:
|
||||
// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f18; dest:f17; op1val:0x7ff0000000000000; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f17, f18, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:
|
||||
// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f15; dest:f16; op1val:0xfff0000000000000; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:
|
||||
// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f16; dest:f15; op1val:0x7ff8000000000000; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f15, f16, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:
|
||||
// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f13; dest:f14; op1val:0xfff8000000000000; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f14, f13, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:
|
||||
// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f14; dest:f13; op1val:0x7ff8000000000001; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f13, f14, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:
|
||||
// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f11; dest:f12; op1val:0xfff8000000000001; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f12, f11, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:
|
||||
// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f12; dest:f11; op1val:0x7ff0000000000001; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:
|
||||
// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f9; dest:f10; op1val:0xfff0000000000001; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f10, f9, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:
|
||||
// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f10; dest:f9; op1val:0x3ff0000000000000; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f9, f10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:
|
||||
// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.d ; op1:f7; dest:f8; op1val:0xbf80000000000000; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f8, f7, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:
|
||||
// rs1==f8, rd==f7,
|
||||
/* opcode: fround.d ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f7, f8, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:
|
||||
// rs1==f5, rd==f6,
|
||||
/* opcode: fround.d ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:
|
||||
// rs1==f6, rd==f5,
|
||||
/* opcode: fround.d ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f5, f6, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:
|
||||
// rs1==f3, rd==f4,
|
||||
/* opcode: fround.d ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f4, f3, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:
|
||||
// rs1==f4, rd==f3,
|
||||
/* opcode: fround.d ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f3, f4, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:
|
||||
// rs1==f1, rd==f2,
|
||||
/* opcode: fround.d ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f2, f1, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:
|
||||
// rs1==f2, rd==f1,
|
||||
/* opcode: fround.d ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:
|
||||
// rs1==f0,
|
||||
/* opcode: fround.d ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f31, f0, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:
|
||||
// rd==f0,
|
||||
/* opcode: fround.d ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.d, f0, f31, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(9223372036854775808,64,FLEN)
|
||||
NAN_BOXED(1,64,FLEN)
|
||||
NAN_BOXED(9223372036854775809,64,FLEN)
|
||||
NAN_BOXED(2,64,FLEN)
|
||||
NAN_BOXED(9223372036854775810,64,FLEN)
|
||||
NAN_BOXED(4503599627370495,64,FLEN)
|
||||
NAN_BOXED(9227875636482146303,64,FLEN)
|
||||
NAN_BOXED(4503599627370496,64,FLEN)
|
||||
NAN_BOXED(9227875636482146304,64,FLEN)
|
||||
NAN_BOXED(4503599627370498,64,FLEN)
|
||||
NAN_BOXED(9227875636482146306,64,FLEN)
|
||||
NAN_BOXED(9218868437227405311,64,FLEN)
|
||||
NAN_BOXED(18442240474082181119,64,FLEN)
|
||||
NAN_BOXED(9218868437227405312,64,FLEN)
|
||||
NAN_BOXED(18442240474082181120,64,FLEN)
|
||||
NAN_BOXED(9221120237041090560,64,FLEN)
|
||||
NAN_BOXED(18444492273895866368,64,FLEN)
|
||||
NAN_BOXED(9221120237041090561,64,FLEN)
|
||||
NAN_BOXED(18444492273895866369,64,FLEN)
|
||||
NAN_BOXED(9218868437227405313,64,FLEN)
|
||||
NAN_BOXED(18442240474082181121,64,FLEN)
|
||||
NAN_BOXED(4607182418800017408,64,FLEN)
|
||||
NAN_BOXED(13799029258263199744,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,353 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:11:45 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fround.s.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fround.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fround_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fround_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:
|
||||
// rs1 == rd, rs1==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f31; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:
|
||||
// rs1 != rd, rs1==f29, rd==f30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f29; dest:f30; op1val:0x80000000; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f30, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:
|
||||
// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f30; dest:f29; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f29, f30, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:
|
||||
// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f28, f27, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:
|
||||
// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f27, f28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:
|
||||
// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:
|
||||
// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f25, f26, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:
|
||||
// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f24, f23, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:
|
||||
// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f23, f24, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:
|
||||
// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f22, f21, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:
|
||||
// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:
|
||||
// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f20, f19, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:
|
||||
// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f19, f20, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:
|
||||
// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f18, f17, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:
|
||||
// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f17, f18, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:
|
||||
// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:
|
||||
// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f15, f16, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:
|
||||
// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f14, f13, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:
|
||||
// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f13, f14, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:
|
||||
// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f12, f11, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:
|
||||
// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:
|
||||
// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f10, f9, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:
|
||||
// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f9, f10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:
|
||||
// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
|
||||
/* opcode: fround.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f8, f7, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:
|
||||
// rs1==f8, rd==f7,
|
||||
/* opcode: fround.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f7, f8, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:
|
||||
// rs1==f5, rd==f6,
|
||||
/* opcode: fround.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:
|
||||
// rs1==f6, rd==f5,
|
||||
/* opcode: fround.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f5, f6, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:
|
||||
// rs1==f3, rd==f4,
|
||||
/* opcode: fround.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f4, f3, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:
|
||||
// rs1==f4, rd==f3,
|
||||
/* opcode: fround.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f3, f4, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:
|
||||
// rs1==f1, rd==f2,
|
||||
/* opcode: fround.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f2, f1, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:
|
||||
// rs1==f2, rd==f1,
|
||||
/* opcode: fround.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:
|
||||
// rs1==f0,
|
||||
/* opcode: fround.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f31, f0, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:
|
||||
// rd==f0,
|
||||
/* opcode: fround.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f0, f31, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(1,32,FLEN)
|
||||
NAN_BOXED(2147483649,32,FLEN)
|
||||
NAN_BOXED(2,32,FLEN)
|
||||
NAN_BOXED(2155872254,32,FLEN)
|
||||
NAN_BOXED(8388607,32,FLEN)
|
||||
NAN_BOXED(2155872255,32,FLEN)
|
||||
NAN_BOXED(8388608,32,FLEN)
|
||||
NAN_BOXED(2155872256,32,FLEN)
|
||||
NAN_BOXED(8388609,32,FLEN)
|
||||
NAN_BOXED(2156221781,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4286578687,32,FLEN)
|
||||
NAN_BOXED(2139095040,32,FLEN)
|
||||
NAN_BOXED(4286578688,32,FLEN)
|
||||
NAN_BOXED(2143289344,32,FLEN)
|
||||
NAN_BOXED(4290772992,32,FLEN)
|
||||
NAN_BOXED(2143289345,32,FLEN)
|
||||
NAN_BOXED(4291122517,32,FLEN)
|
||||
NAN_BOXED(2139095041,32,FLEN)
|
||||
NAN_BOXED(4289374890,32,FLEN)
|
||||
NAN_BOXED(1065353216,32,FLEN)
|
||||
NAN_BOXED(3212836864,32,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
NAN_BOXED(0,64,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,204 @@
|
|||
// Copyright (c) 2023. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fli.s instruction
|
||||
// for the following ISA configurations:
|
||||
// * RV32IF_Zfa
|
||||
// * RV64IF_Zfa
|
||||
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
|
||||
RVTEST_ISA("RV32IF_Zfa,RV64IF_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
|
||||
RVMODEL_BOOT
|
||||
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fli.s)
|
||||
|
||||
// Registers with a special purpose
|
||||
#define SIG_BASEREG x1
|
||||
#define FCSR_REG x2
|
||||
#define DATA_BASEREG x3
|
||||
|
||||
// Initialize the FPU
|
||||
RVTEST_FP_ENABLE()
|
||||
// Prepare the DATA_BASEREG register
|
||||
RVTEST_VALBASEUPD(DATA_BASEREG, dataset_tc1)
|
||||
// Prepare the SIG_BASEREG register
|
||||
RVTEST_SIGBASE(SIG_BASEREG, signature_tc1)
|
||||
|
||||
// FLI.S loads a pre-defined constant into a FP register.
|
||||
// FLI.S has the following inputs and outputs:
|
||||
// - input rs1: 5-bit immediate holding the constants ID
|
||||
// - output fld: FP register
|
||||
|
||||
// TEST_CASE_FLI_S executes a FLI.S insn and stores the result in the sig
|
||||
// 1) the FCSR_OLD value will be store into FCSR using FCSR_REG
|
||||
// 2) fli.s is executed using FLD as dest register and FLI_CONST as constant
|
||||
// 3) The constents of FLD and FCSR are stored in the signature
|
||||
#define TEST_CASE_FLI_S(fld, fli_const, fcsr_old, fcsr_reg) \
|
||||
li fcsr_reg, fcsr_old ;\
|
||||
csrw fcsr, fcsr_reg ;\
|
||||
fli.s fld, fli_const ;\
|
||||
csrr fcsr_reg, fcsr ;\
|
||||
RVTEST_SIGUPD_F(SIG_BASEREG, fld, fcsr_reg) ;\
|
||||
|
||||
// Below we have one instruction test per constant
|
||||
|
||||
inst_0:
|
||||
TEST_CASE_FLI_S(f16, -0x1p+0, 0, FCSR_REG)
|
||||
|
||||
inst_1:
|
||||
TEST_CASE_FLI_S(f17, min, 0, FCSR_REG)
|
||||
|
||||
inst_2:
|
||||
TEST_CASE_FLI_S(f18, 0x1p-16, 0, FCSR_REG)
|
||||
|
||||
inst_3:
|
||||
TEST_CASE_FLI_S(f19, 0x1p-15, 0, FCSR_REG)
|
||||
|
||||
inst_4:
|
||||
TEST_CASE_FLI_S(f20, 0x1p-8, 0, FCSR_REG)
|
||||
|
||||
inst_5:
|
||||
TEST_CASE_FLI_S(f21, 0x1p-7, 0, FCSR_REG)
|
||||
|
||||
inst_6:
|
||||
TEST_CASE_FLI_S(f22, 0x1p-4, 0, FCSR_REG)
|
||||
|
||||
inst_7:
|
||||
TEST_CASE_FLI_S(f23, 0x1p-3, 0, FCSR_REG)
|
||||
|
||||
inst_8:
|
||||
TEST_CASE_FLI_S(f24, 0x1p-2, 0, FCSR_REG)
|
||||
|
||||
inst_9:
|
||||
TEST_CASE_FLI_S(f25, 0x1.4p-2, 0, FCSR_REG)
|
||||
|
||||
inst_10:
|
||||
TEST_CASE_FLI_S(f26, 0x1.8p-2, 0, FCSR_REG)
|
||||
|
||||
inst_11:
|
||||
TEST_CASE_FLI_S(f27, 0x1.cp-2, 0, FCSR_REG)
|
||||
|
||||
inst_12:
|
||||
TEST_CASE_FLI_S(f28, 0x1p-1, 0, FCSR_REG)
|
||||
|
||||
inst_13:
|
||||
TEST_CASE_FLI_S(f29, 0x1.4p-1, 0, FCSR_REG)
|
||||
|
||||
inst_14:
|
||||
TEST_CASE_FLI_S(f30, 0x1.8p-1, 0, FCSR_REG)
|
||||
|
||||
inst_15:
|
||||
TEST_CASE_FLI_S(f31, 0x1.cp-1, 0, FCSR_REG)
|
||||
|
||||
inst_16:
|
||||
TEST_CASE_FLI_S(f0, 0x1p0, 0, FCSR_REG)
|
||||
|
||||
inst_17:
|
||||
TEST_CASE_FLI_S(f1, 0x1.4p+0, 0, FCSR_REG)
|
||||
|
||||
inst_18:
|
||||
TEST_CASE_FLI_S(f2, 0x1.8p+0, 0, FCSR_REG)
|
||||
|
||||
inst_19:
|
||||
TEST_CASE_FLI_S(f3, 0x1.cp+0, 0, FCSR_REG)
|
||||
|
||||
inst_20:
|
||||
TEST_CASE_FLI_S(f4, 0x1p+1, 0, FCSR_REG)
|
||||
|
||||
inst_21:
|
||||
TEST_CASE_FLI_S(f5, 0x1.4p+1, 0, FCSR_REG)
|
||||
|
||||
inst_22:
|
||||
TEST_CASE_FLI_S(f6, 0x1.8p+1, 0, FCSR_REG)
|
||||
|
||||
inst_23:
|
||||
TEST_CASE_FLI_S(f7, 0x1p+2, 0, FCSR_REG)
|
||||
|
||||
inst_24:
|
||||
TEST_CASE_FLI_S(f8, 0x1p+3, 0, FCSR_REG)
|
||||
|
||||
inst_25:
|
||||
TEST_CASE_FLI_S(f9, 0x1p+4, 0, FCSR_REG)
|
||||
|
||||
inst_26:
|
||||
TEST_CASE_FLI_S(f10, 0x1p+7, 0, FCSR_REG)
|
||||
|
||||
inst_27:
|
||||
TEST_CASE_FLI_S(f11, 0x1p+8, 0, FCSR_REG)
|
||||
|
||||
inst_28:
|
||||
TEST_CASE_FLI_S(f12, 0x1p+15, 0, FCSR_REG)
|
||||
|
||||
inst_29:
|
||||
TEST_CASE_FLI_S(f13, 0x1p+16, 0, FCSR_REG)
|
||||
|
||||
inst_30:
|
||||
TEST_CASE_FLI_S(f14, inf, 0, FCSR_REG)
|
||||
|
||||
inst_31:
|
||||
TEST_CASE_FLI_S(f15, nan, 0, FCSR_REG)
|
||||
|
||||
#endif // TEST_CASE_1
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.word 0xbabecafe // trapreg_sv
|
||||
.word 0xabecafeb // tramptbl_sv
|
||||
.word 0xbecafeba // mtvec_save
|
||||
.word 0xecafebab // mscratch_save
|
||||
dataset_tc1:
|
||||
/* empty */
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
signature_tc1:
|
||||
// We have 32 test cases and store for each test case:
|
||||
// - 32-bit FP register (fld)
|
||||
// - 32-bit FCSR content after the instruction
|
||||
.fill 64*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
mtrap_sigptr:
|
||||
.fill 64*(XLEN/32),4,0xdeadbeef
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
|
||||
#endif // rvtest_mtrap_routine
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif // rvtest_gpr_save
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,353 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.10.3
|
||||
// timestamp : Mon May 22 12:11:44 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/cm/src/riscv-ctg/zfa/sample_cgfs/zfa/fround.s.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fround.s instruction of the RISC-V RV32F_Zicsr_Zfa,RV32FD_Zicsr_Zfa,RV64F_Zicsr_Zfa,RV64FD_Zicsr_Zfa extension for the fround_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfa,RV32IFD_Zicsr_Zfa,RV64IF_Zicsr_Zfa,RV64IFD_Zicsr_Zfa")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfa.*);def TEST_CASE_1=True;",fround_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:
|
||||
// rs1 != rd, rs1==f30, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f31, f30, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:
|
||||
// rs1 == rd, rs1==f29, rd==f29,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f29; dest:f29; op1val:0x80000000; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f29, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:
|
||||
// rs1==f31, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f31; dest:f30; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f30, f31, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:
|
||||
// rs1==f27, rd==f28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f27; dest:f28; op1val:0x80000001; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f28, f27, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:
|
||||
// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f28; dest:f27; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f27, f28, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:
|
||||
// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f25; dest:f26; op1val:0x807ffffe; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f26, f25, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:
|
||||
// rs1==f26, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f26; dest:f25; op1val:0x7fffff; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f25, f26, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:
|
||||
// rs1==f23, rd==f24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f23; dest:f24; op1val:0x807fffff; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f24, f23, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:
|
||||
// rs1==f24, rd==f23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f24; dest:f23; op1val:0x800000; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f23, f24, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:
|
||||
// rs1==f21, rd==f22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f21; dest:f22; op1val:0x80800000; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f22, f21, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:
|
||||
// rs1==f22, rd==f21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f22; dest:f21; op1val:0x800001; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f21, f22, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:
|
||||
// rs1==f19, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f19; dest:f20; op1val:0x80855555; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f20, f19, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:
|
||||
// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f20; dest:f19; op1val:0x7f7fffff; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f19, f20, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:
|
||||
// rs1==f17, rd==f18,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f17; dest:f18; op1val:0xff7fffff; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f18, f17, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:
|
||||
// rs1==f18, rd==f17,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f18; dest:f17; op1val:0x7f800000; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f17, f18, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:
|
||||
// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f15; dest:f16; op1val:0xff800000; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f16, f15, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:
|
||||
// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f16; dest:f15; op1val:0x7fc00000; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f15, f16, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:
|
||||
// rs1==f13, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f13; dest:f14; op1val:0xffc00000; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f14, f13, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:
|
||||
// rs1==f14, rd==f13,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f14; dest:f13; op1val:0x7fc00001; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f13, f14, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:
|
||||
// rs1==f11, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f11; dest:f12; op1val:0xffc55555; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f12, f11, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:
|
||||
// rs1==f12, rd==f11,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f12; dest:f11; op1val:0x7f800001; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f11, f12, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:
|
||||
// rs1==f9, rd==f10,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f9; dest:f10; op1val:0xffaaaaaa; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f10, f9, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:
|
||||
// rs1==f10, rd==f9,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f10; dest:f9; op1val:0x3f800000; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f9, f10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:
|
||||
// rs1==f7, rd==f8,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7
|
||||
/* opcode: fround.s ; op1:f7; dest:f8; op1val:0xbf800000; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f8, f7, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:
|
||||
// rs1==f8, rd==f7,
|
||||
/* opcode: fround.s ; op1:f8; dest:f7; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f7, f8, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:
|
||||
// rs1==f5, rd==f6,
|
||||
/* opcode: fround.s ; op1:f5; dest:f6; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f6, f5, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:
|
||||
// rs1==f6, rd==f5,
|
||||
/* opcode: fround.s ; op1:f6; dest:f5; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f5, f6, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:
|
||||
// rs1==f3, rd==f4,
|
||||
/* opcode: fround.s ; op1:f3; dest:f4; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f4, f3, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:
|
||||
// rs1==f4, rd==f3,
|
||||
/* opcode: fround.s ; op1:f4; dest:f3; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f3, f4, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:
|
||||
// rs1==f1, rd==f2,
|
||||
/* opcode: fround.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f2, f1, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:
|
||||
// rs1==f2, rd==f1,
|
||||
/* opcode: fround.s ; op1:f2; dest:f1; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f1, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:
|
||||
// rs1==f0,
|
||||
/* opcode: fround.s ; op1:f0; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f31, f0, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:
|
||||
// rd==f0,
|
||||
/* opcode: fround.s ; op1:f31; dest:f0; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0 */
|
||||
TEST_FPSR_OP(fround.s, f0, f31, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(2147483648,32,FLEN)
|
||||
NAN_BOXED(1,32,FLEN)
|
||||
NAN_BOXED(2147483649,32,FLEN)
|
||||
NAN_BOXED(2,32,FLEN)
|
||||
NAN_BOXED(2155872254,32,FLEN)
|
||||
NAN_BOXED(8388607,32,FLEN)
|
||||
NAN_BOXED(2155872255,32,FLEN)
|
||||
NAN_BOXED(8388608,32,FLEN)
|
||||
NAN_BOXED(2155872256,32,FLEN)
|
||||
NAN_BOXED(8388609,32,FLEN)
|
||||
NAN_BOXED(2156221781,32,FLEN)
|
||||
NAN_BOXED(2139095039,32,FLEN)
|
||||
NAN_BOXED(4286578687,32,FLEN)
|
||||
NAN_BOXED(2139095040,32,FLEN)
|
||||
NAN_BOXED(4286578688,32,FLEN)
|
||||
NAN_BOXED(2143289344,32,FLEN)
|
||||
NAN_BOXED(4290772992,32,FLEN)
|
||||
NAN_BOXED(2143289345,32,FLEN)
|
||||
NAN_BOXED(4291122517,32,FLEN)
|
||||
NAN_BOXED(2139095041,32,FLEN)
|
||||
NAN_BOXED(4289374890,32,FLEN)
|
||||
NAN_BOXED(1065353216,32,FLEN)
|
||||
NAN_BOXED(3212836864,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,413 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Sat May 6 11:38:58 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fadd_b10 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fadd_b10)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f31; op2:f31; dest:f31; op1val:0x52ee; op2val:0x52ee;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f29, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0a and fm2 == 0x262 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f29; op2:f28; dest:f30; op1val:0x52ee; op2val:0x2a62;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f30, f29, f28, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3fb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f29; op1val:0x52ee; op2val:0x37fb;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f29, f30, f29, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f28; op2:f30; dest:f28; op1val:0x52ee; op2val:0x44fd;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f28, f28, f30, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x14 and fm2 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f26; op2:f26; dest:f27; op1val:0x52ee; op2val:0x52ee;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f27, f26, f26, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3cb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f27; op2:f25; dest:f26; op1val:0x52ee; op2val:0x5fcb;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f26, f27, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f24, rs2==f27, rd==f25,
|
||||
/* opcode: fadd.h ; op1:f24; op2:f27; dest:f25; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f25, f24, f27, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f25, rs2==f23, rd==f24,
|
||||
/* opcode: fadd.h ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f24, f25, f23, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f22, rs2==f24, rd==f23,
|
||||
/* opcode: fadd.h ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f23, f22, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f23, rs2==f21, rd==f22,
|
||||
/* opcode: fadd.h ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f22, f23, f21, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f20, rs2==f22, rd==f21,
|
||||
/* opcode: fadd.h ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f21, rs2==f19, rd==f20,
|
||||
/* opcode: fadd.h ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f20, f21, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f18, rs2==f20, rd==f19,
|
||||
/* opcode: fadd.h ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f19, f18, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f19, rs2==f17, rd==f18,
|
||||
/* opcode: fadd.h ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f18, f19, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f16, rs2==f18, rd==f17,
|
||||
/* opcode: fadd.h ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f17, f16, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f17, rs2==f15, rd==f16,
|
||||
/* opcode: fadd.h ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f16, f17, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f14, rs2==f16, rd==f15,
|
||||
/* opcode: fadd.h ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f15, f14, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f15, rs2==f13, rd==f14,
|
||||
/* opcode: fadd.h ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f14, f15, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f12, rs2==f14, rd==f13,
|
||||
/* opcode: fadd.h ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f13, f12, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f13, rs2==f11, rd==f12,
|
||||
/* opcode: fadd.h ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f12, f13, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f10, rs2==f12, rd==f11,
|
||||
/* opcode: fadd.h ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f11, f10, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f11, rs2==f9, rd==f10,
|
||||
/* opcode: fadd.h ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f10, f11, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f8, rs2==f10, rd==f9,
|
||||
/* opcode: fadd.h ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f9, f8, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f9, rs2==f7, rd==f8,
|
||||
/* opcode: fadd.h ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f8, f9, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:// rs1==f6, rs2==f8, rd==f7,
|
||||
/* opcode: fadd.h ; op1:f6; op2:f8; dest:f7; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f7, f6, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:// rs1==f7, rs2==f5, rd==f6,
|
||||
/* opcode: fadd.h ; op1:f7; op2:f5; dest:f6; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f6, f7, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:// rs1==f4, rs2==f6, rd==f5,
|
||||
/* opcode: fadd.h ; op1:f4; op2:f6; dest:f5; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f5, f4, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:// rs1==f5, rs2==f3, rd==f4,
|
||||
/* opcode: fadd.h ; op1:f5; op2:f3; dest:f4; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f4, f5, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:// rs1==f2, rs2==f4, rd==f3,
|
||||
/* opcode: fadd.h ; op1:f2; op2:f4; dest:f3; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f3, f2, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:// rs1==f3, rs2==f1, rd==f2,
|
||||
/* opcode: fadd.h ; op1:f3; op2:f1; dest:f2; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f2, f3, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:// rs1==f0, rs2==f2, rd==f1,
|
||||
/* opcode: fadd.h ; op1:f0; op2:f2; dest:f1; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f1, f0, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:// rs1==f1,
|
||||
/* opcode: fadd.h ; op1:f1; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f1, f30, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:// rs2==f0,
|
||||
/* opcode: fadd.h ; op1:f30; op2:f0; dest:f31; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f0, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:// rd==f0,
|
||||
/* opcode: fadd.h ; op1:f31; op2:f30; dest:f0; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f0, f31, f30, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_34:// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x52ee; op2val:0x53;
|
||||
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_35:// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x14 and fm2 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x52ee; op2val:0x523c;
|
||||
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(10850,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(14331,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(17661,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(24523,16,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(83,16,FLEN)
|
||||
NAN_BOXED(21230,16,FLEN)
|
||||
NAN_BOXED(21052,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 72*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,548 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Sat May 6 11:38:58 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fadd_b12 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fadd_b12)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 1 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f31; op2:f31; dest:f31; op1val:0xfac0; op2val:0xfac0;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f29, rs2==f28, rd==f30,fs1 == 1 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f29; op2:f28; dest:f30; op1val:0xf6b9; op2val:0x796e;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f30, f29, f28, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 1 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f29; op1val:0xf816; op2val:0x7b53;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f29, f30, f29, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 1 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f28; op2:f30; dest:f28; op1val:0xfa44; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f28, f28, f30, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 1 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f26; op2:f26; dest:f27; op1val:0xf79f; op2val:0xf79f;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f27, f26, f26, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f27, rs2==f25, rd==f26,fs1 == 1 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f27; op2:f25; dest:f26; op1val:0xfb42; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f26, f27, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f24, rs2==f27, rd==f25,fs1 == 1 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f24; op2:f27; dest:f25; op1val:0xf481; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f25, f24, f27, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f25, rs2==f23, rd==f24,fs1 == 1 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f2 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f25; op2:f23; dest:f24; op1val:0xf8f1; op2val:0x7af2;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f24, f25, f23, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f22, rs2==f24, rd==f23,fs1 == 1 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f22; op2:f24; dest:f23; op1val:0xfb46; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f23, f22, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f23, rs2==f21, rd==f22,fs1 == 1 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f23; op2:f21; dest:f22; op1val:0xfa7a; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f22, f23, f21, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f20, rs2==f22, rd==f21,fs1 == 1 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f20; op2:f22; dest:f21; op1val:0xf4f5; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f21, rs2==f19, rd==f20,fs1 == 1 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f21; op2:f19; dest:f20; op1val:0xfb2f; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f20, f21, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f18, rs2==f20, rd==f19,fs1 == 1 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x094 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f18; op2:f20; dest:f19; op1val:0xf78c; op2val:0x7894;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f19, f18, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f19, rs2==f17, rd==f18,fs1 == 1 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f19; op2:f17; dest:f18; op1val:0xf6f1; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f18, f19, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f16, rs2==f18, rd==f17,fs1 == 1 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f16; op2:f18; dest:f17; op1val:0xfb4c; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f17, f16, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f17, rs2==f15, rd==f16,fs1 == 1 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f17; op2:f15; dest:f16; op1val:0xf7a0; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f16, f17, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f14, rs2==f16, rd==f15,fs1 == 1 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f14; op2:f16; dest:f15; op1val:0xf42a; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f15, f14, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f15, rs2==f13, rd==f14,fs1 == 1 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f15; op2:f13; dest:f14; op1val:0xf863; op2val:0x787f;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f14, f15, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f12, rs2==f14, rd==f13,fs1 == 1 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f12; op2:f14; dest:f13; op1val:0xf9c1; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f13, f12, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f13, rs2==f11, rd==f12,fs1 == 1 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f13; op2:f11; dest:f12; op1val:0xfa98; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f12, f13, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f10, rs2==f12, rd==f11,fs1 == 1 and fe1 == 0x15 and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f10; op2:f12; dest:f11; op1val:0xd4ad; op2val:0x77e9;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f11, f10, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f11, rs2==f9, rd==f10,fs1 == 1 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f11; op2:f9; dest:f10; op1val:0xfaef; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f10, f11, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f8, rs2==f10, rd==f9,fs1 == 1 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f8; op2:f10; dest:f9; op1val:0xf533; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f9, f8, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f9, rs2==f7, rd==f8,fs1 == 1 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x210 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f9; op2:f7; dest:f8; op1val:0xf21c; op2val:0x7a10;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f8, f9, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f6; op2:f8; dest:f7; op1val:0xf3a1; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f7, f6, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:// rs1==f7, rs2==f5, rd==f6,fs1 == 1 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f7; op2:f5; dest:f6; op1val:0xfa6c; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f6, f7, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f4; op2:f6; dest:f5; op1val:0xed25; op2val:0x7667;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f5, f4, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:// rs1==f5, rs2==f3, rd==f4,fs1 == 1 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f5; op2:f3; dest:f4; op1val:0xf80f; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f4, f5, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x1b and fm1 == 0x2f9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x147 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f2; op2:f4; dest:f3; op1val:0xeef9; op2val:0x7947;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f3, f2, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f3; op2:f1; dest:f2; op1val:0xf9a6; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f2, f3, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f0; op2:f2; dest:f1; op1val:0xfa83; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f1, f0, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:// rs1==f1,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f1; op2:f30; dest:f31; op1val:0xfbb4; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f1, f30, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f0; dest:f31; op1val:0xf8b2; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f0, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:// rd==f0,fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f31; op2:f30; dest:f0; op1val:0xf8c4; op2val:0x7bd8;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f0, f31, f30, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_34:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf89a; op2val:0x7aec;
|
||||
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_35:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x203 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf20e; op2val:0x7603;
|
||||
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_36:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf8e6; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_37:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x087 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf79e; op2val:0x7887;
|
||||
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_38:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfa0e; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_39:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfb62; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_40:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfb2e; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_41:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x373 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf852; op2val:0x7b73;
|
||||
valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_42:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf9a3; op2val:0x7bd7;
|
||||
valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_43:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfa7d; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_44:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfb28; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_45:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfb98; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_46:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf734; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_47:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfbf7; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_48:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfa57; op2val:0x7b00;
|
||||
valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_49:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfac0; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_50:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf79f; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(64192,16,FLEN)
|
||||
NAN_BOXED(64192,16,FLEN)
|
||||
NAN_BOXED(63161,16,FLEN)
|
||||
NAN_BOXED(31086,16,FLEN)
|
||||
NAN_BOXED(63510,16,FLEN)
|
||||
NAN_BOXED(31571,16,FLEN)
|
||||
NAN_BOXED(64068,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63391,16,FLEN)
|
||||
NAN_BOXED(63391,16,FLEN)
|
||||
NAN_BOXED(64322,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(62593,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63729,16,FLEN)
|
||||
NAN_BOXED(31474,16,FLEN)
|
||||
NAN_BOXED(64326,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64122,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(62709,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64303,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63372,16,FLEN)
|
||||
NAN_BOXED(30868,16,FLEN)
|
||||
NAN_BOXED(63217,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64332,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63392,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(62506,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63587,16,FLEN)
|
||||
NAN_BOXED(30847,16,FLEN)
|
||||
NAN_BOXED(63937,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64152,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(54445,16,FLEN)
|
||||
NAN_BOXED(30697,16,FLEN)
|
||||
NAN_BOXED(64239,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(62771,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(61980,16,FLEN)
|
||||
NAN_BOXED(31248,16,FLEN)
|
||||
NAN_BOXED(62369,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64108,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(60709,16,FLEN)
|
||||
NAN_BOXED(30311,16,FLEN)
|
||||
NAN_BOXED(63503,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(61177,16,FLEN)
|
||||
NAN_BOXED(31047,16,FLEN)
|
||||
NAN_BOXED(63910,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64131,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64436,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63666,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63684,16,FLEN)
|
||||
NAN_BOXED(31704,16,FLEN)
|
||||
NAN_BOXED(63642,16,FLEN)
|
||||
NAN_BOXED(31468,16,FLEN)
|
||||
NAN_BOXED(61966,16,FLEN)
|
||||
NAN_BOXED(30211,16,FLEN)
|
||||
NAN_BOXED(63718,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63390,16,FLEN)
|
||||
NAN_BOXED(30855,16,FLEN)
|
||||
NAN_BOXED(64014,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64354,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64302,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63570,16,FLEN)
|
||||
NAN_BOXED(31603,16,FLEN)
|
||||
NAN_BOXED(63907,16,FLEN)
|
||||
NAN_BOXED(31703,16,FLEN)
|
||||
NAN_BOXED(64125,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64296,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64408,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63284,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64503,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64087,16,FLEN)
|
||||
NAN_BOXED(31488,16,FLEN)
|
||||
NAN_BOXED(64192,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(63391,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 102*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,602 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Sat May 6 11:38:58 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fadd_b7 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fadd_b7)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f31; op2:f31; dest:f31; op1val:0x7ac0; op2val:0x7ac0;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f31, f31, dyn, 96, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f29, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f29; op2:f28; dest:f30; op1val:0x76b9; op2val:0xf6b9;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f30, f29, f28, dyn, 96, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f29; op1val:0x7816; op2val:0xf816;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f29, f30, f29, dyn, 96, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f28; op2:f30; dest:f28; op1val:0x7a44; op2val:0xfa44;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f28, f28, f30, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f26; op2:f26; dest:f27; op1val:0x779f; op2val:0x779f;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f27, f26, f26, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f27; op2:f25; dest:f26; op1val:0x7b42; op2val:0xfb42;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f26, f27, f25, dyn, 96, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f24; op2:f27; dest:f25; op1val:0x7481; op2val:0xf481;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f25, f24, f27, dyn, 96, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f25; op2:f23; dest:f24; op1val:0x78f1; op2val:0xf8f1;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f24, f25, f23, dyn, 96, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f22; op2:f24; dest:f23; op1val:0x7b46; op2val:0xfb46;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f23, f22, f24, dyn, 96, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f23; op2:f21; dest:f22; op1val:0x7a7a; op2val:0xfa7a;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f22, f23, f21, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f20; op2:f22; dest:f21; op1val:0x74f5; op2val:0xf4f5;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f21, f20, f22, dyn, 96, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f21; op2:f19; dest:f20; op1val:0x7b2f; op2val:0xfb2f;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f20, f21, f19, dyn, 96, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f18; op2:f20; dest:f19; op1val:0x778c; op2val:0xf78c;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f19, f18, f20, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f19; op2:f17; dest:f18; op1val:0x76f1; op2val:0xf6f1;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f18, f19, f17, dyn, 96, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f16; op2:f18; dest:f17; op1val:0x7b4c; op2val:0xfb4c;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f17, f16, f18, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f17; op2:f15; dest:f16; op1val:0x77a0; op2val:0xf7a0;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f16, f17, f15, dyn, 96, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f14; op2:f16; dest:f15; op1val:0x742a; op2val:0xf42a;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f15, f14, f16, dyn, 96, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f15; op2:f13; dest:f14; op1val:0x7863; op2val:0xf863;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f14, f15, f13, dyn, 96, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f12; op2:f14; dest:f13; op1val:0x79c1; op2val:0xf9c1;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f13, f12, f14, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f13; op2:f11; dest:f12; op1val:0x7a98; op2val:0xfa98;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f12, f13, f11, dyn, 96, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f10; op2:f12; dest:f11; op1val:0x54bd; op2val:0xd4bd;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f11, f10, f12, dyn, 96, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f11; op2:f9; dest:f10; op1val:0x7aef; op2val:0xfaef;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f10, f11, f9, dyn, 96, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f8; op2:f10; dest:f9; op1val:0x7533; op2val:0xf533;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f9, f8, f10, dyn, 96, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f9; op2:f7; dest:f8; op1val:0x721c; op2val:0xf21c;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f8, f9, f7, dyn, 96, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:// rs1==f6, rs2==f8, rd==f7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f6; op2:f8; dest:f7; op1val:0x73a1; op2val:0xf3a1;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f7, f6, f8, dyn, 96, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f7; op2:f5; dest:f6; op1val:0x7a6c; op2val:0xfa6c;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f6, f7, f5, dyn, 96, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:// rs1==f4, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f4; op2:f6; dest:f5; op1val:0x6d25; op2val:0xed25;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f5, f4, f6, dyn, 96, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f5; op2:f3; dest:f4; op1val:0x780f; op2val:0xf80f;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f4, f5, f3, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f2; op2:f4; dest:f3; op1val:0x6efa; op2val:0xeefa;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f3, f2, f4, dyn, 96, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:// rs1==f3, rs2==f1, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f3; op2:f1; dest:f2; op1val:0x79a6; op2val:0xf9a6;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f2, f3, f1, dyn, 96, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f0; op2:f2; dest:f1; op1val:0x7a83; op2val:0xfa83;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f1, f0, f2, dyn, 96, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:// rs1==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f1; op2:f30; dest:f31; op1val:0x7bb4; op2val:0xfbb4;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f1, f30, dyn, 96, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:// rs2==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f0; dest:f31; op1val:0x78b2; op2val:0xf8b2;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f0, dyn, 96, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:// rd==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f31; op2:f30; dest:f0; op1val:0x78c4; op2val:0xf8c4;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f0, f31, f30, dyn, 96, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x789a; op2val:0xf89a;
|
||||
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 68*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_35:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x720e; op2val:0xf20e;
|
||||
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 70*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x78e6; op2val:0xf8e6;
|
||||
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 72*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_37:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x779e; op2val:0xf79e;
|
||||
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 74*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a0e; op2val:0xfa0e;
|
||||
valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 76*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_39:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b62; op2val:0xfb62;
|
||||
valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 78*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b2e; op2val:0xfb2e;
|
||||
valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 80*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_41:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7852; op2val:0xf852;
|
||||
valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 82*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_42:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x79a3; op2val:0xf9a1;
|
||||
valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_43:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a7d; op2val:0xfa7b;
|
||||
valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 86*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x326 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b28; op2val:0xfb26;
|
||||
valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 88*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_45:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x396 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b98; op2val:0xfb96;
|
||||
valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 90*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_46:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x330 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7734; op2val:0xf730;
|
||||
valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 92*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_47:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f5 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7bf7; op2val:0xfbf5;
|
||||
valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 94*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_48:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x255 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a57; op2val:0xfa55;
|
||||
valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 96*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_49:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x109 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7909; op2val:0xf909;
|
||||
valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 98*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_50:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x73c6; op2val:0xf3c6;
|
||||
valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 100*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_51:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x37e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x6f7e; op2val:0xef7e;
|
||||
valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 102*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_52:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x25a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a5a; op2val:0xfa5a;
|
||||
valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 104*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_53:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x286 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a86; op2val:0xfa86;
|
||||
valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 106*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_54:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x70ae; op2val:0xf0ae;
|
||||
valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 108*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_55:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7ac0; op2val:0xfac0;
|
||||
valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 110*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_56:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x779f; op2val:0xf79f;
|
||||
valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 112*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(30393,16,FLEN)
|
||||
NAN_BOXED(63161,16,FLEN)
|
||||
NAN_BOXED(30742,16,FLEN)
|
||||
NAN_BOXED(63510,16,FLEN)
|
||||
NAN_BOXED(31300,16,FLEN)
|
||||
NAN_BOXED(64068,16,FLEN)
|
||||
NAN_BOXED(30623,16,FLEN)
|
||||
NAN_BOXED(30623,16,FLEN)
|
||||
NAN_BOXED(31554,16,FLEN)
|
||||
NAN_BOXED(64322,16,FLEN)
|
||||
NAN_BOXED(29825,16,FLEN)
|
||||
NAN_BOXED(62593,16,FLEN)
|
||||
NAN_BOXED(30961,16,FLEN)
|
||||
NAN_BOXED(63729,16,FLEN)
|
||||
NAN_BOXED(31558,16,FLEN)
|
||||
NAN_BOXED(64326,16,FLEN)
|
||||
NAN_BOXED(31354,16,FLEN)
|
||||
NAN_BOXED(64122,16,FLEN)
|
||||
NAN_BOXED(29941,16,FLEN)
|
||||
NAN_BOXED(62709,16,FLEN)
|
||||
NAN_BOXED(31535,16,FLEN)
|
||||
NAN_BOXED(64303,16,FLEN)
|
||||
NAN_BOXED(30604,16,FLEN)
|
||||
NAN_BOXED(63372,16,FLEN)
|
||||
NAN_BOXED(30449,16,FLEN)
|
||||
NAN_BOXED(63217,16,FLEN)
|
||||
NAN_BOXED(31564,16,FLEN)
|
||||
NAN_BOXED(64332,16,FLEN)
|
||||
NAN_BOXED(30624,16,FLEN)
|
||||
NAN_BOXED(63392,16,FLEN)
|
||||
NAN_BOXED(29738,16,FLEN)
|
||||
NAN_BOXED(62506,16,FLEN)
|
||||
NAN_BOXED(30819,16,FLEN)
|
||||
NAN_BOXED(63587,16,FLEN)
|
||||
NAN_BOXED(31169,16,FLEN)
|
||||
NAN_BOXED(63937,16,FLEN)
|
||||
NAN_BOXED(31384,16,FLEN)
|
||||
NAN_BOXED(64152,16,FLEN)
|
||||
NAN_BOXED(21693,16,FLEN)
|
||||
NAN_BOXED(54461,16,FLEN)
|
||||
NAN_BOXED(31471,16,FLEN)
|
||||
NAN_BOXED(64239,16,FLEN)
|
||||
NAN_BOXED(30003,16,FLEN)
|
||||
NAN_BOXED(62771,16,FLEN)
|
||||
NAN_BOXED(29212,16,FLEN)
|
||||
NAN_BOXED(61980,16,FLEN)
|
||||
NAN_BOXED(29601,16,FLEN)
|
||||
NAN_BOXED(62369,16,FLEN)
|
||||
NAN_BOXED(31340,16,FLEN)
|
||||
NAN_BOXED(64108,16,FLEN)
|
||||
NAN_BOXED(27941,16,FLEN)
|
||||
NAN_BOXED(60709,16,FLEN)
|
||||
NAN_BOXED(30735,16,FLEN)
|
||||
NAN_BOXED(63503,16,FLEN)
|
||||
NAN_BOXED(28410,16,FLEN)
|
||||
NAN_BOXED(61178,16,FLEN)
|
||||
NAN_BOXED(31142,16,FLEN)
|
||||
NAN_BOXED(63910,16,FLEN)
|
||||
NAN_BOXED(31363,16,FLEN)
|
||||
NAN_BOXED(64131,16,FLEN)
|
||||
NAN_BOXED(31668,16,FLEN)
|
||||
NAN_BOXED(64436,16,FLEN)
|
||||
NAN_BOXED(30898,16,FLEN)
|
||||
NAN_BOXED(63666,16,FLEN)
|
||||
NAN_BOXED(30916,16,FLEN)
|
||||
NAN_BOXED(63684,16,FLEN)
|
||||
NAN_BOXED(30874,16,FLEN)
|
||||
NAN_BOXED(63642,16,FLEN)
|
||||
NAN_BOXED(29198,16,FLEN)
|
||||
NAN_BOXED(61966,16,FLEN)
|
||||
NAN_BOXED(30950,16,FLEN)
|
||||
NAN_BOXED(63718,16,FLEN)
|
||||
NAN_BOXED(30622,16,FLEN)
|
||||
NAN_BOXED(63390,16,FLEN)
|
||||
NAN_BOXED(31246,16,FLEN)
|
||||
NAN_BOXED(64014,16,FLEN)
|
||||
NAN_BOXED(31586,16,FLEN)
|
||||
NAN_BOXED(64354,16,FLEN)
|
||||
NAN_BOXED(31534,16,FLEN)
|
||||
NAN_BOXED(64302,16,FLEN)
|
||||
NAN_BOXED(30802,16,FLEN)
|
||||
NAN_BOXED(63570,16,FLEN)
|
||||
NAN_BOXED(31139,16,FLEN)
|
||||
NAN_BOXED(63905,16,FLEN)
|
||||
NAN_BOXED(31357,16,FLEN)
|
||||
NAN_BOXED(64123,16,FLEN)
|
||||
NAN_BOXED(31528,16,FLEN)
|
||||
NAN_BOXED(64294,16,FLEN)
|
||||
NAN_BOXED(31640,16,FLEN)
|
||||
NAN_BOXED(64406,16,FLEN)
|
||||
NAN_BOXED(30516,16,FLEN)
|
||||
NAN_BOXED(63280,16,FLEN)
|
||||
NAN_BOXED(31735,16,FLEN)
|
||||
NAN_BOXED(64501,16,FLEN)
|
||||
NAN_BOXED(31319,16,FLEN)
|
||||
NAN_BOXED(64085,16,FLEN)
|
||||
NAN_BOXED(30985,16,FLEN)
|
||||
NAN_BOXED(63753,16,FLEN)
|
||||
NAN_BOXED(29638,16,FLEN)
|
||||
NAN_BOXED(62406,16,FLEN)
|
||||
NAN_BOXED(28542,16,FLEN)
|
||||
NAN_BOXED(61310,16,FLEN)
|
||||
NAN_BOXED(31322,16,FLEN)
|
||||
NAN_BOXED(64090,16,FLEN)
|
||||
NAN_BOXED(31366,16,FLEN)
|
||||
NAN_BOXED(64134,16,FLEN)
|
||||
NAN_BOXED(28846,16,FLEN)
|
||||
NAN_BOXED(61614,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(64192,16,FLEN)
|
||||
NAN_BOXED(30623,16,FLEN)
|
||||
NAN_BOXED(63391,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 114*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Sat May 6 10:51:45 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fclass.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fclass.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fclass_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fclass_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f30; dest:x30; op1val:0x8000; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f28; dest:x28; op1val:0x8001; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f26; dest:x26; op1val:0x83fe; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f25; dest:x25; op1val:0x3ff; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f24; dest:x24; op1val:0x83ff; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f23; dest:x23; op1val:0x400; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f22; dest:x22; op1val:0x8400; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f21; dest:x21; op1val:0x401; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f20; dest:x20; op1val:0x8455; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f19; dest:x19; op1val:0x7bff; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f18; dest:x18; op1val:0xfbff; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f17; dest:x17; op1val:0x7c00; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f16; dest:x16; op1val:0xfc00; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f15; dest:x15; op1val:0x7e00; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f14; dest:x14; op1val:0xfe00; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f13; dest:x13; op1val:0x7e01; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f12; dest:x12; op1val:0xfe55; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f11; dest:x11; op1val:0x7c01; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f10; dest:x10; op1val:0xfd55; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f9; dest:x9; op1val:0x3c00; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fclass.h ; op1:f8; dest:x8; op1val:0xbc00; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fclass.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fclass.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fclass.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fclass.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fclass.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fclass.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fclass.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fclass.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP_NRM(fclass.h, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(1,16,FLEN)
|
||||
NAN_BOXED(32769,16,FLEN)
|
||||
NAN_BOXED(2,16,FLEN)
|
||||
NAN_BOXED(33790,16,FLEN)
|
||||
NAN_BOXED(1023,16,FLEN)
|
||||
NAN_BOXED(33791,16,FLEN)
|
||||
NAN_BOXED(1024,16,FLEN)
|
||||
NAN_BOXED(33792,16,FLEN)
|
||||
NAN_BOXED(1025,16,FLEN)
|
||||
NAN_BOXED(33877,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(31744,16,FLEN)
|
||||
NAN_BOXED(64512,16,FLEN)
|
||||
NAN_BOXED(32256,16,FLEN)
|
||||
NAN_BOXED(65024,16,FLEN)
|
||||
NAN_BOXED(32257,16,FLEN)
|
||||
NAN_BOXED(65109,16,FLEN)
|
||||
NAN_BOXED(31745,16,FLEN)
|
||||
NAN_BOXED(64853,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:39:52 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.w.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.h.w instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.w_b25 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.w_b25)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f31, x31, dyn, 0, 0, x3, 0*4, x4, x1, x2,lw)
|
||||
|
||||
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f30, x30, dyn, 0, 0, x3, 1*4, x4, x1, x2,lw)
|
||||
|
||||
inst_2:// rs1==x29, rd==f29,rs1_val == -1 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x29; dest:f29; op1val:-0x1; valaddr_reg:x3;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f29, x29, dyn, 0, 0, x3, 2*4, x4, x1, x2,lw)
|
||||
|
||||
inst_3:// rs1==x28, rd==f28,rs1_val == 2147483647 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x28; dest:f28; op1val:0x7fffffff; valaddr_reg:x3;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f28, x28, dyn, 0, 0, x3, 3*4, x4, x1, x2,lw)
|
||||
|
||||
inst_4:// rs1==x27, rd==f27,rs1_val == -2147483647 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x27; dest:f27; op1val:-0x7fffffff; valaddr_reg:x3;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f27, x27, dyn, 0, 0, x3, 4*4, x4, x1, x2,lw)
|
||||
|
||||
inst_5:// rs1==x26, rd==f26,rs1_val == 1227077728 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x26; dest:f26; op1val:0x4923b860; valaddr_reg:x3;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f26, x26, dyn, 0, 0, x3, 5*4, x4, x1, x2,lw)
|
||||
|
||||
inst_6:// rs1==x25, rd==f25,rs1_val == -1227077728 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x25; dest:f25; op1val:-0x4923b860; valaddr_reg:x3;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f25, x25, dyn, 0, 0, x3, 6*4, x4, x1, x2,lw)
|
||||
|
||||
inst_7:// rs1==x24, rd==f24,
|
||||
/* opcode: fcvt.h.w ; op1:x24; dest:f24; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f24, x24, dyn, 0, 0, x3, 7*4, x4, x1, x2,lw)
|
||||
|
||||
inst_8:// rs1==x23, rd==f23,
|
||||
/* opcode: fcvt.h.w ; op1:x23; dest:f23; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:8*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f23, x23, dyn, 0, 0, x3, 8*4, x4, x1, x2,lw)
|
||||
|
||||
inst_9:// rs1==x22, rd==f22,
|
||||
/* opcode: fcvt.h.w ; op1:x22; dest:f22; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:9*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f22, x22, dyn, 0, 0, x3, 9*4, x4, x1, x2,lw)
|
||||
|
||||
inst_10:// rs1==x21, rd==f21,
|
||||
/* opcode: fcvt.h.w ; op1:x21; dest:f21; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:10*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f21, x21, dyn, 0, 0, x3, 10*4, x4, x1, x2,lw)
|
||||
|
||||
inst_11:// rs1==x20, rd==f20,
|
||||
/* opcode: fcvt.h.w ; op1:x20; dest:f20; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:11*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f20, x20, dyn, 0, 0, x3, 11*4, x4, x1, x2,lw)
|
||||
|
||||
inst_12:// rs1==x19, rd==f19,
|
||||
/* opcode: fcvt.h.w ; op1:x19; dest:f19; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:12*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f19, x19, dyn, 0, 0, x3, 12*4, x4, x1, x2,lw)
|
||||
|
||||
inst_13:// rs1==x18, rd==f18,
|
||||
/* opcode: fcvt.h.w ; op1:x18; dest:f18; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:13*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f18, x18, dyn, 0, 0, x3, 13*4, x4, x1, x2,lw)
|
||||
|
||||
inst_14:// rs1==x17, rd==f17,
|
||||
/* opcode: fcvt.h.w ; op1:x17; dest:f17; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:14*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f17, x17, dyn, 0, 0, x3, 14*4, x4, x1, x2,lw)
|
||||
|
||||
inst_15:// rs1==x16, rd==f16,
|
||||
/* opcode: fcvt.h.w ; op1:x16; dest:f16; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:15*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f16, x16, dyn, 0, 0, x3, 15*4, x4, x1, x2,lw)
|
||||
|
||||
inst_16:// rs1==x15, rd==f15,
|
||||
/* opcode: fcvt.h.w ; op1:x15; dest:f15; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:16*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f15, x15, dyn, 0, 0, x3, 16*4, x4, x1, x2,lw)
|
||||
|
||||
inst_17:// rs1==x14, rd==f14,
|
||||
/* opcode: fcvt.h.w ; op1:x14; dest:f14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f14, x14, dyn, 0, 0, x3, 17*4, x4, x1, x2,lw)
|
||||
|
||||
inst_18:// rs1==x13, rd==f13,
|
||||
/* opcode: fcvt.h.w ; op1:x13; dest:f13; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:18*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f13, x13, dyn, 0, 0, x3, 18*4, x4, x1, x2,lw)
|
||||
|
||||
inst_19:// rs1==x12, rd==f12,
|
||||
/* opcode: fcvt.h.w ; op1:x12; dest:f12; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:19*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f12, x12, dyn, 0, 0, x3, 19*4, x4, x1, x2,lw)
|
||||
|
||||
inst_20:// rs1==x11, rd==f11,
|
||||
/* opcode: fcvt.h.w ; op1:x11; dest:f11; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:20*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f11, x11, dyn, 0, 0, x3, 20*4, x4, x1, x2,lw)
|
||||
|
||||
inst_21:// rs1==x10, rd==f10,
|
||||
/* opcode: fcvt.h.w ; op1:x10; dest:f10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f10, x10, dyn, 0, 0, x3, 21*4, x4, x1, x2,lw)
|
||||
|
||||
inst_22:// rs1==x9, rd==f9,
|
||||
/* opcode: fcvt.h.w ; op1:x9; dest:f9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f9, x9, dyn, 0, 0, x3, 22*4, x4, x1, x2,lw)
|
||||
|
||||
inst_23:// rs1==x8, rd==f8,
|
||||
/* opcode: fcvt.h.w ; op1:x8; dest:f8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f8, x8, dyn, 0, 0, x3, 23*4, x4, x1, x2,lw)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==x7, rd==f7,
|
||||
/* opcode: fcvt.h.w ; op1:x7; dest:f7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f7, x7, dyn, 0, 0, x8, 0*4, x9, x1, x2,lw)
|
||||
|
||||
inst_25:// rs1==x6, rd==f6,
|
||||
/* opcode: fcvt.h.w ; op1:x6; dest:f6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f6, x6, dyn, 0, 0, x8, 1*4, x9, x1, x2,lw)
|
||||
|
||||
inst_26:// rs1==x5, rd==f5,
|
||||
/* opcode: fcvt.h.w ; op1:x5; dest:f5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f5, x5, dyn, 0, 0, x8, 2*4, x9, x1, x6,lw)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==x4, rd==f4,
|
||||
/* opcode: fcvt.h.w ; op1:x4; dest:f4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f4, x4, dyn, 0, 0, x8, 3*4, x9, x5, x6,lw)
|
||||
|
||||
inst_28:// rs1==x3, rd==f3,
|
||||
/* opcode: fcvt.h.w ; op1:x3; dest:f3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f3, x3, dyn, 0, 0, x8, 4*4, x9, x5, x6,lw)
|
||||
|
||||
inst_29:// rs1==x2, rd==f2,
|
||||
/* opcode: fcvt.h.w ; op1:x2; dest:f2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f2, x2, dyn, 0, 0, x8, 5*4, x9, x5, x6,lw)
|
||||
|
||||
inst_30:// rs1==x1, rd==f1,
|
||||
/* opcode: fcvt.h.w ; op1:x1; dest:f1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f1, x1, dyn, 0, 0, x8, 6*4, x9, x5, x6,lw)
|
||||
|
||||
inst_31:// rs1==x0, rd==f0,
|
||||
/* opcode: fcvt.h.w ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f0, x0, dyn, 0, 0, x8, 7*4, x9, x5, x6,lw)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
.word 0;
|
||||
.word 1;
|
||||
.word -1;
|
||||
.word 2147483647;
|
||||
.word -2147483647;
|
||||
.word 1227077728;
|
||||
.word -1227077728;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
test_dataset_1:
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:39:52 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.w.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.h.w instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.w_b26 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.w_b26)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f31, x31, dyn, 0, 0, x3, 0*4, x4, x1, x2,lw)
|
||||
|
||||
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f30, x30, dyn, 0, 0, x3, 1*4, x4, x1, x2,lw)
|
||||
|
||||
inst_2:// rs1==x29, rd==f29,rs1_val == 2 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x29; dest:f29; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f29, x29, dyn, 0, 0, x3, 2*4, x4, x1, x2,lw)
|
||||
|
||||
inst_3:// rs1==x28, rd==f28,rs1_val == 7 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x28; dest:f28; op1val:0x7; valaddr_reg:x3;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f28, x28, dyn, 0, 0, x3, 3*4, x4, x1, x2,lw)
|
||||
|
||||
inst_4:// rs1==x27, rd==f27,rs1_val == 15 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x27; dest:f27; op1val:0xf; valaddr_reg:x3;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f27, x27, dyn, 0, 0, x3, 4*4, x4, x1, x2,lw)
|
||||
|
||||
inst_5:// rs1==x26, rd==f26,rs1_val == 16 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x26; dest:f26; op1val:0x10; valaddr_reg:x3;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f26, x26, dyn, 0, 0, x3, 5*4, x4, x1, x2,lw)
|
||||
|
||||
inst_6:// rs1==x25, rd==f25,rs1_val == 45 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x25; dest:f25; op1val:0x2d; valaddr_reg:x3;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f25, x25, dyn, 0, 0, x3, 6*4, x4, x1, x2,lw)
|
||||
|
||||
inst_7:// rs1==x24, rd==f24,rs1_val == 123 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x24; dest:f24; op1val:0x7b; valaddr_reg:x3;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f24, x24, dyn, 0, 0, x3, 7*4, x4, x1, x2,lw)
|
||||
|
||||
inst_8:// rs1==x23, rd==f23,rs1_val == 253 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x23; dest:f23; op1val:0xfd; valaddr_reg:x3;
|
||||
val_offset:8*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f23, x23, dyn, 0, 0, x3, 8*4, x4, x1, x2,lw)
|
||||
|
||||
inst_9:// rs1==x22, rd==f22,rs1_val == 398 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x22; dest:f22; op1val:0x18e; valaddr_reg:x3;
|
||||
val_offset:9*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f22, x22, dyn, 0, 0, x3, 9*4, x4, x1, x2,lw)
|
||||
|
||||
inst_10:// rs1==x21, rd==f21,rs1_val == 676 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x21; dest:f21; op1val:0x2a4; valaddr_reg:x3;
|
||||
val_offset:10*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f21, x21, dyn, 0, 0, x3, 10*4, x4, x1, x2,lw)
|
||||
|
||||
inst_11:// rs1==x20, rd==f20,rs1_val == 1094 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x20; dest:f20; op1val:0x446; valaddr_reg:x3;
|
||||
val_offset:11*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f20, x20, dyn, 0, 0, x3, 11*4, x4, x1, x2,lw)
|
||||
|
||||
inst_12:// rs1==x19, rd==f19,rs1_val == 4055 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x19; dest:f19; op1val:0xfd7; valaddr_reg:x3;
|
||||
val_offset:12*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f19, x19, dyn, 0, 0, x3, 12*4, x4, x1, x2,lw)
|
||||
|
||||
inst_13:// rs1==x18, rd==f18,rs1_val == 6781 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x18; dest:f18; op1val:0x1a7d; valaddr_reg:x3;
|
||||
val_offset:13*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f18, x18, dyn, 0, 0, x3, 13*4, x4, x1, x2,lw)
|
||||
|
||||
inst_14:// rs1==x17, rd==f17,rs1_val == 9438 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x17; dest:f17; op1val:0x24de; valaddr_reg:x3;
|
||||
val_offset:14*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f17, x17, dyn, 0, 0, x3, 14*4, x4, x1, x2,lw)
|
||||
|
||||
inst_15:// rs1==x16, rd==f16,rs1_val == 24575 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x16; dest:f16; op1val:0x5fff; valaddr_reg:x3;
|
||||
val_offset:15*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f16, x16, dyn, 0, 0, x3, 15*4, x4, x1, x2,lw)
|
||||
|
||||
inst_16:// rs1==x15, rd==f15,rs1_val == 56436 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x15; dest:f15; op1val:0xdc74; valaddr_reg:x3;
|
||||
val_offset:16*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f15, x15, dyn, 0, 0, x3, 16*4, x4, x1, x2,lw)
|
||||
|
||||
inst_17:// rs1==x14, rd==f14,rs1_val == 71376 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x14; dest:f14; op1val:0x116d0; valaddr_reg:x3;
|
||||
val_offset:17*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f14, x14, dyn, 0, 0, x3, 17*4, x4, x1, x2,lw)
|
||||
|
||||
inst_18:// rs1==x13, rd==f13,rs1_val == 241276 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x13; dest:f13; op1val:0x3ae7c; valaddr_reg:x3;
|
||||
val_offset:18*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f13, x13, dyn, 0, 0, x3, 18*4, x4, x1, x2,lw)
|
||||
|
||||
inst_19:// rs1==x12, rd==f12,rs1_val == 334857 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x12; dest:f12; op1val:0x51c09; valaddr_reg:x3;
|
||||
val_offset:19*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f12, x12, dyn, 0, 0, x3, 19*4, x4, x1, x2,lw)
|
||||
|
||||
inst_20:// rs1==x11, rd==f11,rs1_val == 896618 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x11; dest:f11; op1val:0xdae6a; valaddr_reg:x3;
|
||||
val_offset:20*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f11, x11, dyn, 0, 0, x3, 20*4, x4, x1, x2,lw)
|
||||
|
||||
inst_21:// rs1==x10, rd==f10,rs1_val == 1848861 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x10; dest:f10; op1val:0x1c361d; valaddr_reg:x3;
|
||||
val_offset:21*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f10, x10, dyn, 0, 0, x3, 21*4, x4, x1, x2,lw)
|
||||
|
||||
inst_22:// rs1==x9, rd==f9,rs1_val == 3864061 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x9; dest:f9; op1val:0x3af5fd; valaddr_reg:x3;
|
||||
val_offset:22*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f9, x9, dyn, 0, 0, x3, 22*4, x4, x1, x2,lw)
|
||||
|
||||
inst_23:// rs1==x8, rd==f8,rs1_val == 6573466 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x8; dest:f8; op1val:0x644d9a; valaddr_reg:x3;
|
||||
val_offset:23*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f8, x8, dyn, 0, 0, x3, 23*4, x4, x1, x2,lw)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==x7, rd==f7,rs1_val == 12789625 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x7; dest:f7; op1val:0xc32779; valaddr_reg:x8;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f7, x7, dyn, 0, 0, x8, 0*4, x9, x1, x2,lw)
|
||||
|
||||
inst_25:// rs1==x6, rd==f6,rs1_val == 32105925 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x6; dest:f6; op1val:0x1e9e5c5; valaddr_reg:x8;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f6, x6, dyn, 0, 0, x8, 1*4, x9, x1, x2,lw)
|
||||
|
||||
inst_26:// rs1==x5, rd==f5,rs1_val == 45276376 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x5; dest:f5; op1val:0x2b2dcd8; valaddr_reg:x8;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f5, x5, dyn, 0, 0, x8, 2*4, x9, x1, x6,lw)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==x4, rd==f4,rs1_val == 107790943 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x4; dest:f4; op1val:0x66cc25f; valaddr_reg:x8;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f4, x4, dyn, 0, 0, x8, 3*4, x9, x5, x6,lw)
|
||||
|
||||
inst_28:// rs1==x3, rd==f3,rs1_val == 231549045 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x3; dest:f3; op1val:0xdcd2875; valaddr_reg:x8;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f3, x3, dyn, 0, 0, x8, 4*4, x9, x5, x6,lw)
|
||||
|
||||
inst_29:// rs1==x2, rd==f2,rs1_val == 339827553 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x2; dest:f2; op1val:0x14415b61; valaddr_reg:x8;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f2, x2, dyn, 0, 0, x8, 5*4, x9, x5, x6,lw)
|
||||
|
||||
inst_30:// rs1==x1, rd==f1,rs1_val == 1027494066 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x1; dest:f1; op1val:0x3d3e50b2; valaddr_reg:x8;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f1, x1, dyn, 0, 0, x8, 6*4, x9, x5, x6,lw)
|
||||
|
||||
inst_31:// rs1==x0, rd==f0,rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f0, x0, dyn, 0, 0, x8, 7*4, x9, x5, x6,lw)
|
||||
|
||||
inst_32:// rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.w ; op1:x31; dest:f31; op1val:0x5ea40361; valaddr_reg:x8;
|
||||
val_offset:8*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.w, f31, x31, dyn, 0, 0, x8, 8*4, x9, x5, x6,lw)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
.word 0;
|
||||
.word 1;
|
||||
.word 2;
|
||||
.word 7;
|
||||
.word 15;
|
||||
.word 16;
|
||||
.word 45;
|
||||
.word 123;
|
||||
.word 253;
|
||||
.word 398;
|
||||
.word 676;
|
||||
.word 1094;
|
||||
.word 4055;
|
||||
.word 6781;
|
||||
.word 9438;
|
||||
.word 24575;
|
||||
.word 56436;
|
||||
.word 71376;
|
||||
.word 241276;
|
||||
.word 334857;
|
||||
.word 896618;
|
||||
.word 1848861;
|
||||
.word 3864061;
|
||||
.word 6573466;
|
||||
test_dataset_1:
|
||||
.word 12789625;
|
||||
.word 32105925;
|
||||
.word 45276376;
|
||||
.word 107790943;
|
||||
.word 231549045;
|
||||
.word 339827553;
|
||||
.word 1027494066;
|
||||
.word 0;
|
||||
.word 1587807073;
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 12*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:07 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.wu.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.h.wu instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.wu_b25 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.wu_b25)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f31, x31, dyn, 0, 0, x3, 0*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f30, x30, dyn, 0, 0, x3, 1*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_2:// rs1==x29, rd==f29,rs1_val == 4294967295 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x29; dest:f29; op1val:0xffffffff; valaddr_reg:x3;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f29, x29, dyn, 0, 0, x3, 2*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_3:// rs1==x28, rd==f28,rs1_val == 2454155456 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x28; dest:f28; op1val:0x924770c0; valaddr_reg:x3;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f28, x28, dyn, 0, 0, x3, 3*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_4:// rs1==x27, rd==f27,
|
||||
/* opcode: fcvt.h.wu ; op1:x27; dest:f27; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f27, x27, dyn, 0, 0, x3, 4*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_5:// rs1==x26, rd==f26,
|
||||
/* opcode: fcvt.h.wu ; op1:x26; dest:f26; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f26, x26, dyn, 0, 0, x3, 5*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_6:// rs1==x25, rd==f25,
|
||||
/* opcode: fcvt.h.wu ; op1:x25; dest:f25; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f25, x25, dyn, 0, 0, x3, 6*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_7:// rs1==x24, rd==f24,
|
||||
/* opcode: fcvt.h.wu ; op1:x24; dest:f24; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f24, x24, dyn, 0, 0, x3, 7*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_8:// rs1==x23, rd==f23,
|
||||
/* opcode: fcvt.h.wu ; op1:x23; dest:f23; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:8*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f23, x23, dyn, 0, 0, x3, 8*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_9:// rs1==x22, rd==f22,
|
||||
/* opcode: fcvt.h.wu ; op1:x22; dest:f22; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:9*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f22, x22, dyn, 0, 0, x3, 9*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_10:// rs1==x21, rd==f21,
|
||||
/* opcode: fcvt.h.wu ; op1:x21; dest:f21; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:10*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f21, x21, dyn, 0, 0, x3, 10*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_11:// rs1==x20, rd==f20,
|
||||
/* opcode: fcvt.h.wu ; op1:x20; dest:f20; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:11*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f20, x20, dyn, 0, 0, x3, 11*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_12:// rs1==x19, rd==f19,
|
||||
/* opcode: fcvt.h.wu ; op1:x19; dest:f19; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:12*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f19, x19, dyn, 0, 0, x3, 12*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_13:// rs1==x18, rd==f18,
|
||||
/* opcode: fcvt.h.wu ; op1:x18; dest:f18; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:13*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f18, x18, dyn, 0, 0, x3, 13*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_14:// rs1==x17, rd==f17,
|
||||
/* opcode: fcvt.h.wu ; op1:x17; dest:f17; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:14*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f17, x17, dyn, 0, 0, x3, 14*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_15:// rs1==x16, rd==f16,
|
||||
/* opcode: fcvt.h.wu ; op1:x16; dest:f16; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:15*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f16, x16, dyn, 0, 0, x3, 15*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_16:// rs1==x15, rd==f15,
|
||||
/* opcode: fcvt.h.wu ; op1:x15; dest:f15; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:16*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f15, x15, dyn, 0, 0, x3, 16*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_17:// rs1==x14, rd==f14,
|
||||
/* opcode: fcvt.h.wu ; op1:x14; dest:f14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f14, x14, dyn, 0, 0, x3, 17*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_18:// rs1==x13, rd==f13,
|
||||
/* opcode: fcvt.h.wu ; op1:x13; dest:f13; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:18*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f13, x13, dyn, 0, 0, x3, 18*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_19:// rs1==x12, rd==f12,
|
||||
/* opcode: fcvt.h.wu ; op1:x12; dest:f12; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:19*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f12, x12, dyn, 0, 0, x3, 19*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_20:// rs1==x11, rd==f11,
|
||||
/* opcode: fcvt.h.wu ; op1:x11; dest:f11; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:20*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f11, x11, dyn, 0, 0, x3, 20*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_21:// rs1==x10, rd==f10,
|
||||
/* opcode: fcvt.h.wu ; op1:x10; dest:f10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f10, x10, dyn, 0, 0, x3, 21*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_22:// rs1==x9, rd==f9,
|
||||
/* opcode: fcvt.h.wu ; op1:x9; dest:f9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f9, x9, dyn, 0, 0, x3, 22*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_23:// rs1==x8, rd==f8,
|
||||
/* opcode: fcvt.h.wu ; op1:x8; dest:f8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f8, x8, dyn, 0, 0, x3, 23*4, x4, x1, x2,LREGWU)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==x7, rd==f7,
|
||||
/* opcode: fcvt.h.wu ; op1:x7; dest:f7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f7, x7, dyn, 0, 0, x8, 0*4, x9, x1, x2,LREGWU)
|
||||
|
||||
inst_25:// rs1==x6, rd==f6,
|
||||
/* opcode: fcvt.h.wu ; op1:x6; dest:f6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f6, x6, dyn, 0, 0, x8, 1*4, x9, x1, x2,LREGWU)
|
||||
|
||||
inst_26:// rs1==x5, rd==f5,
|
||||
/* opcode: fcvt.h.wu ; op1:x5; dest:f5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f5, x5, dyn, 0, 0, x8, 2*4, x9, x1, x6,LREGWU)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==x4, rd==f4,
|
||||
/* opcode: fcvt.h.wu ; op1:x4; dest:f4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f4, x4, dyn, 0, 0, x8, 3*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_28:// rs1==x3, rd==f3,
|
||||
/* opcode: fcvt.h.wu ; op1:x3; dest:f3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f3, x3, dyn, 0, 0, x8, 4*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_29:// rs1==x2, rd==f2,
|
||||
/* opcode: fcvt.h.wu ; op1:x2; dest:f2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f2, x2, dyn, 0, 0, x8, 5*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_30:// rs1==x1, rd==f1,
|
||||
/* opcode: fcvt.h.wu ; op1:x1; dest:f1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f1, x1, dyn, 0, 0, x8, 6*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_31:// rs1==x0, rd==f0,
|
||||
/* opcode: fcvt.h.wu ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f0, x0, dyn, 0, 0, x8, 7*4, x9, x5, x6,LREGWU)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
.word 0;
|
||||
.word 1;
|
||||
.word 4294967295;
|
||||
.word 2454155456;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
test_dataset_1:
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
.word 0;
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,327 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:07 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.wu.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.h.wu instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.wu_b26 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.wu_b26)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f31, x31, dyn, 0, 0, x3, 0*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f30, x30, dyn, 0, 0, x3, 1*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_2:// rs1==x29, rd==f29,rs1_val == 2 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x29; dest:f29; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f29, x29, dyn, 0, 0, x3, 2*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_3:// rs1==x28, rd==f28,rs1_val == 7 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x28; dest:f28; op1val:0x7; valaddr_reg:x3;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f28, x28, dyn, 0, 0, x3, 3*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_4:// rs1==x27, rd==f27,rs1_val == 15 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x27; dest:f27; op1val:0xf; valaddr_reg:x3;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f27, x27, dyn, 0, 0, x3, 4*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_5:// rs1==x26, rd==f26,rs1_val == 16 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x26; dest:f26; op1val:0x10; valaddr_reg:x3;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f26, x26, dyn, 0, 0, x3, 5*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_6:// rs1==x25, rd==f25,rs1_val == 45 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x25; dest:f25; op1val:0x2d; valaddr_reg:x3;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f25, x25, dyn, 0, 0, x3, 6*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_7:// rs1==x24, rd==f24,rs1_val == 123 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x24; dest:f24; op1val:0x7b; valaddr_reg:x3;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f24, x24, dyn, 0, 0, x3, 7*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_8:// rs1==x23, rd==f23,rs1_val == 253 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x23; dest:f23; op1val:0xfd; valaddr_reg:x3;
|
||||
val_offset:8*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f23, x23, dyn, 0, 0, x3, 8*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_9:// rs1==x22, rd==f22,rs1_val == 398 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x22; dest:f22; op1val:0x18e; valaddr_reg:x3;
|
||||
val_offset:9*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f22, x22, dyn, 0, 0, x3, 9*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_10:// rs1==x21, rd==f21,rs1_val == 676 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x21; dest:f21; op1val:0x2a4; valaddr_reg:x3;
|
||||
val_offset:10*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f21, x21, dyn, 0, 0, x3, 10*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_11:// rs1==x20, rd==f20,rs1_val == 1094 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x20; dest:f20; op1val:0x446; valaddr_reg:x3;
|
||||
val_offset:11*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f20, x20, dyn, 0, 0, x3, 11*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_12:// rs1==x19, rd==f19,rs1_val == 4055 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x19; dest:f19; op1val:0xfd7; valaddr_reg:x3;
|
||||
val_offset:12*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f19, x19, dyn, 0, 0, x3, 12*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_13:// rs1==x18, rd==f18,rs1_val == 6781 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x18; dest:f18; op1val:0x1a7d; valaddr_reg:x3;
|
||||
val_offset:13*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f18, x18, dyn, 0, 0, x3, 13*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_14:// rs1==x17, rd==f17,rs1_val == 9438 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x17; dest:f17; op1val:0x24de; valaddr_reg:x3;
|
||||
val_offset:14*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f17, x17, dyn, 0, 0, x3, 14*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_15:// rs1==x16, rd==f16,rs1_val == 24575 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x16; dest:f16; op1val:0x5fff; valaddr_reg:x3;
|
||||
val_offset:15*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f16, x16, dyn, 0, 0, x3, 15*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_16:// rs1==x15, rd==f15,rs1_val == 56436 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x15; dest:f15; op1val:0xdc74; valaddr_reg:x3;
|
||||
val_offset:16*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f15, x15, dyn, 0, 0, x3, 16*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_17:// rs1==x14, rd==f14,rs1_val == 71376 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x14; dest:f14; op1val:0x116d0; valaddr_reg:x3;
|
||||
val_offset:17*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f14, x14, dyn, 0, 0, x3, 17*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_18:// rs1==x13, rd==f13,rs1_val == 241276 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x13; dest:f13; op1val:0x3ae7c; valaddr_reg:x3;
|
||||
val_offset:18*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f13, x13, dyn, 0, 0, x3, 18*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_19:// rs1==x12, rd==f12,rs1_val == 334857 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x12; dest:f12; op1val:0x51c09; valaddr_reg:x3;
|
||||
val_offset:19*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f12, x12, dyn, 0, 0, x3, 19*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_20:// rs1==x11, rd==f11,rs1_val == 896618 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x11; dest:f11; op1val:0xdae6a; valaddr_reg:x3;
|
||||
val_offset:20*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f11, x11, dyn, 0, 0, x3, 20*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_21:// rs1==x10, rd==f10,rs1_val == 1848861 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x10; dest:f10; op1val:0x1c361d; valaddr_reg:x3;
|
||||
val_offset:21*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f10, x10, dyn, 0, 0, x3, 21*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_22:// rs1==x9, rd==f9,rs1_val == 3864061 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x9; dest:f9; op1val:0x3af5fd; valaddr_reg:x3;
|
||||
val_offset:22*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f9, x9, dyn, 0, 0, x3, 22*4, x4, x1, x2,LREGWU)
|
||||
|
||||
inst_23:// rs1==x8, rd==f8,rs1_val == 6573466 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x8; dest:f8; op1val:0x644d9a; valaddr_reg:x3;
|
||||
val_offset:23*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f8, x8, dyn, 0, 0, x3, 23*4, x4, x1, x2,LREGWU)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==x7, rd==f7,rs1_val == 12789625 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x7; dest:f7; op1val:0xc32779; valaddr_reg:x8;
|
||||
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f7, x7, dyn, 0, 0, x8, 0*4, x9, x1, x2,LREGWU)
|
||||
|
||||
inst_25:// rs1==x6, rd==f6,rs1_val == 32105925 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x6; dest:f6; op1val:0x1e9e5c5; valaddr_reg:x8;
|
||||
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f6, x6, dyn, 0, 0, x8, 1*4, x9, x1, x2,LREGWU)
|
||||
|
||||
inst_26:// rs1==x5, rd==f5,rs1_val == 45276376 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x5; dest:f5; op1val:0x2b2dcd8; valaddr_reg:x8;
|
||||
val_offset:2*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f5, x5, dyn, 0, 0, x8, 2*4, x9, x1, x6,LREGWU)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==x4, rd==f4,rs1_val == 107790943 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x4; dest:f4; op1val:0x66cc25f; valaddr_reg:x8;
|
||||
val_offset:3*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f4, x4, dyn, 0, 0, x8, 3*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_28:// rs1==x3, rd==f3,rs1_val == 231549045 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x3; dest:f3; op1val:0xdcd2875; valaddr_reg:x8;
|
||||
val_offset:4*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f3, x3, dyn, 0, 0, x8, 4*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_29:// rs1==x2, rd==f2,rs1_val == 339827553 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x2; dest:f2; op1val:0x14415b61; valaddr_reg:x8;
|
||||
val_offset:5*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f2, x2, dyn, 0, 0, x8, 5*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_30:// rs1==x1, rd==f1,rs1_val == 1027494066 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x1; dest:f1; op1val:0x3d3e50b2; valaddr_reg:x8;
|
||||
val_offset:6*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f1, x1, dyn, 0, 0, x8, 6*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_31:// rs1==x0, rd==f0,rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f0, x0, dyn, 0, 0, x8, 7*4, x9, x5, x6,LREGWU)
|
||||
|
||||
inst_32:// rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
|
||||
/* opcode: fcvt.h.wu ; op1:x31; dest:f31; op1val:0x5ea40361; valaddr_reg:x8;
|
||||
val_offset:8*4; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val: 0*/
|
||||
TEST_FPIO_OP(fcvt.h.wu, f31, x31, dyn, 0, 0, x8, 8*4, x9, x5, x6,LREGWU)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
.word 0;
|
||||
.word 1;
|
||||
.word 2;
|
||||
.word 7;
|
||||
.word 15;
|
||||
.word 16;
|
||||
.word 45;
|
||||
.word 123;
|
||||
.word 253;
|
||||
.word 398;
|
||||
.word 676;
|
||||
.word 1094;
|
||||
.word 4055;
|
||||
.word 6781;
|
||||
.word 9438;
|
||||
.word 24575;
|
||||
.word 56436;
|
||||
.word 71376;
|
||||
.word 241276;
|
||||
.word 334857;
|
||||
.word 896618;
|
||||
.word 1848861;
|
||||
.word 3864061;
|
||||
.word 6573466;
|
||||
test_dataset_1:
|
||||
.word 12789625;
|
||||
.word 32105925;
|
||||
.word 45276376;
|
||||
.word 107790943;
|
||||
.word 231549045;
|
||||
.word 339827553;
|
||||
.word 1027494066;
|
||||
.word 0;
|
||||
.word 1587807073;
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 12*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x8000; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x8001; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x83fe; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x3ff; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x83ff; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x400; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x8400; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x401; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x8455; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x7bff; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0xfbff; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x7c00; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0xfc00; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x7e00; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xfe00; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x7e01; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0xfe55; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x7c01; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0xfd55; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x3c00; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0xbc00; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(1,16,FLEN)
|
||||
NAN_BOXED(32769,16,FLEN)
|
||||
NAN_BOXED(2,16,FLEN)
|
||||
NAN_BOXED(33790,16,FLEN)
|
||||
NAN_BOXED(1023,16,FLEN)
|
||||
NAN_BOXED(33791,16,FLEN)
|
||||
NAN_BOXED(1024,16,FLEN)
|
||||
NAN_BOXED(33792,16,FLEN)
|
||||
NAN_BOXED(1025,16,FLEN)
|
||||
NAN_BOXED(33877,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(31744,16,FLEN)
|
||||
NAN_BOXED(64512,16,FLEN)
|
||||
NAN_BOXED(32256,16,FLEN)
|
||||
NAN_BOXED(65024,16,FLEN)
|
||||
NAN_BOXED(32257,16,FLEN)
|
||||
NAN_BOXED(65109,16,FLEN)
|
||||
NAN_BOXED(31745,16,FLEN)
|
||||
NAN_BOXED(64853,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,383 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b22 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b22)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x35b7; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x3a4f; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x3cd3; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x4340; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x474b; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x12 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0xca9d; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x13 and fm1 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x4ca4; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x5215; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x15 and fm1 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x554f; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 1 and fe1 == 0x16 and fm1 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0xd8ff; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x17 and fm1 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0xdfcf; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x18 and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x63fc; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x19 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x642d; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1a and fm1 == 0x370 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x6b70; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x1b and fm1 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x6e69; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x7186; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1d and fm1 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xf522; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x7ab3; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0x7bff; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x00 and fm1 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x82be; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x01 and fm1 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x86a5; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x02 and fm1 == 0x088 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x8888; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x03 and fm1 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x8f12; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x04 and fm1 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x93ed; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x05 and fm1 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x97e0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x06 and fm1 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x9a74; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x07 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x9c2d; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 1 and fe1 == 0x08 and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0xa004; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 1 and fe1 == 0x09 and fm1 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0xa489; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x0a and fm1 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0xabc3; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0xad36; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x176 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb176; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 1 and fe1 == 0x0d and fm1 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb797; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb941; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbe32; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xc1be; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xc442; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 1 and fe1 == 0x09 and fm1 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa656; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 1 and fe1 == 0x16 and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xda01; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xad36; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(13751,16,FLEN)
|
||||
NAN_BOXED(14927,16,FLEN)
|
||||
NAN_BOXED(15571,16,FLEN)
|
||||
NAN_BOXED(17216,16,FLEN)
|
||||
NAN_BOXED(18251,16,FLEN)
|
||||
NAN_BOXED(51869,16,FLEN)
|
||||
NAN_BOXED(19620,16,FLEN)
|
||||
NAN_BOXED(21013,16,FLEN)
|
||||
NAN_BOXED(21839,16,FLEN)
|
||||
NAN_BOXED(55551,16,FLEN)
|
||||
NAN_BOXED(57295,16,FLEN)
|
||||
NAN_BOXED(25596,16,FLEN)
|
||||
NAN_BOXED(25645,16,FLEN)
|
||||
NAN_BOXED(27504,16,FLEN)
|
||||
NAN_BOXED(28265,16,FLEN)
|
||||
NAN_BOXED(29062,16,FLEN)
|
||||
NAN_BOXED(62754,16,FLEN)
|
||||
NAN_BOXED(31411,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(33470,16,FLEN)
|
||||
NAN_BOXED(34469,16,FLEN)
|
||||
NAN_BOXED(34952,16,FLEN)
|
||||
NAN_BOXED(36626,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(37869,16,FLEN)
|
||||
NAN_BOXED(38880,16,FLEN)
|
||||
NAN_BOXED(39540,16,FLEN)
|
||||
NAN_BOXED(39981,16,FLEN)
|
||||
NAN_BOXED(40964,16,FLEN)
|
||||
NAN_BOXED(42121,16,FLEN)
|
||||
NAN_BOXED(43971,16,FLEN)
|
||||
NAN_BOXED(44342,16,FLEN)
|
||||
NAN_BOXED(45430,16,FLEN)
|
||||
NAN_BOXED(46999,16,FLEN)
|
||||
NAN_BOXED(47425,16,FLEN)
|
||||
NAN_BOXED(48690,16,FLEN)
|
||||
NAN_BOXED(49598,16,FLEN)
|
||||
NAN_BOXED(50242,16,FLEN)
|
||||
NAN_BOXED(42582,16,FLEN)
|
||||
NAN_BOXED(55809,16,FLEN)
|
||||
NAN_BOXED(44342,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 28*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,418 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b23 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b23)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x7800; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x7800; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x7800; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x7800; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x7800; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_41:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_42:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_43:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_45:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 38*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,838 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b24 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b24)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x2e66; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x2e66; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x2e66; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x2e66; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x2e66; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0xf0; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0xf0; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0xf0; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0xf0; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0xf0; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0xbb1e; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0xbb1e; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xbb1e; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0xbb1e; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0xbb1e; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x2f0a; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x2f0a; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x2f0a; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x2f0a; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x2f0a; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_41:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_42:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_43:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_44:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_45:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_46:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_47:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_48:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_49:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_50:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_51:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_52:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_53:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_54:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_55:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
|
||||
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_56:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
|
||||
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_57:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
|
||||
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_58:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
|
||||
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_59:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
|
||||
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_60:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_61:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_62:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_63:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_64:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_65:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_66:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_67:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_68:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_69:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_70:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
|
||||
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_71:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
|
||||
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_72:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
|
||||
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_73:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
|
||||
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_74:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
|
||||
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_75:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_76:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_77:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_78:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_79:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_80:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_81:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 57*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_82:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 58*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_83:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 59*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_84:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 60*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_85:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 61*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_86:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 62*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_87:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 63*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_88:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 64*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_89:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 65*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_90:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
|
||||
val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 66*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_91:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
|
||||
val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 67*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_92:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
|
||||
val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 68*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_93:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
|
||||
val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 69*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_94:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
|
||||
val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 70*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_95:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 71*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_96:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 72*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_97:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 73*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_98:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 74*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_99:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:75*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 75*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_100:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:76*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 76*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_101:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:77*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 77*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_102:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:78*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 78*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_103:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:79*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 79*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_104:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:80*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 80*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_105:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:81*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 81*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 158*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b27 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b27)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7c01; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0xfc01; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x7d55; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0xfd55; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x7e01; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0xfe01; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x7e55; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0xfe55; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(31745,16,FLEN)
|
||||
NAN_BOXED(64513,16,FLEN)
|
||||
NAN_BOXED(32085,16,FLEN)
|
||||
NAN_BOXED(64853,16,FLEN)
|
||||
NAN_BOXED(32257,16,FLEN)
|
||||
NAN_BOXED(65025,16,FLEN)
|
||||
NAN_BOXED(32341,16,FLEN)
|
||||
NAN_BOXED(65109,16,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b28 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b28)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x3892; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x3c00; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x3d00; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x3e00; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x3f00; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x4000; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x4080; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x4100; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x4180; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x72dc; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x7c00; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x7c01; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x7e01; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x8000; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0xb6c0; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xbc00; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0xc180; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0xc100; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0xc080; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0xc000; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0xbf00; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0xbe00; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0xbd00; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0xf659; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0xf800; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0xfc00; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(14482,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15616,16,FLEN)
|
||||
NAN_BOXED(15872,16,FLEN)
|
||||
NAN_BOXED(16128,16,FLEN)
|
||||
NAN_BOXED(16384,16,FLEN)
|
||||
NAN_BOXED(16512,16,FLEN)
|
||||
NAN_BOXED(16640,16,FLEN)
|
||||
NAN_BOXED(16768,16,FLEN)
|
||||
NAN_BOXED(29404,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(31744,16,FLEN)
|
||||
NAN_BOXED(31745,16,FLEN)
|
||||
NAN_BOXED(32257,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(46784,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(49536,16,FLEN)
|
||||
NAN_BOXED(49408,16,FLEN)
|
||||
NAN_BOXED(49280,16,FLEN)
|
||||
NAN_BOXED(49152,16,FLEN)
|
||||
NAN_BOXED(48896,16,FLEN)
|
||||
NAN_BOXED(48640,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(48384,16,FLEN)
|
||||
NAN_BOXED(63065,16,FLEN)
|
||||
NAN_BOXED(63488,16,FLEN)
|
||||
NAN_BOXED(64512,16,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,663 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:30 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b29 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b29)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3248; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x3248; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x3248; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x3248; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x3248; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x324a; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x324a; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x324a; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x324a; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x324a; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x324b; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x324b; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0x324b; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x324b; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0x324b; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x324c; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x324c; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x324c; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x324c; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x324c; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x324d; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x324d; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x324d; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x324d; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x324d; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x324e; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x324e; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_41:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_42:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_43:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_44:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_45:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_46:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_47:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_48:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
|
||||
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_49:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
|
||||
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_50:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
|
||||
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_51:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
|
||||
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_52:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
|
||||
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_53:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
|
||||
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_54:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
|
||||
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_55:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
|
||||
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_56:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
|
||||
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_57:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
|
||||
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_58:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
|
||||
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_59:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
|
||||
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_60:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
|
||||
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_61:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
|
||||
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_62:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
|
||||
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_63:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
|
||||
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_64:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
|
||||
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_65:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
|
||||
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_66:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
|
||||
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_67:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
|
||||
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_68:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
|
||||
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_69:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
|
||||
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_70:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
|
||||
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_71:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
|
||||
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_72:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
|
||||
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_73:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
|
||||
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_74:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
|
||||
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_75:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
|
||||
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_76:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
|
||||
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_77:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
|
||||
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_78:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
|
||||
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_79:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
|
||||
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_80:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
|
||||
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(12872,16,FLEN)
|
||||
NAN_BOXED(12872,16,FLEN)
|
||||
NAN_BOXED(12872,16,FLEN)
|
||||
NAN_BOXED(12872,16,FLEN)
|
||||
NAN_BOXED(12872,16,FLEN)
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(12874,16,FLEN)
|
||||
NAN_BOXED(12874,16,FLEN)
|
||||
NAN_BOXED(12874,16,FLEN)
|
||||
NAN_BOXED(12874,16,FLEN)
|
||||
NAN_BOXED(12874,16,FLEN)
|
||||
NAN_BOXED(12875,16,FLEN)
|
||||
NAN_BOXED(12875,16,FLEN)
|
||||
NAN_BOXED(12875,16,FLEN)
|
||||
NAN_BOXED(12875,16,FLEN)
|
||||
NAN_BOXED(12875,16,FLEN)
|
||||
NAN_BOXED(12876,16,FLEN)
|
||||
NAN_BOXED(12876,16,FLEN)
|
||||
NAN_BOXED(12876,16,FLEN)
|
||||
NAN_BOXED(12876,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(12876,16,FLEN)
|
||||
NAN_BOXED(12877,16,FLEN)
|
||||
NAN_BOXED(12877,16,FLEN)
|
||||
NAN_BOXED(12877,16,FLEN)
|
||||
NAN_BOXED(12877,16,FLEN)
|
||||
NAN_BOXED(12877,16,FLEN)
|
||||
NAN_BOXED(12878,16,FLEN)
|
||||
NAN_BOXED(12878,16,FLEN)
|
||||
NAN_BOXED(12878,16,FLEN)
|
||||
NAN_BOXED(12878,16,FLEN)
|
||||
NAN_BOXED(12878,16,FLEN)
|
||||
NAN_BOXED(12879,16,FLEN)
|
||||
NAN_BOXED(12879,16,FLEN)
|
||||
NAN_BOXED(12879,16,FLEN)
|
||||
NAN_BOXED(12879,16,FLEN)
|
||||
NAN_BOXED(12879,16,FLEN)
|
||||
NAN_BOXED(45640,16,FLEN)
|
||||
NAN_BOXED(45640,16,FLEN)
|
||||
NAN_BOXED(45640,16,FLEN)
|
||||
NAN_BOXED(45640,16,FLEN)
|
||||
NAN_BOXED(45640,16,FLEN)
|
||||
NAN_BOXED(45641,16,FLEN)
|
||||
NAN_BOXED(45641,16,FLEN)
|
||||
NAN_BOXED(45641,16,FLEN)
|
||||
NAN_BOXED(45641,16,FLEN)
|
||||
NAN_BOXED(45641,16,FLEN)
|
||||
NAN_BOXED(45642,16,FLEN)
|
||||
NAN_BOXED(45642,16,FLEN)
|
||||
NAN_BOXED(45642,16,FLEN)
|
||||
NAN_BOXED(45642,16,FLEN)
|
||||
NAN_BOXED(45642,16,FLEN)
|
||||
NAN_BOXED(45643,16,FLEN)
|
||||
NAN_BOXED(45643,16,FLEN)
|
||||
NAN_BOXED(45643,16,FLEN)
|
||||
NAN_BOXED(45643,16,FLEN)
|
||||
NAN_BOXED(45643,16,FLEN)
|
||||
NAN_BOXED(45644,16,FLEN)
|
||||
NAN_BOXED(45644,16,FLEN)
|
||||
NAN_BOXED(45644,16,FLEN)
|
||||
NAN_BOXED(45644,16,FLEN)
|
||||
NAN_BOXED(45644,16,FLEN)
|
||||
NAN_BOXED(45645,16,FLEN)
|
||||
NAN_BOXED(45645,16,FLEN)
|
||||
NAN_BOXED(45645,16,FLEN)
|
||||
NAN_BOXED(45645,16,FLEN)
|
||||
NAN_BOXED(45645,16,FLEN)
|
||||
NAN_BOXED(45646,16,FLEN)
|
||||
NAN_BOXED(45646,16,FLEN)
|
||||
NAN_BOXED(45646,16,FLEN)
|
||||
NAN_BOXED(45646,16,FLEN)
|
||||
NAN_BOXED(45646,16,FLEN)
|
||||
NAN_BOXED(45647,16,FLEN)
|
||||
NAN_BOXED(45647,16,FLEN)
|
||||
NAN_BOXED(45647,16,FLEN)
|
||||
NAN_BOXED(45647,16,FLEN)
|
||||
NAN_BOXED(45647,16,FLEN)
|
||||
NAN_BOXED(12878,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 108*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:49 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b1 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b1)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0x8000; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0x8001; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0x83fe; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0x3ff; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0x83ff; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x400; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x8400; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0x401; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0x8455; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0x7bff; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0xfbff; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0x7c00; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0xfc00; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0x7e00; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0xfe00; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0x7e01; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0xfe55; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0x7c01; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0xfd55; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0x3c00; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0xbc00; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(1,16,FLEN)
|
||||
NAN_BOXED(32769,16,FLEN)
|
||||
NAN_BOXED(2,16,FLEN)
|
||||
NAN_BOXED(33790,16,FLEN)
|
||||
NAN_BOXED(1023,16,FLEN)
|
||||
NAN_BOXED(33791,16,FLEN)
|
||||
NAN_BOXED(1024,16,FLEN)
|
||||
NAN_BOXED(33792,16,FLEN)
|
||||
NAN_BOXED(1025,16,FLEN)
|
||||
NAN_BOXED(33877,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(31744,16,FLEN)
|
||||
NAN_BOXED(64512,16,FLEN)
|
||||
NAN_BOXED(32256,16,FLEN)
|
||||
NAN_BOXED(65024,16,FLEN)
|
||||
NAN_BOXED(32257,16,FLEN)
|
||||
NAN_BOXED(65109,16,FLEN)
|
||||
NAN_BOXED(31745,16,FLEN)
|
||||
NAN_BOXED(64853,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,383 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:49 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b22 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b22)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0x35b7; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x3a4f; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0x3cd3; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x4340; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0x474b; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x12 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0xca9d; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x13 and fm1 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0x4ca4; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x5215; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x15 and fm1 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x554f; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 1 and fe1 == 0x16 and fm1 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0xd8ff; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x17 and fm1 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0xdfcf; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x18 and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0x63fc; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x19 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0x642d; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1a and fm1 == 0x370 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0x6b70; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x1b and fm1 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0x6e69; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0x7186; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1d and fm1 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0xf522; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0x7ab3; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0x7bff; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x00 and fm1 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0x82be; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x01 and fm1 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0x86a5; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x02 and fm1 == 0x088 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0x8888; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x03 and fm1 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0x8f12; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x04 and fm1 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0x93ed; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x05 and fm1 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0x97e0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x06 and fm1 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0x9a74; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x07 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0x9c2d; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 1 and fe1 == 0x08 and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0xa004; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 1 and fe1 == 0x09 and fm1 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0xa489; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x0a and fm1 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0xabc3; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0xad36; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x176 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb176; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 1 and fe1 == 0x0d and fm1 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb797; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb941; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbe32; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xc1be; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xc442; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 1 and fe1 == 0x09 and fm1 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xa656; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 1 and fe1 == 0x16 and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xda01; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xad36; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(13751,16,FLEN)
|
||||
NAN_BOXED(14927,16,FLEN)
|
||||
NAN_BOXED(15571,16,FLEN)
|
||||
NAN_BOXED(17216,16,FLEN)
|
||||
NAN_BOXED(18251,16,FLEN)
|
||||
NAN_BOXED(51869,16,FLEN)
|
||||
NAN_BOXED(19620,16,FLEN)
|
||||
NAN_BOXED(21013,16,FLEN)
|
||||
NAN_BOXED(21839,16,FLEN)
|
||||
NAN_BOXED(55551,16,FLEN)
|
||||
NAN_BOXED(57295,16,FLEN)
|
||||
NAN_BOXED(25596,16,FLEN)
|
||||
NAN_BOXED(25645,16,FLEN)
|
||||
NAN_BOXED(27504,16,FLEN)
|
||||
NAN_BOXED(28265,16,FLEN)
|
||||
NAN_BOXED(29062,16,FLEN)
|
||||
NAN_BOXED(62754,16,FLEN)
|
||||
NAN_BOXED(31411,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(33470,16,FLEN)
|
||||
NAN_BOXED(34469,16,FLEN)
|
||||
NAN_BOXED(34952,16,FLEN)
|
||||
NAN_BOXED(36626,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(37869,16,FLEN)
|
||||
NAN_BOXED(38880,16,FLEN)
|
||||
NAN_BOXED(39540,16,FLEN)
|
||||
NAN_BOXED(39981,16,FLEN)
|
||||
NAN_BOXED(40964,16,FLEN)
|
||||
NAN_BOXED(42121,16,FLEN)
|
||||
NAN_BOXED(43971,16,FLEN)
|
||||
NAN_BOXED(44342,16,FLEN)
|
||||
NAN_BOXED(45430,16,FLEN)
|
||||
NAN_BOXED(46999,16,FLEN)
|
||||
NAN_BOXED(47425,16,FLEN)
|
||||
NAN_BOXED(48690,16,FLEN)
|
||||
NAN_BOXED(49598,16,FLEN)
|
||||
NAN_BOXED(50242,16,FLEN)
|
||||
NAN_BOXED(42582,16,FLEN)
|
||||
NAN_BOXED(55809,16,FLEN)
|
||||
NAN_BOXED(44342,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 28*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,418 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:49 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b23 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b23)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x77fc; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x77fd; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0x77fe; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0x7800; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0x7800; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0x7800; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0x7800; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0x7800; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0x7801; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_41:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_42:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_43:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_45:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30716,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30717,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30718,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(30720,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30721,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30723,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30724,16,FLEN)
|
||||
NAN_BOXED(30722,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 38*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,838 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:49 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b24 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b24)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0x3c0a; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x3c0a; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0x3c0a; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x3c0a; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x211e; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0xbc70; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0xbc70; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0xbc70; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0xbc70; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0xbc70; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0xa11e; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0xa11e; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0xa11e; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0xa11e; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0xa11e; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0x3c00; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0x3c00; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0x3c00; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0x3c00; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0x3c00; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0xbbeb; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xf0; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_41:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xf0; valaddr_reg:x8;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_42:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xf0; valaddr_reg:x8;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_43:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xf0; valaddr_reg:x8;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_44:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xf0; valaddr_reg:x8;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_45:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_46:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_47:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_48:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_49:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
|
||||
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_50:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_51:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_52:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_53:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_54:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xaf0a; valaddr_reg:x8;
|
||||
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_55:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_56:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_57:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_58:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_59:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
|
||||
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_60:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2e66; valaddr_reg:x8;
|
||||
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_61:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2e66; valaddr_reg:x8;
|
||||
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_62:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2e66; valaddr_reg:x8;
|
||||
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_63:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2e66; valaddr_reg:x8;
|
||||
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_64:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2e66; valaddr_reg:x8;
|
||||
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_65:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2f0a; valaddr_reg:x8;
|
||||
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_66:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2f0a; valaddr_reg:x8;
|
||||
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_67:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2f0a; valaddr_reg:x8;
|
||||
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_68:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2f0a; valaddr_reg:x8;
|
||||
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_69:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2f0a; valaddr_reg:x8;
|
||||
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_70:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_71:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_72:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_73:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_74:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
|
||||
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_75:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_76:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_77:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_78:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_79:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
|
||||
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_80:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_81:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 57*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_82:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 58*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_83:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 59*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_84:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
|
||||
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 60*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_85:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 61*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_86:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 62*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_87:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 63*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_88:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 64*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_89:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
|
||||
val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 65*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_90:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 66*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_91:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 67*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_92:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 68*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_93:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 69*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_94:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
|
||||
val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 70*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_95:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 71*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_96:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 72*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_97:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 73*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_98:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 74*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_99:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
|
||||
val_offset:75*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 75*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_100:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb1e; valaddr_reg:x8;
|
||||
val_offset:76*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 76*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_101:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb1e; valaddr_reg:x8;
|
||||
val_offset:77*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 77*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_102:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb1e; valaddr_reg:x8;
|
||||
val_offset:78*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 78*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_103:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb1e; valaddr_reg:x8;
|
||||
val_offset:79*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 79*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_104:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb1e; valaddr_reg:x8;
|
||||
val_offset:80*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 80*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_105:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
|
||||
val_offset:81*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 81*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(15370,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(8478,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(48240,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(41246,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48107,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(48230,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(240,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(15155,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(44810,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(15339,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(11878,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(12042,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(15134,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(44646,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(15462,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(47923,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(48138,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(15472,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(47902,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 158*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:49 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b27 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b27)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7c01; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0xfc01; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x7d55; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0xfd55; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x7e01; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0xfe01; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0x7e55; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0xfe55; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,
|
||||
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,
|
||||
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,
|
||||
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,
|
||||
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,
|
||||
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,
|
||||
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,
|
||||
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,
|
||||
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,
|
||||
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,
|
||||
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,
|
||||
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,
|
||||
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,
|
||||
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,
|
||||
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,
|
||||
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,
|
||||
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,
|
||||
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,
|
||||
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,
|
||||
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,
|
||||
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(31745,16,FLEN)
|
||||
NAN_BOXED(64513,16,FLEN)
|
||||
NAN_BOXED(32085,16,FLEN)
|
||||
NAN_BOXED(64853,16,FLEN)
|
||||
NAN_BOXED(32257,16,FLEN)
|
||||
NAN_BOXED(65025,16,FLEN)
|
||||
NAN_BOXED(32341,16,FLEN)
|
||||
NAN_BOXED(65109,16,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:49 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b28 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b28)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0x3892; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x3c00; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0x3d00; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x3e00; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0x3f00; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0x4000; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0x4080; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x4100; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x4180; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0x72dc; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0x77ff; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0x7c00; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0x7c01; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0x7e01; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0x8000; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0xb6c0; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0xbc00; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0xc180; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0xc100; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0xc080; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0xc000; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0xbf00; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0xbe00; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0xbd00; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0xf659; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0xf800; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0xfc00; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,
|
||||
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,
|
||||
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,
|
||||
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,
|
||||
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(14482,16,FLEN)
|
||||
NAN_BOXED(15360,16,FLEN)
|
||||
NAN_BOXED(15616,16,FLEN)
|
||||
NAN_BOXED(15872,16,FLEN)
|
||||
NAN_BOXED(16128,16,FLEN)
|
||||
NAN_BOXED(16384,16,FLEN)
|
||||
NAN_BOXED(16512,16,FLEN)
|
||||
NAN_BOXED(16640,16,FLEN)
|
||||
NAN_BOXED(16768,16,FLEN)
|
||||
NAN_BOXED(29404,16,FLEN)
|
||||
NAN_BOXED(30719,16,FLEN)
|
||||
NAN_BOXED(31744,16,FLEN)
|
||||
NAN_BOXED(31745,16,FLEN)
|
||||
NAN_BOXED(32257,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(46784,16,FLEN)
|
||||
NAN_BOXED(48128,16,FLEN)
|
||||
NAN_BOXED(49536,16,FLEN)
|
||||
NAN_BOXED(49408,16,FLEN)
|
||||
NAN_BOXED(49280,16,FLEN)
|
||||
NAN_BOXED(49152,16,FLEN)
|
||||
NAN_BOXED(48896,16,FLEN)
|
||||
NAN_BOXED(48640,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(48384,16,FLEN)
|
||||
NAN_BOXED(63065,16,FLEN)
|
||||
NAN_BOXED(63488,16,FLEN)
|
||||
NAN_BOXED(64512,16,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,663 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:40:49 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b29 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b29)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3248; valaddr_reg:x3;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0x3248; valaddr_reg:x3;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x3248; valaddr_reg:x3;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0x3248; valaddr_reg:x3;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x3248; valaddr_reg:x3;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x3249; valaddr_reg:x3;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0x324a; valaddr_reg:x3;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0x324a; valaddr_reg:x3;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0x324a; valaddr_reg:x3;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0x324a; valaddr_reg:x3;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0x324a; valaddr_reg:x3;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0x324b; valaddr_reg:x3;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0x324b; valaddr_reg:x3;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0x324b; valaddr_reg:x3;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0x324b; valaddr_reg:x3;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0x324b; valaddr_reg:x3;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0x324c; valaddr_reg:x3;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0x324c; valaddr_reg:x3;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0x324c; valaddr_reg:x3;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
|
||||
|
||||
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0x324c; valaddr_reg:x3;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0x324c; valaddr_reg:x8;
|
||||
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0x324d; valaddr_reg:x8;
|
||||
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
|
||||
|
||||
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0x324d; valaddr_reg:x8;
|
||||
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0x324d; valaddr_reg:x8;
|
||||
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0x324d; valaddr_reg:x8;
|
||||
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0x324d; valaddr_reg:x8;
|
||||
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0x324e; valaddr_reg:x8;
|
||||
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0x324e; valaddr_reg:x8;
|
||||
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_32:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
|
||||
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_33:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
|
||||
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_34:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
|
||||
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_35:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
|
||||
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_36:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
|
||||
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_37:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
|
||||
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_38:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
|
||||
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_39:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
|
||||
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_40:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
|
||||
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_41:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
|
||||
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_42:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
|
||||
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_43:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
|
||||
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_44:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
|
||||
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_45:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
|
||||
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_46:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
|
||||
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_47:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
|
||||
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_48:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
|
||||
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_49:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
|
||||
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_50:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
|
||||
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_51:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
|
||||
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_52:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
|
||||
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_53:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
|
||||
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_54:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
|
||||
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_55:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
|
||||
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_56:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
|
||||
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_57:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
|
||||
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_58:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
|
||||
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_59:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
|
||||
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_60:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
|
||||
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_61:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
|
||||
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_62:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
|
||||
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_63:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
|
||||
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_64:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
|
||||
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_65:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
|
||||
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_66:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
|
||||
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_67:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
|
||||
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_68:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
|
||||
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_69:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
|
||||
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_70:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
|
||||
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_71:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
|
||||
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_72:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
|
||||
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_73:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
|
||||
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_74:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
|
||||
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_75:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
|
||||
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:0*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_76:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
|
||||
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_77:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
|
||||
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:64*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_78:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
|
||||
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:96*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_79:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
|
||||
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:128*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
|
||||
|
||||
inst_80:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
|
||||
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
|
||||
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
|
||||
fcsr_val:32*/
|
||||
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(12872,16,FLEN)
|
||||
NAN_BOXED(12872,16,FLEN)
|
||||
NAN_BOXED(12872,16,FLEN)
|
||||
NAN_BOXED(12872,16,FLEN)
|
||||
NAN_BOXED(12872,16,FLEN)
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(12873,16,FLEN)
|
||||
NAN_BOXED(12874,16,FLEN)
|
||||
NAN_BOXED(12874,16,FLEN)
|
||||
NAN_BOXED(12874,16,FLEN)
|
||||
NAN_BOXED(12874,16,FLEN)
|
||||
NAN_BOXED(12874,16,FLEN)
|
||||
NAN_BOXED(12875,16,FLEN)
|
||||
NAN_BOXED(12875,16,FLEN)
|
||||
NAN_BOXED(12875,16,FLEN)
|
||||
NAN_BOXED(12875,16,FLEN)
|
||||
NAN_BOXED(12875,16,FLEN)
|
||||
NAN_BOXED(12876,16,FLEN)
|
||||
NAN_BOXED(12876,16,FLEN)
|
||||
NAN_BOXED(12876,16,FLEN)
|
||||
NAN_BOXED(12876,16,FLEN)
|
||||
test_dataset_1:
|
||||
NAN_BOXED(12876,16,FLEN)
|
||||
NAN_BOXED(12877,16,FLEN)
|
||||
NAN_BOXED(12877,16,FLEN)
|
||||
NAN_BOXED(12877,16,FLEN)
|
||||
NAN_BOXED(12877,16,FLEN)
|
||||
NAN_BOXED(12877,16,FLEN)
|
||||
NAN_BOXED(12878,16,FLEN)
|
||||
NAN_BOXED(12878,16,FLEN)
|
||||
NAN_BOXED(12878,16,FLEN)
|
||||
NAN_BOXED(12878,16,FLEN)
|
||||
NAN_BOXED(12878,16,FLEN)
|
||||
NAN_BOXED(12879,16,FLEN)
|
||||
NAN_BOXED(12879,16,FLEN)
|
||||
NAN_BOXED(12879,16,FLEN)
|
||||
NAN_BOXED(12879,16,FLEN)
|
||||
NAN_BOXED(12879,16,FLEN)
|
||||
NAN_BOXED(45640,16,FLEN)
|
||||
NAN_BOXED(45640,16,FLEN)
|
||||
NAN_BOXED(45640,16,FLEN)
|
||||
NAN_BOXED(45640,16,FLEN)
|
||||
NAN_BOXED(45640,16,FLEN)
|
||||
NAN_BOXED(45641,16,FLEN)
|
||||
NAN_BOXED(45641,16,FLEN)
|
||||
NAN_BOXED(45641,16,FLEN)
|
||||
NAN_BOXED(45641,16,FLEN)
|
||||
NAN_BOXED(45641,16,FLEN)
|
||||
NAN_BOXED(45642,16,FLEN)
|
||||
NAN_BOXED(45642,16,FLEN)
|
||||
NAN_BOXED(45642,16,FLEN)
|
||||
NAN_BOXED(45642,16,FLEN)
|
||||
NAN_BOXED(45642,16,FLEN)
|
||||
NAN_BOXED(45643,16,FLEN)
|
||||
NAN_BOXED(45643,16,FLEN)
|
||||
NAN_BOXED(45643,16,FLEN)
|
||||
NAN_BOXED(45643,16,FLEN)
|
||||
NAN_BOXED(45643,16,FLEN)
|
||||
NAN_BOXED(45644,16,FLEN)
|
||||
NAN_BOXED(45644,16,FLEN)
|
||||
NAN_BOXED(45644,16,FLEN)
|
||||
NAN_BOXED(45644,16,FLEN)
|
||||
NAN_BOXED(45644,16,FLEN)
|
||||
NAN_BOXED(45645,16,FLEN)
|
||||
NAN_BOXED(45645,16,FLEN)
|
||||
NAN_BOXED(45645,16,FLEN)
|
||||
NAN_BOXED(45645,16,FLEN)
|
||||
NAN_BOXED(45645,16,FLEN)
|
||||
NAN_BOXED(45646,16,FLEN)
|
||||
NAN_BOXED(45646,16,FLEN)
|
||||
NAN_BOXED(45646,16,FLEN)
|
||||
NAN_BOXED(45646,16,FLEN)
|
||||
NAN_BOXED(45646,16,FLEN)
|
||||
NAN_BOXED(45647,16,FLEN)
|
||||
NAN_BOXED(45647,16,FLEN)
|
||||
NAN_BOXED(45647,16,FLEN)
|
||||
NAN_BOXED(45647,16,FLEN)
|
||||
NAN_BOXED(45647,16,FLEN)
|
||||
NAN_BOXED(12878,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 108*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,479 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Sat May 6 11:18:48 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fdiv.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fdiv.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fdiv_b20 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b20)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:
|
||||
// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x24a and fs2 == 1 and fe2 == 0x0a and fm2 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f31; dest:f31; op1val:0x764a; op2val:0xaa4a;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:
|
||||
// rs1 == rs2 == rd, rs1==f29, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f29; op2:f29; dest:f29; op1val:0x7ad2; op2val:0x7ad2;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f29, f29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:
|
||||
// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f28; op2:f30; dest:f28; op1val:0x77ae; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f28, f28, f30, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:
|
||||
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f31, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f31; op2:f28; dest:f30; op1val:0x79f2; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f30, f31, f28, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:
|
||||
// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f26; op2:f26; dest:f27; op1val:0x7677; op2val:0x7677;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f27, f26, f26, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:
|
||||
// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x150 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f27; op2:f25; dest:f26; op1val:0x7950; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f26, f27, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:
|
||||
// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f24; op2:f27; dest:f25; op1val:0x75df; op2val:0x8000;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f25, f24, f27, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:
|
||||
// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f25; op2:f23; dest:f24; op1val:0x7b0e; op2val:0xfbff;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f24, f25, f23, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:
|
||||
// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f22; op2:f24; dest:f23; op1val:0x7a34; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f23, f22, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:
|
||||
// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f23; op2:f21; dest:f22; op1val:0x79e7; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f22, f23, f21, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:
|
||||
// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x1b and fm1 == 0x188 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f20; op2:f22; dest:f21; op1val:0x6d88; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:
|
||||
// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x14e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f21; op2:f19; dest:f20; op1val:0x794e; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f20, f21, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:
|
||||
// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f18; op2:f20; dest:f19; op1val:0x6ee7; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f19, f18, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:
|
||||
// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x1c and fm1 == 0x13c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f19; op2:f17; dest:f18; op1val:0x713c; op2val:0xfbff;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f18, f19, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:
|
||||
// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f16; op2:f18; dest:f17; op1val:0x7ab7; op2val:0xfbff;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f17, f16, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:
|
||||
// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f17; op2:f15; dest:f16; op1val:0x75ec; op2val:0xfbff;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f16, f17, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:
|
||||
// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f14; op2:f16; dest:f15; op1val:0x79db; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f15, f14, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:
|
||||
// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x381 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f15; op2:f13; dest:f14; op1val:0x7781; op2val:0xfbff;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f14, f15, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:
|
||||
// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f12; op2:f14; dest:f13; op1val:0x74ef; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f13, f12, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:
|
||||
// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f13; op2:f11; dest:f12; op1val:0x7ac8; op2val:0xf7c0;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f12, f13, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:
|
||||
// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f10; op2:f12; dest:f11; op1val:0x78ea; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f11, f10, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:
|
||||
// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x09f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f11; op2:f9; dest:f10; op1val:0x789f; op2val:0xfbff;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f10, f11, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:
|
||||
// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f8; op2:f10; dest:f9; op1val:0x792c; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f9, f8, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:
|
||||
// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f9; op2:f7; dest:f8; op1val:0x7164; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f8, f9, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:
|
||||
// rs1==f6, rs2==f8, rd==f7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f6; op2:f8; dest:f7; op1val:0x7342; op2val:0x8000;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f7, f6, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:
|
||||
// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0x18 and fm1 == 0x24d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f7; op2:f5; dest:f6; op1val:0x624d; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f6, f7, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:
|
||||
// rs1==f4, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0x1c and fm1 == 0x261 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f4; op2:f6; dest:f5; op1val:0x7261; op2val:0x8008;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f5, f4, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:
|
||||
// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x35b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f5; op2:f3; dest:f4; op1val:0x7b5b; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f4, f5, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:
|
||||
// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f2; op2:f4; dest:f3; op1val:0x7862; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f3, f2, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:
|
||||
// rs1==f3, rs2==f1, rd==f2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f3; op2:f1; dest:f2; op1val:0x7677; op2val:0x8000;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f2, f3, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:
|
||||
// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x17f and fs2 == 1 and fe2 == 0x16 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f0; op2:f2; dest:f1; op1val:0x757f; op2val:0xda66;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f1, f0, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:
|
||||
// rs1==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f1; op2:f30; dest:f31; op1val:0x7ac6; op2val:0xfbff;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f1, f30, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:
|
||||
// rs2==f0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f0; dest:f31; op1val:0x75a6; op2val:0x8000;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f0, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:
|
||||
// rd==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f31; op2:f30; dest:f0; op1val:0x7b46; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f0, f31, f30, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_34:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7945; op2val:0x8000;
|
||||
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_35:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0de and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x78de; op2val:0xfbff;
|
||||
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_36:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x79d5; op2val:0x8000;
|
||||
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_37:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7ad2; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_38:
|
||||
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7677; op2val:0xfbff;
|
||||
valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(30282,16,FLEN)
|
||||
NAN_BOXED(43594,16,FLEN)
|
||||
NAN_BOXED(31442,16,FLEN)
|
||||
NAN_BOXED(31442,16,FLEN)
|
||||
NAN_BOXED(30638,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31218,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30327,16,FLEN)
|
||||
NAN_BOXED(30327,16,FLEN)
|
||||
NAN_BOXED(31056,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30175,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(31502,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(31284,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(31207,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(28040,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(31054,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(28391,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(28988,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(31415,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(30188,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(31195,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(30593,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(29935,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(31432,16,FLEN)
|
||||
NAN_BOXED(63424,16,FLEN)
|
||||
NAN_BOXED(30954,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30879,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(31020,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(29028,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(29506,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(25165,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(29281,16,FLEN)
|
||||
NAN_BOXED(32776,16,FLEN)
|
||||
NAN_BOXED(31579,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(30818,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(30327,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(30079,16,FLEN)
|
||||
NAN_BOXED(55910,16,FLEN)
|
||||
NAN_BOXED(31430,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(30118,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(31558,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31045,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(30942,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
NAN_BOXED(31189,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(31442,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(30327,16,FLEN)
|
||||
NAN_BOXED(64511,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 78*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,449 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Sat May 6 11:18:48 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fdiv.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fdiv.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fdiv_b6 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b6)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:
|
||||
// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f31; dest:f31; op1val:0x0; op2val:0x8000;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:
|
||||
// rs1 == rs2 == rd, rs1==f29, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f29; op2:f29; dest:f29; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f29, f29, f29, dyn, 32, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:
|
||||
// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f28; op2:f30; dest:f28; op1val:0x0; op2val:0x8000;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f28, f28, f30, dyn, 64, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:
|
||||
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f31, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f31; op2:f28; dest:f30; op1val:0x0; op2val:0x8000;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f30, f31, f28, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:
|
||||
// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f26; op2:f26; dest:f27; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f27, f26, f26, dyn, 128, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:
|
||||
// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f27; op2:f25; dest:f26; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f26, f27, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:
|
||||
// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f24; op2:f27; dest:f25; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f25, f24, f27, dyn, 32, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:
|
||||
// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f24, f25, f23, dyn, 64, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:
|
||||
// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f23, f22, f24, dyn, 96, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:
|
||||
// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f22, f23, f21, dyn, 128, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:
|
||||
// rs1==f20, rs2==f22, rd==f21,
|
||||
/* opcode: fdiv.h ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:
|
||||
// rs1==f21, rs2==f19, rd==f20,
|
||||
/* opcode: fdiv.h ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f20, f21, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:
|
||||
// rs1==f18, rs2==f20, rd==f19,
|
||||
/* opcode: fdiv.h ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f19, f18, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:
|
||||
// rs1==f19, rs2==f17, rd==f18,
|
||||
/* opcode: fdiv.h ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f18, f19, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:
|
||||
// rs1==f16, rs2==f18, rd==f17,
|
||||
/* opcode: fdiv.h ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f17, f16, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:
|
||||
// rs1==f17, rs2==f15, rd==f16,
|
||||
/* opcode: fdiv.h ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f16, f17, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:
|
||||
// rs1==f14, rs2==f16, rd==f15,
|
||||
/* opcode: fdiv.h ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f15, f14, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:
|
||||
// rs1==f15, rs2==f13, rd==f14,
|
||||
/* opcode: fdiv.h ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f14, f15, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:
|
||||
// rs1==f12, rs2==f14, rd==f13,
|
||||
/* opcode: fdiv.h ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f13, f12, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:
|
||||
// rs1==f13, rs2==f11, rd==f12,
|
||||
/* opcode: fdiv.h ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f12, f13, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:
|
||||
// rs1==f10, rs2==f12, rd==f11,
|
||||
/* opcode: fdiv.h ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f11, f10, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:
|
||||
// rs1==f11, rs2==f9, rd==f10,
|
||||
/* opcode: fdiv.h ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f10, f11, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:
|
||||
// rs1==f8, rs2==f10, rd==f9,
|
||||
/* opcode: fdiv.h ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f9, f8, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:
|
||||
// rs1==f9, rs2==f7, rd==f8,
|
||||
/* opcode: fdiv.h ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f8, f9, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:
|
||||
// rs1==f6, rs2==f8, rd==f7,
|
||||
/* opcode: fdiv.h ; op1:f6; op2:f8; dest:f7; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f7, f6, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:
|
||||
// rs1==f7, rs2==f5, rd==f6,
|
||||
/* opcode: fdiv.h ; op1:f7; op2:f5; dest:f6; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f6, f7, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:
|
||||
// rs1==f4, rs2==f6, rd==f5,
|
||||
/* opcode: fdiv.h ; op1:f4; op2:f6; dest:f5; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f5, f4, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:
|
||||
// rs1==f5, rs2==f3, rd==f4,
|
||||
/* opcode: fdiv.h ; op1:f5; op2:f3; dest:f4; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f4, f5, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:
|
||||
// rs1==f2, rs2==f4, rd==f3,
|
||||
/* opcode: fdiv.h ; op1:f2; op2:f4; dest:f3; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f3, f2, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:
|
||||
// rs1==f3, rs2==f1, rd==f2,
|
||||
/* opcode: fdiv.h ; op1:f3; op2:f1; dest:f2; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f2, f3, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:
|
||||
// rs1==f0, rs2==f2, rd==f1,
|
||||
/* opcode: fdiv.h ; op1:f0; op2:f2; dest:f1; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f1, f0, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:
|
||||
// rs1==f1,
|
||||
/* opcode: fdiv.h ; op1:f1; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f1, f30, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:
|
||||
// rs2==f0,
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f0; dest:f31; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f0, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:
|
||||
// rd==f0,
|
||||
/* opcode: fdiv.h ; op1:f31; op2:f30; dest:f0; op1val:0x0; op2val:0x0;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f0, f31, f30, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_34:
|
||||
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x8000;
|
||||
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 32;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 32, 0, x3, 68*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_35:
|
||||
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x8000;
|
||||
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 128;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 128, 0, x3, 70*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
NAN_BOXED(0,16,FLEN)
|
||||
NAN_BOXED(32768,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 72*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
|
|
@ -0,0 +1,649 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Sat May 6 11:18:48 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fdiv.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fdiv.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fdiv_b7 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b7)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:
|
||||
// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f31; dest:f31; op1val:0x739c; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f31, dyn, 96, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:
|
||||
// rs1 == rs2 == rd, rs1==f29, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f29; op2:f29; dest:f29; op1val:0x75ea; op2val:0x75ea;
|
||||
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f29, f29, f29, dyn, 96, 0, x3, 2*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:
|
||||
// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f28; op2:f30; dest:f28; op1val:0x7900; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f28, f28, f30, dyn, 96, 0, x3, 4*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:
|
||||
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f31, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f31; op2:f28; dest:f30; op1val:0x62bf; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f30, f31, f28, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:
|
||||
// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f26; op2:f26; dest:f27; op1val:0x7425; op2val:0x7425;
|
||||
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f27, f26, f26, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:
|
||||
// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f27; op2:f25; dest:f26; op1val:0x7bf6; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f26, f27, f25, dyn, 96, 0, x3, 10*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:
|
||||
// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f24; op2:f27; dest:f25; op1val:0x7ab0; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f25, f24, f27, dyn, 96, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:
|
||||
// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f25; op2:f23; dest:f24; op1val:0x791c; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f24, f25, f23, dyn, 96, 0, x3, 14*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:
|
||||
// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f22; op2:f24; dest:f23; op1val:0x7913; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f23, f22, f24, dyn, 96, 0, x3, 16*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:
|
||||
// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f23; op2:f21; dest:f22; op1val:0x782e; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f22, f23, f21, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:
|
||||
// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f20; op2:f22; dest:f21; op1val:0x795e; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f21, f20, f22, dyn, 96, 0, x3, 20*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:
|
||||
// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f21; op2:f19; dest:f20; op1val:0x7a10; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f20, f21, f19, dyn, 96, 0, x3, 22*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:
|
||||
// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f18; op2:f20; dest:f19; op1val:0x74d1; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f19, f18, f20, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:
|
||||
// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f19; op2:f17; dest:f18; op1val:0x7aeb; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f18, f19, f17, dyn, 96, 0, x3, 26*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:
|
||||
// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f16; op2:f18; dest:f17; op1val:0x79bf; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f17, f16, f18, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:
|
||||
// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f17; op2:f15; dest:f16; op1val:0x79b5; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f16, f17, f15, dyn, 96, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:
|
||||
// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f14; op2:f16; dest:f15; op1val:0x7651; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f15, f14, f16, dyn, 96, 0, x3, 32*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:
|
||||
// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f15; op2:f13; dest:f14; op1val:0x771c; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f14, f15, f13, dyn, 96, 0, x3, 34*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:
|
||||
// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f12; op2:f14; dest:f13; op1val:0x7b07; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f13, f12, f14, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:
|
||||
// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f13; op2:f11; dest:f12; op1val:0x7059; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f12, f13, f11, dyn, 96, 0, x3, 38*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:
|
||||
// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f10; op2:f12; dest:f11; op1val:0x7bb8; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f11, f10, f12, dyn, 96, 0, x3, 40*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:
|
||||
// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f11; op2:f9; dest:f10; op1val:0x7902; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f10, f11, f9, dyn, 96, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:
|
||||
// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f8; op2:f10; dest:f9; op1val:0x780e; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f9, f8, f10, dyn, 96, 0, x3, 44*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:
|
||||
// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f9; op2:f7; dest:f8; op1val:0x759c; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f8, f9, f7, dyn, 96, 0, x3, 46*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:
|
||||
// rs1==f6, rs2==f8, rd==f7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f6; op2:f8; dest:f7; op1val:0x78ab; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f7, f6, f8, dyn, 96, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:
|
||||
// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f7; op2:f5; dest:f6; op1val:0x7974; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f6, f7, f5, dyn, 96, 0, x3, 50*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:
|
||||
// rs1==f4, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f4; op2:f6; dest:f5; op1val:0x7ad9; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f5, f4, f6, dyn, 96, 0, x3, 52*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:
|
||||
// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f5; op2:f3; dest:f4; op1val:0x7ae1; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f4, f5, f3, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:
|
||||
// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f2; op2:f4; dest:f3; op1val:0x7b3b; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f3, f2, f4, dyn, 96, 0, x3, 56*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:
|
||||
// rs1==f3, rs2==f1, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f3; op2:f1; dest:f2; op1val:0x7aa6; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f2, f3, f1, dyn, 96, 0, x3, 58*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:
|
||||
// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f0; op2:f2; dest:f1; op1val:0x748e; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f1, f0, f2, dyn, 96, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:
|
||||
// rs1==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f1; op2:f30; dest:f31; op1val:0x7ad4; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f1, f30, dyn, 96, 0, x3, 62*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:
|
||||
// rs2==f0,fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f0; dest:f31; op1val:0x6da9; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f0, dyn, 96, 0, x3, 64*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:
|
||||
// rd==f0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f31; op2:f30; dest:f0; op1val:0x7690; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f0, f31, f30, dyn, 96, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_34:
|
||||
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x74b3; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 68*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_35:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7afa; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 70*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_36:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x78e9; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 72*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_37:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x79be; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 74*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_38:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b0b; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 76*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_39:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x780a; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 78*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_40:
|
||||
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x0f3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x74f3; op2val:0x5cf3;
|
||||
valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 80*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_41:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0cb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x78cb; op2val:0x60cb;
|
||||
valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 82*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_42:
|
||||
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x250 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7250; op2val:0x5a50;
|
||||
valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_43:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0e1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x78e1; op2val:0x60e1;
|
||||
valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 86*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_44:
|
||||
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x16e and fs2 == 0 and fe2 == 0x14 and fm2 == 0x16e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x696e; op2val:0x516e;
|
||||
valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 88*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_45:
|
||||
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x104 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x104 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7504; op2val:0x5d04;
|
||||
valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 90*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_46:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x18 and fm2 == 0x32b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b2b; op2val:0x632b;
|
||||
valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 92*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_47:
|
||||
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x775c; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 94*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_48:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7926; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 96*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_49:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7878; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 98*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_50:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b85; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 100*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_51:
|
||||
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x76e5; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 102*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_52:
|
||||
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7399; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 104*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_53:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7bd1; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 106*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_54:
|
||||
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x75ea; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 108*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_55:
|
||||
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
|
||||
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7425; op2val:0x7bff;
|
||||
valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 96;
|
||||
correctval:??; testreg:x2
|
||||
*/
|
||||
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 110*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(29596,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30186,16,FLEN)
|
||||
NAN_BOXED(30186,16,FLEN)
|
||||
NAN_BOXED(30976,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(25279,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(29733,16,FLEN)
|
||||
NAN_BOXED(29733,16,FLEN)
|
||||
NAN_BOXED(31734,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31408,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31004,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30995,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30766,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31070,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31248,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(29905,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31467,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31167,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31157,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30289,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30492,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31495,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(28761,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31672,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30978,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30734,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30108,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30891,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31092,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31449,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31457,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31547,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31398,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(29838,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31444,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(28073,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30352,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(29875,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31482,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30953,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31166,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31499,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30730,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(29939,16,FLEN)
|
||||
NAN_BOXED(23795,16,FLEN)
|
||||
NAN_BOXED(30923,16,FLEN)
|
||||
NAN_BOXED(24779,16,FLEN)
|
||||
NAN_BOXED(29264,16,FLEN)
|
||||
NAN_BOXED(23120,16,FLEN)
|
||||
NAN_BOXED(30945,16,FLEN)
|
||||
NAN_BOXED(24801,16,FLEN)
|
||||
NAN_BOXED(26990,16,FLEN)
|
||||
NAN_BOXED(20846,16,FLEN)
|
||||
NAN_BOXED(29956,16,FLEN)
|
||||
NAN_BOXED(23812,16,FLEN)
|
||||
NAN_BOXED(31531,16,FLEN)
|
||||
NAN_BOXED(25387,16,FLEN)
|
||||
NAN_BOXED(30556,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31014,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30840,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31621,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30437,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(29593,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(31697,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(30186,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(29733,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 112*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,256 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Mon May 8 04:56:28 2023 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_flh.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the flh instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the flh-align covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*);def TEST_CASE_1=True;",flh-align)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:// rs1==x31, rd==f31,ea_align == 0 and (imm_val % 4) == 0, imm_val < 0
|
||||
// opcode:flh op1:x31; dest:f31; immval:-0x4; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,159,x31,f31,-0x4,flh,0,x4)
|
||||
|
||||
inst_1:// rs1==x30, rd==f30,ea_align == 0 and (imm_val % 4) == 1,
|
||||
// opcode:flh op1:x30; dest:f30; immval:-0x3; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,159,x30,f30,-0x3,flh,0,x4)
|
||||
|
||||
inst_2:// rs1==x29, rd==f29,ea_align == 0 and (imm_val % 4) == 2,
|
||||
// opcode:flh op1:x29; dest:f29; immval:-0x6; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,159,x29,f29,-0x6,flh,0,x4)
|
||||
|
||||
inst_3:// rs1==x28, rd==f28,ea_align == 0 and (imm_val % 4) == 3, imm_val > 0
|
||||
// opcode:flh op1:x28; dest:f28; immval:0x7ff; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,159,x28,f28,0x7ff,flh,0,x4)
|
||||
|
||||
inst_4:// rs1==x27, rd==f27,imm_val == 0,
|
||||
// opcode:flh op1:x27; dest:f27; immval:0x0; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,159,x27,f27,0x0,flh,0,x4)
|
||||
|
||||
inst_5:// rs1==x26, rd==f26,
|
||||
// opcode:flh op1:x26; dest:f26; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x26,f26,-0x800,flh,0,x4)
|
||||
|
||||
inst_6:// rs1==x25, rd==f25,
|
||||
// opcode:flh op1:x25; dest:f25; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x25,f25,-0x800,flh,0,x4)
|
||||
|
||||
inst_7:// rs1==x24, rd==f24,
|
||||
// opcode:flh op1:x24; dest:f24; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x24,f24,-0x800,flh,0,x4)
|
||||
|
||||
inst_8:// rs1==x23, rd==f23,
|
||||
// opcode:flh op1:x23; dest:f23; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x23,f23,-0x800,flh,0,x4)
|
||||
|
||||
inst_9:// rs1==x22, rd==f22,
|
||||
// opcode:flh op1:x22; dest:f22; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x22,f22,-0x800,flh,0,x4)
|
||||
|
||||
inst_10:// rs1==x21, rd==f21,
|
||||
// opcode:flh op1:x21; dest:f21; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x21,f21,-0x800,flh,0,x4)
|
||||
|
||||
inst_11:// rs1==x20, rd==f20,
|
||||
// opcode:flh op1:x20; dest:f20; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x20,f20,-0x800,flh,0,x4)
|
||||
|
||||
inst_12:// rs1==x19, rd==f19,
|
||||
// opcode:flh op1:x19; dest:f19; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x19,f19,-0x800,flh,0,x4)
|
||||
|
||||
inst_13:// rs1==x18, rd==f18,
|
||||
// opcode:flh op1:x18; dest:f18; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x18,f18,-0x800,flh,0,x4)
|
||||
|
||||
inst_14:// rs1==x17, rd==f17,
|
||||
// opcode:flh op1:x17; dest:f17; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x17,f17,-0x800,flh,0,x4)
|
||||
|
||||
inst_15:// rs1==x16, rd==f16,
|
||||
// opcode:flh op1:x16; dest:f16; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x16,f16,-0x800,flh,0,x4)
|
||||
|
||||
inst_16:// rs1==x15, rd==f15,
|
||||
// opcode:flh op1:x15; dest:f15; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x15,f15,-0x800,flh,0,x4)
|
||||
|
||||
inst_17:// rs1==x14, rd==f14,
|
||||
// opcode:flh op1:x14; dest:f14; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x14,f14,-0x800,flh,0,x4)
|
||||
|
||||
inst_18:// rs1==x13, rd==f13,
|
||||
// opcode:flh op1:x13; dest:f13; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x13,f13,-0x800,flh,0,x4)
|
||||
|
||||
inst_19:// rs1==x12, rd==f12,
|
||||
// opcode:flh op1:x12; dest:f12; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x12,f12,-0x800,flh,0,x4)
|
||||
|
||||
inst_20:// rs1==x11, rd==f11,
|
||||
// opcode:flh op1:x11; dest:f11; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x11,f11,-0x800,flh,0,x4)
|
||||
|
||||
inst_21:// rs1==x10, rd==f10,
|
||||
// opcode:flh op1:x10; dest:f10; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x10,f10,-0x800,flh,0,x4)
|
||||
|
||||
inst_22:// rs1==x9, rd==f9,
|
||||
// opcode:flh op1:x9; dest:f9; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x9,f9,-0x800,flh,0,x4)
|
||||
|
||||
inst_23:// rs1==x8, rd==f8,
|
||||
// opcode:flh op1:x8; dest:f8; immval:-0x800; align:0; flagreg:x4
|
||||
TEST_LOAD_F(x1,x2,0,x8,f8,-0x800,flh,0,x4)
|
||||
RVTEST_VALBASEUPD(x8,test_dataset_1)
|
||||
|
||||
inst_24:// rs1==x7, rd==f7,
|
||||
// opcode:flh op1:x7; dest:f7; immval:-0x800; align:0; flagreg:x9
|
||||
TEST_LOAD_F(x1,x2,0,x7,f7,-0x800,flh,0,x9)
|
||||
|
||||
inst_25:// rs1==x6, rd==f6,
|
||||
// opcode:flh op1:x6; dest:f6; immval:-0x800; align:0; flagreg:x9
|
||||
TEST_LOAD_F(x1,x2,0,x6,f6,-0x800,flh,0,x9)
|
||||
|
||||
inst_26:// rs1==x5, rd==f5,
|
||||
// opcode:flh op1:x5; dest:f5; immval:-0x800; align:0; flagreg:x9
|
||||
TEST_LOAD_F(x1,x6,0,x5,f5,-0x800,flh,0,x9)
|
||||
RVTEST_SIGBASE(x5,signature_x5_0)
|
||||
|
||||
inst_27:// rs1==x4, rd==f4,
|
||||
// opcode:flh op1:x4; dest:f4; immval:-0x800; align:0; flagreg:x9
|
||||
TEST_LOAD_F(x5,x6,0,x4,f4,-0x800,flh,0,x9)
|
||||
|
||||
inst_28:// rs1==x3, rd==f3,
|
||||
// opcode:flh op1:x3; dest:f3; immval:-0x800; align:0; flagreg:x9
|
||||
TEST_LOAD_F(x5,x6,0,x3,f3,-0x800,flh,0,x9)
|
||||
|
||||
inst_29:// rs1==x2, rd==f2,
|
||||
// opcode:flh op1:x2; dest:f2; immval:-0x800; align:0; flagreg:x9
|
||||
TEST_LOAD_F(x5,x6,0,x2,f2,-0x800,flh,0,x9)
|
||||
|
||||
inst_30:// rs1==x1, rd==f1,
|
||||
// opcode:flh op1:x1; dest:f1; immval:-0x800; align:0; flagreg:x9
|
||||
TEST_LOAD_F(x5,x6,0,x1,f1,-0x800,flh,0,x9)
|
||||
|
||||
inst_31:// rd==f0,
|
||||
// opcode:flh op1:x31; dest:f0; immval:-0x800; align:0; flagreg:x9
|
||||
TEST_LOAD_F(x5,x6,0,x31,f0,-0x800,flh,0,x9)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
test_dataset_1:
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x5_0:
|
||||
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
138939
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b1-01.S
Normal file
138939
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b1-01.S
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,519 @@
|
|||
|
||||
// -----------
|
||||
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
|
||||
// version : 0.11.0
|
||||
// timestamp : Tue Jan 30 08:43:40 2024 GMT
|
||||
// usage : riscv_ctg \
|
||||
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
|
||||
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmadd.cgf \
|
||||
\
|
||||
// -- xlen 32 \
|
||||
// -----------
|
||||
//
|
||||
// -----------
|
||||
// Copyright (c) 2020. RISC-V International. All rights reserved.
|
||||
// SPDX-License-Identifier: BSD-3-Clause
|
||||
// -----------
|
||||
//
|
||||
// This assembly file tests the fmadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmadd_b14 covergroup.
|
||||
//
|
||||
#include "model_test.h"
|
||||
#include "arch_test.h"
|
||||
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
|
||||
|
||||
.section .text.init
|
||||
.globl rvtest_entry_point
|
||||
rvtest_entry_point:
|
||||
RVMODEL_BOOT
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#ifdef TEST_CASE_1
|
||||
|
||||
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmadd_b14)
|
||||
|
||||
RVTEST_FP_ENABLE()
|
||||
RVTEST_VALBASEUPD(x3,test_dataset_0)
|
||||
RVTEST_SIGBASE(x1,signature_x1_1)
|
||||
|
||||
inst_0:
|
||||
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f30, rs2==f29, rs3==f29, rd==f31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f29; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x7a0f; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f29, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_1:
|
||||
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f29, rs2==f31, rs3==f30, rd==f29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0f and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f29; op2:f31; op3:f30; dest:f29; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x3eb9; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f29, f29, f31, f30, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_2:
|
||||
// rs1 == rs2 == rs3 != rd, rs1==f28, rs2==f28, rs3==f28, rd==f30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x10 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f28; op2:f28; op3:f28; dest:f30; op1val:0x7ac0; op2val:0x7ac0;
|
||||
op3val:0x7ac0; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f30, f28, f28, f28, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_3:
|
||||
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f27, rs2==f27, rs3==f31, rd==f28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f27; op2:f27; op3:f31; dest:f28; op1val:0x7ac0; op2val:0x7ac0;
|
||||
op3val:0x46b9; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f28, f27, f27, f31, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_4:
|
||||
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f26, rs2==f30, rs3==f26, rd==f27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f26; op2:f30; op3:f26; dest:f27; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x7ac0; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f27, f26, f30, f26, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_5:
|
||||
// rd == rs2 == rs3 != rs1, rs1==f31, rs2==f25, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f31; op2:f25; op3:f25; dest:f25; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x7a0f; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f25, f31, f25, f25, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_6:
|
||||
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f25, rs2==f24, rs3==f27, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f25; op2:f24; op3:f27; dest:f26; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x52b9; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f26, f25, f24, f27, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_7:
|
||||
// rs1 == rs2 == rs3 == rd, rs1==f23, rs2==f23, rs3==f23, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x15 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f23; op2:f23; op3:f23; dest:f23; op1val:0x7ac0; op2val:0x7ac0;
|
||||
op3val:0x7ac0; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f23, f23, f23, f23, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_8:
|
||||
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f22, rs2==f26, rs3==f24, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x16 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f22; op2:f26; op3:f24; dest:f24; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x5ab9; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f24, f22, f26, f24, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_9:
|
||||
// rs1 == rs2 == rd != rs3, rs1==f21, rs2==f21, rs3==f22, rd==f21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x17 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f21; op2:f21; op3:f22; dest:f21; op1val:0x7ac0; op2val:0x7ac0;
|
||||
op3val:0x5eb9; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f21, f21, f21, f22, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_10:
|
||||
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f24, rs2==f22, rs3==f21, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f24; op2:f22; op3:f21; dest:f22; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x62b9; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f22, f24, f22, f21, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_11:
|
||||
// rs1 == rd == rs3 != rs2, rs1==f20, rs2==f19, rs3==f20, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f20; op2:f19; op3:f20; dest:f20; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x7ac0; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f20, f20, f19, f20, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_12:
|
||||
// rs1==f18, rs2==f20, rs3==f17, rd==f19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f18; op2:f20; op3:f17; dest:f19; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x6ab9; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f19, f18, f20, f17, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_13:
|
||||
// rs1==f19, rs2==f17, rs3==f16, rd==f18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x6eb9; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f18, f19, f17, f16, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_14:
|
||||
// rs1==f16, rs2==f18, rs3==f19, rd==f17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x72b9; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f17, f16, f18, f19, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_15:
|
||||
// rs1==f17, rs2==f15, rs3==f18, rd==f16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f17; op2:f15; op3:f18; dest:f16; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x76b9; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f16, f17, f15, f18, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_16:
|
||||
// rs1==f14, rs2==f16, rs3==f13, rd==f15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f14; op2:f16; op3:f13; dest:f15; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x7ab9; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f15, f14, f16, f13, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_17:
|
||||
// rs1==f15, rs2==f13, rs3==f12, rd==f14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x7bff; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f14, f15, f13, f12, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_18:
|
||||
// rs1==f12, rs2==f14, rs3==f15, rd==f13,
|
||||
/* opcode: fmadd.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f13, f12, f14, f15, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_19:
|
||||
// rs1==f13, rs2==f11, rs3==f14, rd==f12,
|
||||
/* opcode: fmadd.h ; op1:f13; op2:f11; op3:f14; dest:f12; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f12, f13, f11, f14, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_20:
|
||||
// rs1==f10, rs2==f12, rs3==f9, rd==f11,
|
||||
/* opcode: fmadd.h ; op1:f10; op2:f12; op3:f9; dest:f11; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f11, f10, f12, f9, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_21:
|
||||
// rs1==f11, rs2==f9, rs3==f8, rd==f10,
|
||||
/* opcode: fmadd.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f10, f11, f9, f8, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_22:
|
||||
// rs1==f8, rs2==f10, rs3==f11, rd==f9,
|
||||
/* opcode: fmadd.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f9, f8, f10, f11, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_23:
|
||||
// rs1==f9, rs2==f7, rs3==f10, rd==f8,
|
||||
/* opcode: fmadd.h ; op1:f9; op2:f7; op3:f10; dest:f8; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f8, f9, f7, f10, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_24:
|
||||
// rs1==f6, rs2==f8, rs3==f5, rd==f7,
|
||||
/* opcode: fmadd.h ; op1:f6; op2:f8; op3:f5; dest:f7; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f7, f6, f8, f5, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_25:
|
||||
// rs1==f7, rs2==f5, rs3==f4, rd==f6,
|
||||
/* opcode: fmadd.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f6, f7, f5, f4, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_26:
|
||||
// rs1==f4, rs2==f6, rs3==f7, rd==f5,
|
||||
/* opcode: fmadd.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f5, f4, f6, f7, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_27:
|
||||
// rs1==f5, rs2==f3, rs3==f6, rd==f4,
|
||||
/* opcode: fmadd.h ; op1:f5; op2:f3; op3:f6; dest:f4; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f4, f5, f3, f6, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_28:
|
||||
// rs1==f2, rs2==f4, rs3==f1, rd==f3,
|
||||
/* opcode: fmadd.h ; op1:f2; op2:f4; op3:f1; dest:f3; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f3, f2, f4, f1, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_29:
|
||||
// rs1==f3, rs2==f1, rs3==f0, rd==f2,
|
||||
/* opcode: fmadd.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f2, f3, f1, f0, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_30:
|
||||
// rs1==f0, rs2==f2, rs3==f3, rd==f1,
|
||||
/* opcode: fmadd.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f1, f0, f2, f3, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_31:
|
||||
// rs1==f1,
|
||||
/* opcode: fmadd.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f31, f1, f30, f29, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_32:
|
||||
// rs2==f0,
|
||||
/* opcode: fmadd.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f31, f30, f0, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_33:
|
||||
// rs3==f2,
|
||||
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f2; dest:f31; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f2, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_34:
|
||||
// rd==f0,
|
||||
/* opcode: fmadd.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x0; op2val:0x0;
|
||||
op3val:0x0; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f0, f31, f30, f29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_35:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x3ab9; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_36:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x10 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x42b9; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_37:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x46b9; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 111*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_38:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x4ab9; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_39:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x4eb9; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_40:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x15 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x56b9; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_41:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x17 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x5eb9; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 123*FLEN/8, x4, x1, x2)
|
||||
|
||||
inst_42:
|
||||
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
|
||||
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
|
||||
op3val:0x66b9; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
|
||||
testreg:x2; fcsr_val:0 */
|
||||
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
|
||||
#endif
|
||||
|
||||
|
||||
RVTEST_CODE_END
|
||||
RVMODEL_HALT
|
||||
|
||||
RVTEST_DATA_BEGIN
|
||||
.align 4
|
||||
rvtest_data:
|
||||
.word 0xbabecafe
|
||||
.word 0xabecafeb
|
||||
.word 0xbecafeba
|
||||
.word 0xecafebab
|
||||
test_dataset_0:
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(16057,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(18105,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(21177,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(23225,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(24249,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(25273,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(27321,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(28345,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(29369,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(30393,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(31417,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(31743,16,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(0,32,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(15033,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(17081,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(18105,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(19129,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(20153,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(22201,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(24249,16,FLEN)
|
||||
NAN_BOXED(31424,16,FLEN)
|
||||
NAN_BOXED(31247,16,FLEN)
|
||||
NAN_BOXED(26297,16,FLEN)
|
||||
RVTEST_DATA_END
|
||||
|
||||
RVMODEL_DATA_BEGIN
|
||||
rvtest_sig_begin:
|
||||
sig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
|
||||
|
||||
signature_x1_0:
|
||||
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
|
||||
signature_x1_1:
|
||||
.fill 86*((SIGALIGN)/4),4,0xdeadbeef
|
||||
|
||||
#ifdef rvtest_mtrap_routine
|
||||
tsig_begin_canary:
|
||||
CANARY;
|
||||
|
||||
mtrap_sigptr:
|
||||
.fill 64*XLEN/32,4,0xdeadbeef
|
||||
|
||||
tsig_end_canary:
|
||||
CANARY;
|
||||
#endif
|
||||
|
||||
#ifdef rvtest_gpr_save
|
||||
|
||||
gpr_save:
|
||||
.fill 32*XLEN/32,4,0xdeadbeef
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
sig_end_canary:
|
||||
CANARY;
|
||||
rvtest_sig_end:
|
||||
RVMODEL_DATA_END
|
||||
101439
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b15-01.S
Normal file
101439
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b15-01.S
Normal file
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue