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Removed unnecessary RV64 PWDATA muxing from AHB peripherals because LSU already replicates

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This commit is contained in:
David Harris 2023-10-18 05:50:41 -07:00
parent b76c371e45
commit 48d42c1e7c
4 changed files with 9 additions and 41 deletions
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1
src/uncore/ahbapbbridge.sv
View file

@ -88,7 +88,6 @@ module ahbapbbridge import cvw::*; #(parameter cvw_t P,
int i;
always_comb begin
// default: no peripheral selected: read 0, indicate ready during access phase so bus doesn't hang
// *** also could assert ready right away
HRDATA = 0;
PREADYOUT = 1'b1;
for (i=0; i<PERIPHS; i++) begin

11
src/uncore/gpio_apb.sv
View file

@ -59,14 +59,9 @@ module gpio_apb import cvw::*; #(parameter cvw_t P) (
// account for subword read/write circuitry
// -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
// (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported")
if (P.XLEN == 64) begin
assign Din = entry[2] ? PWDATA[63:32] : PWDATA[31:0];
assign PRDATA = entry[2] ? {Dout,32'b0} : {32'b0,Dout};
end else begin // 32-bit
assign Din = PWDATA[31:0];
assign PRDATA = Dout;
end
assign Din = PWDATA[31:0];
if (P.XLEN == 64) assign PRDATA = {Dout, Dout};
else assign PRDATA = Dout;
// register access
always_ff @(posedge PCLK, negedge PRESETn)

10
src/uncore/plic_apb.sv
View file

@ -94,13 +94,9 @@ module plic_apb import cvw::*; #(parameter cvw_t P) (
// account for subword read/write circuitry
// -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
if (P.XLEN == 64) begin
assign Din = entry[2] ? PWDATA[63:32] : PWDATA[31:0];
assign PRDATA = entry[2] ? {Dout,32'b0} : {32'b0,Dout};
end else begin // 32-bit
assign PRDATA = Dout;
assign Din = PWDATA[31:0];
end
assign Din = PWDATA[31:0];
if (P.XLEN == 64) assign PRDATA = {Dout, Dout};
else assign PRDATA = Dout;
// ==================
// Register Interface

28
src/uncore/uart_apb.sv
View file

@ -54,31 +54,9 @@ module uart_apb import cvw::*; #(parameter cvw_t P) (
assign MEMRb = ~memread;
assign MEMWb = ~memwrite;
if (P.XLEN == 64) begin:uart
always_comb begin
PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
case (entry)
3'b000: Din = PWDATA[7:0];
3'b001: Din = PWDATA[15:8];
3'b010: Din = PWDATA[23:16];
3'b011: Din = PWDATA[31:24];
3'b100: Din = PWDATA[39:32];
3'b101: Din = PWDATA[47:40];
3'b110: Din = PWDATA[55:48];
3'b111: Din = PWDATA[63:56];
endcase
end
end else begin:uart // 32-bit
always_comb begin
PRDATA = {Dout, Dout, Dout, Dout};
case (entry[1:0])
2'b00: Din = PWDATA[7:0];
2'b01: Din = PWDATA[15:8];
2'b10: Din = PWDATA[23:16];
2'b11: Din = PWDATA[31:24];
endcase
end
end
assign Din = PWDATA[7:0];
if (P.XLEN == 64) assign PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
else assign PRDATA = {Dout, Dout, Dout, Dout};
logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK
uartPC16550D #(P.UART_PRESCALE) u(