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Merge branch 'main' of https://github.com/openhwgroup/cvw

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This commit is contained in:
Rose Thompson 2024-03-28 13:45:12 -05:00
commit 4a7c16990f
170 changed files with 268 additions and 1475666 deletions
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4
testbench/testbench.sv
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@ -248,8 +248,8 @@ module testbench;
end
always_ff @(posedge clk)
if (TestBenchReset) CurrState <= #1 STATE_TESTBENCH_RESET;
else CurrState <= #1 NextState;
if (TestBenchReset) CurrState <= STATE_TESTBENCH_RESET;
else CurrState <= NextState;
// fsm next state logic
always_comb begin

26
testbench/tests.vh
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@ -1209,8 +1209,7 @@ string imperas32f[] = '{
};
string arch64zfh_fma[] = '{
//`RISCVARCHTEST,
`WALLYTEST,
`RISCVARCHTEST,
"rv64i_m/Zfh/src/fmadd_b15-01.S",
"rv64i_m/Zfh/src/fmsub_b15-01.S",
"rv64i_m/Zfh/src/fnmadd_b15-01.S",
@ -1368,8 +1367,7 @@ string imperas32f[] = '{
};
string arch64zfh_divsqrt[] = '{
//`RISCVARCHTEST,
`WALLYTEST,
`RISCVARCHTEST,
"rv64i_m/Zfh/src/fdiv_b20-01.S",
"rv64i_m/Zfh/src/fdiv_b1-01.S",
"rv64i_m/Zfh/src/fdiv_b2-01.S",
@ -1393,8 +1391,7 @@ string imperas32f[] = '{
};
string arch64zfh[] = '{
//`RISCVARCHTEST,
`WALLYTEST,
`RISCVARCHTEST,
"rv64i_m/Zfh/src/fadd_b10-01.S",
"rv64i_m/Zfh/src/fadd_b1-01.S",
"rv64i_m/Zfh/src/fadd_b11-01.S",
@ -1425,10 +1422,10 @@ string imperas32f[] = '{
"rv64i_m/Zfh/src/fcvt.wu.h_b27-01.S",
"rv64i_m/Zfh/src/fcvt.wu.h_b28-01.S",
"rv64i_m/Zfh/src/fcvt.wu.h_b29-01.S",
// "rv64i_m/Zfh/src/fcvt.h.l_b25-01.S", // tests commented out because they involve a fsd that hangs on vsim -c -do "do wally-batch.do fh_rv64gc arch64zfh" which lacks fsd support
// "rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
// "rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
// "rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
"rv64i_m/Zfh/src/fcvt.h.l_b25-01.S",
"rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
"rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
"rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
"rv64i_m/Zfh/src/fcvt.l.h_b1-01.S",
"rv64i_m/Zfh/src/fcvt.l.h_b22-01.S",
"rv64i_m/Zfh/src/fcvt.l.h_b23-01.S",
@ -2059,8 +2056,7 @@ string arch64zknh[] = '{
};
string arch32zfh_divsqrt[] = '{
//`RISCVARCHTEST,
`WALLYTEST,
`RISCVARCHTEST,
"rv32i_m/Zfh/src/fdiv_b20-01.S",
"rv32i_m/Zfh/src/fdiv_b1-01.S",
"rv32i_m/Zfh/src/fdiv_b2-01.S",
@ -2084,8 +2080,7 @@ string arch64zknh[] = '{
};
string arch32zfh[] = '{
//`RISCVARCHTEST,
`WALLYTEST,
`RISCVARCHTEST,
"rv32i_m/Zfh/src/fadd_b10-01.S",
"rv32i_m/Zfh/src/fadd_b1-01.S",
"rv32i_m/Zfh/src/fadd_b11-01.S",
@ -2310,8 +2305,7 @@ string arch64zknh[] = '{
};
string arch32zfh_fma[] = '{
//`RISCVARCHTEST,
`WALLYTEST,
`RISCVARCHTEST,
"rv32i_m/Zfh/src/fmadd_b15-01.S",
"rv32i_m/Zfh/src/fmsub_b15-01.S",
"rv32i_m/Zfh/src/fnmadd_b15-01.S",

207
tests/testgen/covergen.py Executable file
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@ -0,0 +1,207 @@
#!/usr/bin/python3
##################################
# covergen.py
#
# David_Harris@hmc.edu 27 March 2024
#
# Generate directed tests for functional coverage
##################################
##################################
# libraries
##################################
from datetime import datetime
from random import randint
from random import seed
from random import getrandbits
##################################
# functions
##################################
def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen):
rdval = randint(0, 2**xlen-1)
lines = "\n# Testcase " + str(desc) + "\n"
lines = lines + "li x" + str(rd) + ", MASK_XLEN(" + formatstr.format(rdval) + ") # initialize rd to a random value that should get changed\n"
lines = lines + "li x" + str(rs1) + ", MASK_XLEN(" + formatstr.format(rs1val) + ") # initialize rs1 to a random value \n"
lines = lines + "li x" + str(rs2) + ", MASK_XLEN(" + formatstr.format(rs2val) + ") # initialize rs2 to a random value\n"
lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", x" + str(rs2) + " # perform operation\n"
f.write(lines)
def make_cp_rd(rd, test, storecmd, xlen):
rs1 = randint(0, 31)
rs2 = randint(0, 31)
rs1val = randint(0, 2**xlen-1)
rs2val = randint(0, 2**xlen-1)
desc = "cp_rd (Test destination rd = x" + str(rd) + ")"
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
def make_cp_rs1(rs1, test, storecmd, xlen):
rd = randint(0, 31)
rs2 = randint(0, 31)
rs1val = randint(0, 2**xlen-1)
rs2val = randint(0, 2**xlen-1)
desc = "cp_rs1 (Test source rs1 = x" + str(rs1) + ")"
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
def make_cp_rs2(rs2, test, storecmd, xlen):
rd = randint(0, 31)
rs1 = randint(0, 31)
rs1val = randint(0, 2**xlen-1)
rs2val = randint(0, 2**xlen-1)
desc = "cp_rs2 (Test source rs2 = x" + str(rs2) + ")"
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
def make_cmp_rd_rs1(r, test, storecmd, xlen):
rd = r
rs1 = r
rs2 = randint(0, 31)
rs1val = randint(0, 2**xlen-1)
rs2val = randint(0, 2**xlen-1)
desc = "cmp_rd_rs1 (Test destination rd = source rs1 = x" + str(r) + ")"
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
def make_cmp_rd_rs2(r, test, storecmd, xlen):
rd = r
rs1 = randint(0, 31)
rs2 = r
rs1val = randint(0, 2**xlen-1)
rs2val = randint(0, 2**xlen-1)
desc = "cmp_rd_rs2 (Test destination rd = source rs2 = x" + str(r) + ")"
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
def make_cmp_rd_rs1_rs2(r, test, storecmd, xlen):
rd = r
rs1 = r
rs2 = r
rs1val = randint(0, 2**xlen-1)
rs2val = randint(0, 2**xlen-1)
desc = "cmp_rd_rs1_rs2 (Test destination rd = source rs1 = source rs2 = x" + str(r) + ")"
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
def make_cp_gpr_hazard(test, storecmd, xlen):
rs1val = randint(0, 2**xlen-1)
rs2val = randint(0, 2**xlen-1)
desc = "cp_gpr_hazard"
writeCovVector(desc, 20, 21, 22, rs1val, rs2val, test, storecmd, xlen)
lines = test + " x23, x22, x20 # RAW\n"
lines = lines + test + " x22, x23, x20 # WAR\n"
lines = lines + test + " x22, x21, x20 # WAW\n"
f.write(lines)
def make_cp_rs1_maxvals(test, storecmd, xlen):
for rs1val in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
rd = randint(1, 31)
rs1 = randint(0, 31)
rs2 = randint(0, 31)
rs2val = randint(0, 2**xlen-1)
desc = "cp_rs1_maxvals (rs1 = " + str(rs1val) + ")"
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
def make_cp_rs2_maxvals(test, storecmd, xlen):
for rs2val in [0, 2**(xlen-1), 2**(xlen-1)-1, 2**xlen-1, 1, 2**(xlen-1)+1]:
rd = randint(1, 31)
rs1 = randint(0, 31)
rs2 = randint(0, 31)
rs1val = randint(0, 2**xlen-1)
desc = "cp_rs2_maxvals (rs2 = " + str(rs2val) + ")"
writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen)
def writeCovVector(desc, rs1, rs2, rd, rs1val, rs2val, test, storecmd, xlen):
rdval = randint(0, 2**xlen-1)
lines = "\n# Testcase " + str(desc) + "\n"
lines = lines + "li x" + str(rd) + ", MASK_XLEN(" + formatstr.format(rdval) + ") # initialize rd to a random value that should get changed\n"
lines = lines + "li x" + str(rs1) + ", MASK_XLEN(" + formatstr.format(rs1val) + ") # initialize rs1 to a random value \n"
lines = lines + "li x" + str(rs2) + ", MASK_XLEN(" + formatstr.format(rs2val) + ") # initialize rs2 to a random value\n"
lines = lines + test + " x" + str(rd) + ", x" + str(rs1) + ", x" + str(rs2) + " # perform operation\n"
f.write(lines)
def write_rtype_arith_vectors(test, storecmd, xlen):
for r in range(32):
make_cp_rd(r, test, storecmd, xlen)
for r in range(32):
make_cp_rs1(r, test, storecmd, xlen)
for r in range(32):
make_cp_rs2(r, test, storecmd, xlen)
for r in range(32):
make_cmp_rd_rs2(r, test, storecmd, xlen)
for r in range(32):
make_cmp_rd_rs1(r, test, storecmd, xlen)
for r in range(32):
make_cmp_rd_rs1_rs2(r, test, storecmd, xlen)
make_cp_gpr_hazard(test, storecmd, xlen)
make_cp_rs1_maxvals(test, storecmd, xlen)
make_cp_rs2_maxvals(test, storecmd, xlen)
##################################
# main body
##################################
# change these to suite your tests
rtests = ["ADD", "SUB", "SLT", "SLTU", "XOR"]
tests = rtests
author = "David_Harris@hmc.edu"
xlens = [64]
numrand = 3
# setup
seed(0) # make tests reproducible
# generate files for each test
for xlen in xlens:
formatstrlen = str(int(xlen/4))
formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
if (xlen == 32):
storecmd = "sw"
wordsize = 4
else:
storecmd = "sd"
wordsize = 8
for test in tests:
# corners = [0, 1, 2, 0xFF, 0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1,
# 2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1]
corners = [0, 1, 2**(xlen)-1]
pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
basename = "WALLY-COV-" + test
fname = pathname + "src/" + basename + ".S"
# print custom header part
f = open(fname, "w")
line = "///////////////////////////////////////////\n"
f.write(line)
lines="// "+fname+ "\n// " + author + "\n"
f.write(lines)
line ="// Created " + str(datetime.now())
f.write(line)
# insert generic header
h = open("covergen_header.S", "r")
for line in h:
f.write(line)
# print directed and random test vectors
# Coverage for R-type arithmetic instructions
if (test not in rtests):
exit("Error: %s not implemented yet" % test)
else:
write_rtype_arith_vectors(test, storecmd, xlen)
# print footer
line = "\n.EQU NUMTESTS," + str(1) + "\n\n"
f.write(line)
h = open("covergen_footer.S", "r")
for line in h:
f.write(line)
# Finish
# lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
# lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
f.write(lines)
f.close()

30
tests/testgen/covergen_footer.S Normal file
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@ -0,0 +1,30 @@
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0x98765432
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
wally_signature:
.fill NUMTESTS*(XLEN/32),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32),4,0xdeadbeef
#endif
RVMODEL_DATA_END

18
tests/testgen/covergen_header.S Normal file
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@ -0,0 +1,18 @@
//
// Copyright (C) 2024 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
///////////////////////////////////////////
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",temp)

2
tests/testgen/testgen_header.S
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@ -1,5 +1,5 @@
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
// Copyright (C) 2024 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
///////////////////////////////////////////

5311
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fadd_b1-01.S
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File diff suppressed because it is too large Load diff

413
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fadd_b10-01.S
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@ -1,413 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Sat May 6 11:38:58 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fadd_b10 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fadd_b10)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f31; op2:f31; dest:f31; op1val:0x52ee; op2val:0x52ee;
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f29, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0a and fm2 == 0x262 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f29; op2:f28; dest:f30; op1val:0x52ee; op2val:0x2a62;
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f30, f29, f28, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x0d and fm2 == 0x3fb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f29; op1val:0x52ee; op2val:0x37fb;
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f29, f30, f29, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x11 and fm2 == 0x0fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f28; op2:f30; dest:f28; op1val:0x52ee; op2val:0x44fd;
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f28, f28, f30, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x14 and fm2 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f26; op2:f26; dest:f27; op1val:0x52ee; op2val:0x52ee;
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f27, f26, f26, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x17 and fm2 == 0x3cb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f27; op2:f25; dest:f26; op1val:0x52ee; op2val:0x5fcb;
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f26, f27, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:// rs1==f24, rs2==f27, rd==f25,
/* opcode: fadd.h ; op1:f24; op2:f27; dest:f25; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f25, f24, f27, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:// rs1==f25, rs2==f23, rd==f24,
/* opcode: fadd.h ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f24, f25, f23, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:// rs1==f22, rs2==f24, rd==f23,
/* opcode: fadd.h ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f23, f22, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:// rs1==f23, rs2==f21, rd==f22,
/* opcode: fadd.h ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f22, f23, f21, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:// rs1==f20, rs2==f22, rd==f21,
/* opcode: fadd.h ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:// rs1==f21, rs2==f19, rd==f20,
/* opcode: fadd.h ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f20, f21, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:// rs1==f18, rs2==f20, rd==f19,
/* opcode: fadd.h ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f19, f18, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:// rs1==f19, rs2==f17, rd==f18,
/* opcode: fadd.h ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f18, f19, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:// rs1==f16, rs2==f18, rd==f17,
/* opcode: fadd.h ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f17, f16, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:// rs1==f17, rs2==f15, rd==f16,
/* opcode: fadd.h ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f16, f17, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:// rs1==f14, rs2==f16, rd==f15,
/* opcode: fadd.h ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f15, f14, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:// rs1==f15, rs2==f13, rd==f14,
/* opcode: fadd.h ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f14, f15, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:// rs1==f12, rs2==f14, rd==f13,
/* opcode: fadd.h ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f13, f12, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:// rs1==f13, rs2==f11, rd==f12,
/* opcode: fadd.h ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f12, f13, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:// rs1==f10, rs2==f12, rd==f11,
/* opcode: fadd.h ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f11, f10, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:// rs1==f11, rs2==f9, rd==f10,
/* opcode: fadd.h ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f10, f11, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:// rs1==f8, rs2==f10, rd==f9,
/* opcode: fadd.h ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f9, f8, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:// rs1==f9, rs2==f7, rd==f8,
/* opcode: fadd.h ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f8, f9, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:// rs1==f6, rs2==f8, rd==f7,
/* opcode: fadd.h ; op1:f6; op2:f8; dest:f7; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f7, f6, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:// rs1==f7, rs2==f5, rd==f6,
/* opcode: fadd.h ; op1:f7; op2:f5; dest:f6; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f6, f7, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:// rs1==f4, rs2==f6, rd==f5,
/* opcode: fadd.h ; op1:f4; op2:f6; dest:f5; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f5, f4, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:// rs1==f5, rs2==f3, rd==f4,
/* opcode: fadd.h ; op1:f5; op2:f3; dest:f4; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f4, f5, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:// rs1==f2, rs2==f4, rd==f3,
/* opcode: fadd.h ; op1:f2; op2:f4; dest:f3; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f3, f2, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:// rs1==f3, rs2==f1, rd==f2,
/* opcode: fadd.h ; op1:f3; op2:f1; dest:f2; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f2, f3, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:// rs1==f0, rs2==f2, rd==f1,
/* opcode: fadd.h ; op1:f0; op2:f2; dest:f1; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f1, f0, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:// rs1==f1,
/* opcode: fadd.h ; op1:f1; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f1, f30, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:// rs2==f0,
/* opcode: fadd.h ; op1:f30; op2:f0; dest:f31; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f0, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
inst_33:// rd==f0,
/* opcode: fadd.h ; op1:f31; op2:f30; dest:f0; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f0, f31, f30, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_34:// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x00 and fm2 == 0x053 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x52ee; op2val:0x53;
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
inst_35:// fs1 == 0 and fe1 == 0x14 and fm1 == 0x2ee and fs2 == 0 and fe2 == 0x14 and fm2 == 0x23c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x52ee; op2val:0x523c;
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(21230,16,FLEN)
NAN_BOXED(21230,16,FLEN)
NAN_BOXED(21230,16,FLEN)
NAN_BOXED(10850,16,FLEN)
NAN_BOXED(21230,16,FLEN)
NAN_BOXED(14331,16,FLEN)
NAN_BOXED(21230,16,FLEN)
NAN_BOXED(17661,16,FLEN)
NAN_BOXED(21230,16,FLEN)
NAN_BOXED(21230,16,FLEN)
NAN_BOXED(21230,16,FLEN)
NAN_BOXED(24523,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(21230,16,FLEN)
NAN_BOXED(83,16,FLEN)
NAN_BOXED(21230,16,FLEN)
NAN_BOXED(21052,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 72*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

30459
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fadd_b11-01.S
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File diff suppressed because it is too large Load diff

548
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fadd_b12-01.S
View file

@ -1,548 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Sat May 6 11:38:58 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fadd_b12 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fadd_b12)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 1 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f31; op2:f31; dest:f31; op1val:0xfac0; op2val:0xfac0;
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f29, rs2==f28, rd==f30,fs1 == 1 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x16e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f29; op2:f28; dest:f30; op1val:0xf6b9; op2val:0x796e;
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f30, f29, f28, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 1 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x353 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f29; op1val:0xf816; op2val:0x7b53;
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f29, f30, f29, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 1 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f28; op2:f30; dest:f28; op1val:0xfa44; op2val:0x7bff;
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f28, f28, f30, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 1 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f26; op2:f26; dest:f27; op1val:0xf79f; op2val:0xf79f;
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f27, f26, f26, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:// rs1==f27, rs2==f25, rd==f26,fs1 == 1 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f27; op2:f25; dest:f26; op1val:0xfb42; op2val:0x7bff;
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f26, f27, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:// rs1==f24, rs2==f27, rd==f25,fs1 == 1 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f24; op2:f27; dest:f25; op1val:0xf481; op2val:0x7bff;
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f25, f24, f27, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:// rs1==f25, rs2==f23, rd==f24,fs1 == 1 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2f2 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f25; op2:f23; dest:f24; op1val:0xf8f1; op2val:0x7af2;
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f24, f25, f23, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:// rs1==f22, rs2==f24, rd==f23,fs1 == 1 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f22; op2:f24; dest:f23; op1val:0xfb46; op2val:0x7bff;
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f23, f22, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:// rs1==f23, rs2==f21, rd==f22,fs1 == 1 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f23; op2:f21; dest:f22; op1val:0xfa7a; op2val:0x7bff;
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f22, f23, f21, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:// rs1==f20, rs2==f22, rd==f21,fs1 == 1 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f20; op2:f22; dest:f21; op1val:0xf4f5; op2val:0x7bff;
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:// rs1==f21, rs2==f19, rd==f20,fs1 == 1 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f21; op2:f19; dest:f20; op1val:0xfb2f; op2val:0x7bff;
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f20, f21, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:// rs1==f18, rs2==f20, rd==f19,fs1 == 1 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x094 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f18; op2:f20; dest:f19; op1val:0xf78c; op2val:0x7894;
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f19, f18, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:// rs1==f19, rs2==f17, rd==f18,fs1 == 1 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f19; op2:f17; dest:f18; op1val:0xf6f1; op2val:0x7bff;
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f18, f19, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:// rs1==f16, rs2==f18, rd==f17,fs1 == 1 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f16; op2:f18; dest:f17; op1val:0xfb4c; op2val:0x7bff;
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f17, f16, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:// rs1==f17, rs2==f15, rd==f16,fs1 == 1 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f17; op2:f15; dest:f16; op1val:0xf7a0; op2val:0x7bff;
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f16, f17, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:// rs1==f14, rs2==f16, rd==f15,fs1 == 1 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f14; op2:f16; dest:f15; op1val:0xf42a; op2val:0x7bff;
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f15, f14, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:// rs1==f15, rs2==f13, rd==f14,fs1 == 1 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x07f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f15; op2:f13; dest:f14; op1val:0xf863; op2val:0x787f;
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f14, f15, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:// rs1==f12, rs2==f14, rd==f13,fs1 == 1 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f12; op2:f14; dest:f13; op1val:0xf9c1; op2val:0x7bff;
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f13, f12, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:// rs1==f13, rs2==f11, rd==f12,fs1 == 1 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f13; op2:f11; dest:f12; op1val:0xfa98; op2val:0x7bff;
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f12, f13, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:// rs1==f10, rs2==f12, rd==f11,fs1 == 1 and fe1 == 0x15 and fm1 == 0x0ad and fs2 == 0 and fe2 == 0x1d and fm2 == 0x3e9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f10; op2:f12; dest:f11; op1val:0xd4ad; op2val:0x77e9;
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f11, f10, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:// rs1==f11, rs2==f9, rd==f10,fs1 == 1 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f11; op2:f9; dest:f10; op1val:0xfaef; op2val:0x7bff;
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f10, f11, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:// rs1==f8, rs2==f10, rd==f9,fs1 == 1 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f8; op2:f10; dest:f9; op1val:0xf533; op2val:0x7bff;
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f9, f8, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:// rs1==f9, rs2==f7, rd==f8,fs1 == 1 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x210 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f9; op2:f7; dest:f8; op1val:0xf21c; op2val:0x7a10;
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f8, f9, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:// rs1==f6, rs2==f8, rd==f7,fs1 == 1 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f6; op2:f8; dest:f7; op1val:0xf3a1; op2val:0x7bff;
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f7, f6, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:// rs1==f7, rs2==f5, rd==f6,fs1 == 1 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f7; op2:f5; dest:f6; op1val:0xfa6c; op2val:0x7bff;
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f6, f7, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:// rs1==f4, rs2==f6, rd==f5,fs1 == 1 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 0 and fe2 == 0x1d and fm2 == 0x267 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f4; op2:f6; dest:f5; op1val:0xed25; op2val:0x7667;
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f5, f4, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:// rs1==f5, rs2==f3, rd==f4,fs1 == 1 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f5; op2:f3; dest:f4; op1val:0xf80f; op2val:0x7bff;
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f4, f5, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:// rs1==f2, rs2==f4, rd==f3,fs1 == 1 and fe1 == 0x1b and fm1 == 0x2f9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x147 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f2; op2:f4; dest:f3; op1val:0xeef9; op2val:0x7947;
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f3, f2, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:// rs1==f3, rs2==f1, rd==f2,fs1 == 1 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f3; op2:f1; dest:f2; op1val:0xf9a6; op2val:0x7bff;
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f2, f3, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:// rs1==f0, rs2==f2, rd==f1,fs1 == 1 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f0; op2:f2; dest:f1; op1val:0xfa83; op2val:0x7bff;
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f1, f0, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:// rs1==f1,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f1; op2:f30; dest:f31; op1val:0xfbb4; op2val:0x7bff;
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f1, f30, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:// rs2==f0,fs1 == 1 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f0; dest:f31; op1val:0xf8b2; op2val:0x7bff;
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f0, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
inst_33:// rd==f0,fs1 == 1 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f31; op2:f30; dest:f0; op1val:0xf8c4; op2val:0x7bd8;
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f0, f31, f30, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_34:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2ec and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf89a; op2val:0x7aec;
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
inst_35:// fs1 == 1 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 0 and fe2 == 0x1d and fm2 == 0x203 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf20e; op2val:0x7603;
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
inst_36:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf8e6; op2val:0x7bff;
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_37:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x087 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf79e; op2val:0x7887;
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
inst_38:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfa0e; op2val:0x7bff;
valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
inst_39:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfb62; op2val:0x7bff;
valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_40:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfb2e; op2val:0x7bff;
valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
inst_41:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x373 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf852; op2val:0x7b73;
valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
inst_42:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3d7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf9a3; op2val:0x7bd7;
valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
inst_43:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfa7d; op2val:0x7bff;
valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
inst_44:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfb28; op2val:0x7bff;
valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
inst_45:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfb98; op2val:0x7bff;
valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
inst_46:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf734; op2val:0x7bff;
valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
inst_47:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfbf7; op2val:0x7bff;
valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
inst_48:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfa57; op2val:0x7b00;
valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
inst_49:// fs1 == 1 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xfac0; op2val:0x7bff;
valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
inst_50:// fs1 == 1 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0xf79f; op2val:0x7bff;
valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(64192,16,FLEN)
NAN_BOXED(64192,16,FLEN)
NAN_BOXED(63161,16,FLEN)
NAN_BOXED(31086,16,FLEN)
NAN_BOXED(63510,16,FLEN)
NAN_BOXED(31571,16,FLEN)
NAN_BOXED(64068,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(63391,16,FLEN)
NAN_BOXED(63391,16,FLEN)
NAN_BOXED(64322,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(62593,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(63729,16,FLEN)
NAN_BOXED(31474,16,FLEN)
NAN_BOXED(64326,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64122,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(62709,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64303,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(63372,16,FLEN)
NAN_BOXED(30868,16,FLEN)
NAN_BOXED(63217,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64332,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(63392,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(62506,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(63587,16,FLEN)
NAN_BOXED(30847,16,FLEN)
NAN_BOXED(63937,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64152,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(54445,16,FLEN)
NAN_BOXED(30697,16,FLEN)
NAN_BOXED(64239,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(62771,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(61980,16,FLEN)
NAN_BOXED(31248,16,FLEN)
NAN_BOXED(62369,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64108,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(60709,16,FLEN)
NAN_BOXED(30311,16,FLEN)
NAN_BOXED(63503,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(61177,16,FLEN)
NAN_BOXED(31047,16,FLEN)
NAN_BOXED(63910,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64131,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64436,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(63666,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(63684,16,FLEN)
NAN_BOXED(31704,16,FLEN)
NAN_BOXED(63642,16,FLEN)
NAN_BOXED(31468,16,FLEN)
NAN_BOXED(61966,16,FLEN)
NAN_BOXED(30211,16,FLEN)
NAN_BOXED(63718,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(63390,16,FLEN)
NAN_BOXED(30855,16,FLEN)
NAN_BOXED(64014,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64354,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64302,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(63570,16,FLEN)
NAN_BOXED(31603,16,FLEN)
NAN_BOXED(63907,16,FLEN)
NAN_BOXED(31703,16,FLEN)
NAN_BOXED(64125,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64296,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64408,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(63284,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64503,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64087,16,FLEN)
NAN_BOXED(31488,16,FLEN)
NAN_BOXED(64192,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(63391,16,FLEN)
NAN_BOXED(31743,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 102*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fadd_b13-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fadd_b2-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fadd_b3-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fadd_b4-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fadd_b5-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fadd_b7-01.S
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@ -1,602 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Sat May 6 11:38:58 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fadd.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fadd_b7 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fadd_b7)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1 == rs2 == rd, rs1==f31, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f31; op2:f31; dest:f31; op1val:0x7ac0; op2val:0x7ac0;
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f31, f31, dyn, 96, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f29, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2b9 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2b9 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f29; op2:f28; dest:f30; op1val:0x76b9; op2val:0xf6b9;
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f30, f29, f28, dyn, 96, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:// rs2 == rd != rs1, rs1==f30, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x016 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x016 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f29; op1val:0x7816; op2val:0xf816;
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f29, f30, f29, dyn, 96, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x244 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x244 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f28; op2:f30; dest:f28; op1val:0x7a44; op2val:0xfa44;
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f28, f28, f30, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f26; op2:f26; dest:f27; op1val:0x779f; op2val:0x779f;
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f27, f26, f26, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x342 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f27; op2:f25; dest:f26; op1val:0x7b42; op2val:0xfb42;
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f26, f27, f25, dyn, 96, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x081 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x081 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f24; op2:f27; dest:f25; op1val:0x7481; op2val:0xf481;
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f25, f24, f27, dyn, 96, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0f1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0f1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f25; op2:f23; dest:f24; op1val:0x78f1; op2val:0xf8f1;
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f24, f25, f23, dyn, 96, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x346 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f22; op2:f24; dest:f23; op1val:0x7b46; op2val:0xfb46;
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f23, f22, f24, dyn, 96, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x27a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f23; op2:f21; dest:f22; op1val:0x7a7a; op2val:0xfa7a;
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f22, f23, f21, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f5 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f20; op2:f22; dest:f21; op1val:0x74f5; op2val:0xf4f5;
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f21, f20, f22, dyn, 96, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x32f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f21; op2:f19; dest:f20; op1val:0x7b2f; op2val:0xfb2f;
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f20, f21, f19, dyn, 96, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x38c and fs2 == 1 and fe2 == 0x1d and fm2 == 0x38c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f18; op2:f20; dest:f19; op1val:0x778c; op2val:0xf78c;
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f19, f18, f20, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2f1 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x2f1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f19; op2:f17; dest:f18; op1val:0x76f1; op2val:0xf6f1;
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f18, f19, f17, dyn, 96, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x34c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x34c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f16; op2:f18; dest:f17; op1val:0x7b4c; op2val:0xfb4c;
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f17, f16, f18, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3a0 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3a0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f17; op2:f15; dest:f16; op1val:0x77a0; op2val:0xf7a0;
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f16, f17, f15, dyn, 96, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x02a and fs2 == 1 and fe2 == 0x1d and fm2 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f14; op2:f16; dest:f15; op1val:0x742a; op2val:0xf42a;
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f15, f14, f16, dyn, 96, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x063 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x063 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f15; op2:f13; dest:f14; op1val:0x7863; op2val:0xf863;
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f14, f15, f13, dyn, 96, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c1 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1c1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f12; op2:f14; dest:f13; op1val:0x79c1; op2val:0xf9c1;
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f13, f12, f14, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x298 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x298 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f13; op2:f11; dest:f12; op1val:0x7a98; op2val:0xfa98;
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f12, f13, f11, dyn, 96, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x15 and fm1 == 0x0bd and fs2 == 1 and fe2 == 0x15 and fm2 == 0x0bd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f10; op2:f12; dest:f11; op1val:0x54bd; op2val:0xd4bd;
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f11, f10, f12, dyn, 96, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ef and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f11; op2:f9; dest:f10; op1val:0x7aef; op2val:0xfaef;
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f10, f11, f9, dyn, 96, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x133 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f8; op2:f10; dest:f9; op1val:0x7533; op2val:0xf533;
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f9, f8, f10, dyn, 96, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x21c and fs2 == 1 and fe2 == 0x1c and fm2 == 0x21c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f9; op2:f7; dest:f8; op1val:0x721c; op2val:0xf21c;
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f8, f9, f7, dyn, 96, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:// rs1==f6, rs2==f8, rd==f7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x3a1 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3a1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f6; op2:f8; dest:f7; op1val:0x73a1; op2val:0xf3a1;
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f7, f6, f8, dyn, 96, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x26c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x26c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f7; op2:f5; dest:f6; op1val:0x7a6c; op2val:0xfa6c;
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f6, f7, f5, dyn, 96, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:// rs1==f4, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0x1b and fm1 == 0x125 and fs2 == 1 and fe2 == 0x1b and fm2 == 0x125 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f4; op2:f6; dest:f5; op1val:0x6d25; op2val:0xed25;
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f5, f4, f6, dyn, 96, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x00f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f5; op2:f3; dest:f4; op1val:0x780f; op2val:0xf80f;
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f4, f5, f3, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x1b and fm1 == 0x2fa and fs2 == 1 and fe2 == 0x1b and fm2 == 0x2fa and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f2; op2:f4; dest:f3; op1val:0x6efa; op2val:0xeefa;
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f3, f2, f4, dyn, 96, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:// rs1==f3, rs2==f1, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f3; op2:f1; dest:f2; op1val:0x79a6; op2val:0xf9a6;
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f2, f3, f1, dyn, 96, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x283 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x283 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f0; op2:f2; dest:f1; op1val:0x7a83; op2val:0xfa83;
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f1, f0, f2, dyn, 96, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:// rs1==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3b4 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f1; op2:f30; dest:f31; op1val:0x7bb4; op2val:0xfbb4;
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f1, f30, dyn, 96, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:// rs2==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b2 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0b2 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f0; dest:f31; op1val:0x78b2; op2val:0xf8b2;
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f0, dyn, 96, 0, x3, 64*FLEN/8, x4, x1, x2)
inst_33:// rd==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0c4 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0c4 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f31; op2:f30; dest:f0; op1val:0x78c4; op2val:0xf8c4;
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f0, f31, f30, dyn, 96, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x789a; op2val:0xf89a;
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 68*FLEN/8, x4, x1, x2)
inst_35:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1c and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x720e; op2val:0xf20e;
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 70*FLEN/8, x4, x1, x2)
inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x0e6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x78e6; op2val:0xf8e6;
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_37:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39e and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x779e; op2val:0xf79e;
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 74*FLEN/8, x4, x1, x2)
inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x20e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x20e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a0e; op2val:0xfa0e;
valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 76*FLEN/8, x4, x1, x2)
inst_39:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x362 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b62; op2val:0xfb62;
valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x32e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b2e; op2val:0xfb2e;
valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 80*FLEN/8, x4, x1, x2)
inst_41:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x052 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x052 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7852; op2val:0xf852;
valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 82*FLEN/8, x4, x1, x2)
inst_42:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a3 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x1a1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x79a3; op2val:0xf9a1;
valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x2)
inst_43:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x27d and fs2 == 1 and fe2 == 0x1e and fm2 == 0x27b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a7d; op2val:0xfa7b;
valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 86*FLEN/8, x4, x1, x2)
inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x328 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x326 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b28; op2val:0xfb26;
valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 88*FLEN/8, x4, x1, x2)
inst_45:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x398 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x396 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b98; op2val:0xfb96;
valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 90*FLEN/8, x4, x1, x2)
inst_46:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x334 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x330 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7734; op2val:0xf730;
valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 92*FLEN/8, x4, x1, x2)
inst_47:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3f5 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7bf7; op2val:0xfbf5;
valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 94*FLEN/8, x4, x1, x2)
inst_48:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x257 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x255 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a57; op2val:0xfa55;
valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 96*FLEN/8, x4, x1, x2)
inst_49:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x109 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x109 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7909; op2val:0xf909;
valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 98*FLEN/8, x4, x1, x2)
inst_50:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x3c6 and fs2 == 1 and fe2 == 0x1c and fm2 == 0x3c6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x73c6; op2val:0xf3c6;
valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 100*FLEN/8, x4, x1, x2)
inst_51:// fs1 == 0 and fe1 == 0x1b and fm1 == 0x37e and fs2 == 1 and fe2 == 0x1b and fm2 == 0x37e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x6f7e; op2val:0xef7e;
valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 102*FLEN/8, x4, x1, x2)
inst_52:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 1 and fe2 == 0x1e and fm2 == 0x25a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a5a; op2val:0xfa5a;
valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 104*FLEN/8, x4, x1, x2)
inst_53:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x286 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x286 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a86; op2val:0xfa86;
valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 106*FLEN/8, x4, x1, x2)
inst_54:// fs1 == 0 and fe1 == 0x1c and fm1 == 0x0ae and fs2 == 1 and fe2 == 0x1c and fm2 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x70ae; op2val:0xf0ae;
valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 108*FLEN/8, x4, x1, x2)
inst_55:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x2c0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x7ac0; op2val:0xfac0;
valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 110*FLEN/8, x4, x1, x2)
inst_56:// fs1 == 0 and fe1 == 0x1d and fm1 == 0x39f and fs2 == 1 and fe2 == 0x1d and fm2 == 0x39f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fadd.h ; op1:f30; op2:f29; dest:f31; op1val:0x779f; op2val:0xf79f;
valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.h, f31, f30, f29, dyn, 96, 0, x3, 112*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(30393,16,FLEN)
NAN_BOXED(63161,16,FLEN)
NAN_BOXED(30742,16,FLEN)
NAN_BOXED(63510,16,FLEN)
NAN_BOXED(31300,16,FLEN)
NAN_BOXED(64068,16,FLEN)
NAN_BOXED(30623,16,FLEN)
NAN_BOXED(30623,16,FLEN)
NAN_BOXED(31554,16,FLEN)
NAN_BOXED(64322,16,FLEN)
NAN_BOXED(29825,16,FLEN)
NAN_BOXED(62593,16,FLEN)
NAN_BOXED(30961,16,FLEN)
NAN_BOXED(63729,16,FLEN)
NAN_BOXED(31558,16,FLEN)
NAN_BOXED(64326,16,FLEN)
NAN_BOXED(31354,16,FLEN)
NAN_BOXED(64122,16,FLEN)
NAN_BOXED(29941,16,FLEN)
NAN_BOXED(62709,16,FLEN)
NAN_BOXED(31535,16,FLEN)
NAN_BOXED(64303,16,FLEN)
NAN_BOXED(30604,16,FLEN)
NAN_BOXED(63372,16,FLEN)
NAN_BOXED(30449,16,FLEN)
NAN_BOXED(63217,16,FLEN)
NAN_BOXED(31564,16,FLEN)
NAN_BOXED(64332,16,FLEN)
NAN_BOXED(30624,16,FLEN)
NAN_BOXED(63392,16,FLEN)
NAN_BOXED(29738,16,FLEN)
NAN_BOXED(62506,16,FLEN)
NAN_BOXED(30819,16,FLEN)
NAN_BOXED(63587,16,FLEN)
NAN_BOXED(31169,16,FLEN)
NAN_BOXED(63937,16,FLEN)
NAN_BOXED(31384,16,FLEN)
NAN_BOXED(64152,16,FLEN)
NAN_BOXED(21693,16,FLEN)
NAN_BOXED(54461,16,FLEN)
NAN_BOXED(31471,16,FLEN)
NAN_BOXED(64239,16,FLEN)
NAN_BOXED(30003,16,FLEN)
NAN_BOXED(62771,16,FLEN)
NAN_BOXED(29212,16,FLEN)
NAN_BOXED(61980,16,FLEN)
NAN_BOXED(29601,16,FLEN)
NAN_BOXED(62369,16,FLEN)
NAN_BOXED(31340,16,FLEN)
NAN_BOXED(64108,16,FLEN)
NAN_BOXED(27941,16,FLEN)
NAN_BOXED(60709,16,FLEN)
NAN_BOXED(30735,16,FLEN)
NAN_BOXED(63503,16,FLEN)
NAN_BOXED(28410,16,FLEN)
NAN_BOXED(61178,16,FLEN)
NAN_BOXED(31142,16,FLEN)
NAN_BOXED(63910,16,FLEN)
NAN_BOXED(31363,16,FLEN)
NAN_BOXED(64131,16,FLEN)
NAN_BOXED(31668,16,FLEN)
NAN_BOXED(64436,16,FLEN)
NAN_BOXED(30898,16,FLEN)
NAN_BOXED(63666,16,FLEN)
NAN_BOXED(30916,16,FLEN)
NAN_BOXED(63684,16,FLEN)
NAN_BOXED(30874,16,FLEN)
NAN_BOXED(63642,16,FLEN)
NAN_BOXED(29198,16,FLEN)
NAN_BOXED(61966,16,FLEN)
NAN_BOXED(30950,16,FLEN)
NAN_BOXED(63718,16,FLEN)
NAN_BOXED(30622,16,FLEN)
NAN_BOXED(63390,16,FLEN)
NAN_BOXED(31246,16,FLEN)
NAN_BOXED(64014,16,FLEN)
NAN_BOXED(31586,16,FLEN)
NAN_BOXED(64354,16,FLEN)
NAN_BOXED(31534,16,FLEN)
NAN_BOXED(64302,16,FLEN)
NAN_BOXED(30802,16,FLEN)
NAN_BOXED(63570,16,FLEN)
NAN_BOXED(31139,16,FLEN)
NAN_BOXED(63905,16,FLEN)
NAN_BOXED(31357,16,FLEN)
NAN_BOXED(64123,16,FLEN)
NAN_BOXED(31528,16,FLEN)
NAN_BOXED(64294,16,FLEN)
NAN_BOXED(31640,16,FLEN)
NAN_BOXED(64406,16,FLEN)
NAN_BOXED(30516,16,FLEN)
NAN_BOXED(63280,16,FLEN)
NAN_BOXED(31735,16,FLEN)
NAN_BOXED(64501,16,FLEN)
NAN_BOXED(31319,16,FLEN)
NAN_BOXED(64085,16,FLEN)
NAN_BOXED(30985,16,FLEN)
NAN_BOXED(63753,16,FLEN)
NAN_BOXED(29638,16,FLEN)
NAN_BOXED(62406,16,FLEN)
NAN_BOXED(28542,16,FLEN)
NAN_BOXED(61310,16,FLEN)
NAN_BOXED(31322,16,FLEN)
NAN_BOXED(64090,16,FLEN)
NAN_BOXED(31366,16,FLEN)
NAN_BOXED(64134,16,FLEN)
NAN_BOXED(28846,16,FLEN)
NAN_BOXED(61614,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(64192,16,FLEN)
NAN_BOXED(30623,16,FLEN)
NAN_BOXED(63391,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 114*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

14972
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fadd_b8-01.S
View file

File diff suppressed because it is too large Load diff

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fclass_b1-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Sat May 6 10:51:45 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fclass.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fclass.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fclass_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fclass_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f30; dest:x30; op1val:0x8000; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f28; dest:x28; op1val:0x8001; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f26; dest:x26; op1val:0x83fe; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f25; dest:x25; op1val:0x3ff; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f24; dest:x24; op1val:0x83ff; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f23; dest:x23; op1val:0x400; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f22; dest:x22; op1val:0x8400; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f21; dest:x21; op1val:0x401; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f20; dest:x20; op1val:0x8455; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f19; dest:x19; op1val:0x7bff; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f18; dest:x18; op1val:0xfbff; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f17; dest:x17; op1val:0x7c00; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f16; dest:x16; op1val:0xfc00; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f15; dest:x15; op1val:0x7e00; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f14; dest:x14; op1val:0xfe00; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f13; dest:x13; op1val:0x7e01; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f12; dest:x12; op1val:0xfe55; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f11; dest:x11; op1val:0x7c01; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f10; dest:x10; op1val:0xfd55; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f9; dest:x9; op1val:0x3c00; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0 and rs1_nan_prefix == 0xffff
/* opcode: fclass.h ; op1:f8; dest:x8; op1val:0xbc00; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,
/* opcode: fclass.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
inst_25:// rs1==f6, rd==x6,
/* opcode: fclass.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
inst_26:// rs1==f5, rd==x5,
/* opcode: fclass.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
val_offset:2*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,
/* opcode: fclass.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
val_offset:3*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
inst_28:// rs1==f3, rd==x3,
/* opcode: fclass.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
inst_29:// rs1==f2, rd==x2,
/* opcode: fclass.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
inst_30:// rs1==f1, rd==x1,
/* opcode: fclass.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
inst_31:// rs1==f0, rd==x0,
/* opcode: fclass.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.h, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(48128,16,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.w_b25-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:39:52 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.w.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.h.w instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.w_b25 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.w_b25)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f31, x31, dyn, 0, 0, x3, 0*4, x4, x1, x2,lw)
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f30, x30, dyn, 0, 0, x3, 1*4, x4, x1, x2,lw)
inst_2:// rs1==x29, rd==f29,rs1_val == -1 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x29; dest:f29; op1val:-0x1; valaddr_reg:x3;
val_offset:2*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f29, x29, dyn, 0, 0, x3, 2*4, x4, x1, x2,lw)
inst_3:// rs1==x28, rd==f28,rs1_val == 2147483647 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x28; dest:f28; op1val:0x7fffffff; valaddr_reg:x3;
val_offset:3*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f28, x28, dyn, 0, 0, x3, 3*4, x4, x1, x2,lw)
inst_4:// rs1==x27, rd==f27,rs1_val == -2147483647 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x27; dest:f27; op1val:-0x7fffffff; valaddr_reg:x3;
val_offset:4*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f27, x27, dyn, 0, 0, x3, 4*4, x4, x1, x2,lw)
inst_5:// rs1==x26, rd==f26,rs1_val == 1227077728 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x26; dest:f26; op1val:0x4923b860; valaddr_reg:x3;
val_offset:5*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f26, x26, dyn, 0, 0, x3, 5*4, x4, x1, x2,lw)
inst_6:// rs1==x25, rd==f25,rs1_val == -1227077728 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x25; dest:f25; op1val:-0x4923b860; valaddr_reg:x3;
val_offset:6*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f25, x25, dyn, 0, 0, x3, 6*4, x4, x1, x2,lw)
inst_7:// rs1==x24, rd==f24,
/* opcode: fcvt.h.w ; op1:x24; dest:f24; op1val:0x0; valaddr_reg:x3;
val_offset:7*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f24, x24, dyn, 0, 0, x3, 7*4, x4, x1, x2,lw)
inst_8:// rs1==x23, rd==f23,
/* opcode: fcvt.h.w ; op1:x23; dest:f23; op1val:0x0; valaddr_reg:x3;
val_offset:8*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f23, x23, dyn, 0, 0, x3, 8*4, x4, x1, x2,lw)
inst_9:// rs1==x22, rd==f22,
/* opcode: fcvt.h.w ; op1:x22; dest:f22; op1val:0x0; valaddr_reg:x3;
val_offset:9*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f22, x22, dyn, 0, 0, x3, 9*4, x4, x1, x2,lw)
inst_10:// rs1==x21, rd==f21,
/* opcode: fcvt.h.w ; op1:x21; dest:f21; op1val:0x0; valaddr_reg:x3;
val_offset:10*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f21, x21, dyn, 0, 0, x3, 10*4, x4, x1, x2,lw)
inst_11:// rs1==x20, rd==f20,
/* opcode: fcvt.h.w ; op1:x20; dest:f20; op1val:0x0; valaddr_reg:x3;
val_offset:11*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f20, x20, dyn, 0, 0, x3, 11*4, x4, x1, x2,lw)
inst_12:// rs1==x19, rd==f19,
/* opcode: fcvt.h.w ; op1:x19; dest:f19; op1val:0x0; valaddr_reg:x3;
val_offset:12*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f19, x19, dyn, 0, 0, x3, 12*4, x4, x1, x2,lw)
inst_13:// rs1==x18, rd==f18,
/* opcode: fcvt.h.w ; op1:x18; dest:f18; op1val:0x0; valaddr_reg:x3;
val_offset:13*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f18, x18, dyn, 0, 0, x3, 13*4, x4, x1, x2,lw)
inst_14:// rs1==x17, rd==f17,
/* opcode: fcvt.h.w ; op1:x17; dest:f17; op1val:0x0; valaddr_reg:x3;
val_offset:14*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f17, x17, dyn, 0, 0, x3, 14*4, x4, x1, x2,lw)
inst_15:// rs1==x16, rd==f16,
/* opcode: fcvt.h.w ; op1:x16; dest:f16; op1val:0x0; valaddr_reg:x3;
val_offset:15*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f16, x16, dyn, 0, 0, x3, 15*4, x4, x1, x2,lw)
inst_16:// rs1==x15, rd==f15,
/* opcode: fcvt.h.w ; op1:x15; dest:f15; op1val:0x0; valaddr_reg:x3;
val_offset:16*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f15, x15, dyn, 0, 0, x3, 16*4, x4, x1, x2,lw)
inst_17:// rs1==x14, rd==f14,
/* opcode: fcvt.h.w ; op1:x14; dest:f14; op1val:0x0; valaddr_reg:x3;
val_offset:17*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f14, x14, dyn, 0, 0, x3, 17*4, x4, x1, x2,lw)
inst_18:// rs1==x13, rd==f13,
/* opcode: fcvt.h.w ; op1:x13; dest:f13; op1val:0x0; valaddr_reg:x3;
val_offset:18*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f13, x13, dyn, 0, 0, x3, 18*4, x4, x1, x2,lw)
inst_19:// rs1==x12, rd==f12,
/* opcode: fcvt.h.w ; op1:x12; dest:f12; op1val:0x0; valaddr_reg:x3;
val_offset:19*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f12, x12, dyn, 0, 0, x3, 19*4, x4, x1, x2,lw)
inst_20:// rs1==x11, rd==f11,
/* opcode: fcvt.h.w ; op1:x11; dest:f11; op1val:0x0; valaddr_reg:x3;
val_offset:20*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f11, x11, dyn, 0, 0, x3, 20*4, x4, x1, x2,lw)
inst_21:// rs1==x10, rd==f10,
/* opcode: fcvt.h.w ; op1:x10; dest:f10; op1val:0x0; valaddr_reg:x3;
val_offset:21*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f10, x10, dyn, 0, 0, x3, 21*4, x4, x1, x2,lw)
inst_22:// rs1==x9, rd==f9,
/* opcode: fcvt.h.w ; op1:x9; dest:f9; op1val:0x0; valaddr_reg:x3;
val_offset:22*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f9, x9, dyn, 0, 0, x3, 22*4, x4, x1, x2,lw)
inst_23:// rs1==x8, rd==f8,
/* opcode: fcvt.h.w ; op1:x8; dest:f8; op1val:0x0; valaddr_reg:x3;
val_offset:23*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f8, x8, dyn, 0, 0, x3, 23*4, x4, x1, x2,lw)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==x7, rd==f7,
/* opcode: fcvt.h.w ; op1:x7; dest:f7; op1val:0x0; valaddr_reg:x8;
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f7, x7, dyn, 0, 0, x8, 0*4, x9, x1, x2,lw)
inst_25:// rs1==x6, rd==f6,
/* opcode: fcvt.h.w ; op1:x6; dest:f6; op1val:0x0; valaddr_reg:x8;
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f6, x6, dyn, 0, 0, x8, 1*4, x9, x1, x2,lw)
inst_26:// rs1==x5, rd==f5,
/* opcode: fcvt.h.w ; op1:x5; dest:f5; op1val:0x0; valaddr_reg:x8;
val_offset:2*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f5, x5, dyn, 0, 0, x8, 2*4, x9, x1, x6,lw)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==x4, rd==f4,
/* opcode: fcvt.h.w ; op1:x4; dest:f4; op1val:0x0; valaddr_reg:x8;
val_offset:3*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f4, x4, dyn, 0, 0, x8, 3*4, x9, x5, x6,lw)
inst_28:// rs1==x3, rd==f3,
/* opcode: fcvt.h.w ; op1:x3; dest:f3; op1val:0x0; valaddr_reg:x8;
val_offset:4*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f3, x3, dyn, 0, 0, x8, 4*4, x9, x5, x6,lw)
inst_29:// rs1==x2, rd==f2,
/* opcode: fcvt.h.w ; op1:x2; dest:f2; op1val:0x0; valaddr_reg:x8;
val_offset:5*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f2, x2, dyn, 0, 0, x8, 5*4, x9, x5, x6,lw)
inst_30:// rs1==x1, rd==f1,
/* opcode: fcvt.h.w ; op1:x1; dest:f1; op1val:0x0; valaddr_reg:x8;
val_offset:6*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f1, x1, dyn, 0, 0, x8, 6*4, x9, x5, x6,lw)
inst_31:// rs1==x0, rd==f0,
/* opcode: fcvt.h.w ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
val_offset:7*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f0, x0, dyn, 0, 0, x8, 7*4, x9, x5, x6,lw)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.word 0;
.word 1;
.word -1;
.word 2147483647;
.word -2147483647;
.word 1227077728;
.word -1227077728;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
test_dataset_1:
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

327
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.w_b26-01.S
View file

@ -1,327 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:39:52 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.w.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.h.w instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.w_b26 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.w_b26)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f31, x31, dyn, 0, 0, x3, 0*4, x4, x1, x2,lw)
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f30, x30, dyn, 0, 0, x3, 1*4, x4, x1, x2,lw)
inst_2:// rs1==x29, rd==f29,rs1_val == 2 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x29; dest:f29; op1val:0x2; valaddr_reg:x3;
val_offset:2*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f29, x29, dyn, 0, 0, x3, 2*4, x4, x1, x2,lw)
inst_3:// rs1==x28, rd==f28,rs1_val == 7 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x28; dest:f28; op1val:0x7; valaddr_reg:x3;
val_offset:3*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f28, x28, dyn, 0, 0, x3, 3*4, x4, x1, x2,lw)
inst_4:// rs1==x27, rd==f27,rs1_val == 15 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x27; dest:f27; op1val:0xf; valaddr_reg:x3;
val_offset:4*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f27, x27, dyn, 0, 0, x3, 4*4, x4, x1, x2,lw)
inst_5:// rs1==x26, rd==f26,rs1_val == 16 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x26; dest:f26; op1val:0x10; valaddr_reg:x3;
val_offset:5*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f26, x26, dyn, 0, 0, x3, 5*4, x4, x1, x2,lw)
inst_6:// rs1==x25, rd==f25,rs1_val == 45 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x25; dest:f25; op1val:0x2d; valaddr_reg:x3;
val_offset:6*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f25, x25, dyn, 0, 0, x3, 6*4, x4, x1, x2,lw)
inst_7:// rs1==x24, rd==f24,rs1_val == 123 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x24; dest:f24; op1val:0x7b; valaddr_reg:x3;
val_offset:7*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f24, x24, dyn, 0, 0, x3, 7*4, x4, x1, x2,lw)
inst_8:// rs1==x23, rd==f23,rs1_val == 253 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x23; dest:f23; op1val:0xfd; valaddr_reg:x3;
val_offset:8*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f23, x23, dyn, 0, 0, x3, 8*4, x4, x1, x2,lw)
inst_9:// rs1==x22, rd==f22,rs1_val == 398 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x22; dest:f22; op1val:0x18e; valaddr_reg:x3;
val_offset:9*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f22, x22, dyn, 0, 0, x3, 9*4, x4, x1, x2,lw)
inst_10:// rs1==x21, rd==f21,rs1_val == 676 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x21; dest:f21; op1val:0x2a4; valaddr_reg:x3;
val_offset:10*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f21, x21, dyn, 0, 0, x3, 10*4, x4, x1, x2,lw)
inst_11:// rs1==x20, rd==f20,rs1_val == 1094 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x20; dest:f20; op1val:0x446; valaddr_reg:x3;
val_offset:11*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f20, x20, dyn, 0, 0, x3, 11*4, x4, x1, x2,lw)
inst_12:// rs1==x19, rd==f19,rs1_val == 4055 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x19; dest:f19; op1val:0xfd7; valaddr_reg:x3;
val_offset:12*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f19, x19, dyn, 0, 0, x3, 12*4, x4, x1, x2,lw)
inst_13:// rs1==x18, rd==f18,rs1_val == 6781 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x18; dest:f18; op1val:0x1a7d; valaddr_reg:x3;
val_offset:13*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f18, x18, dyn, 0, 0, x3, 13*4, x4, x1, x2,lw)
inst_14:// rs1==x17, rd==f17,rs1_val == 9438 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x17; dest:f17; op1val:0x24de; valaddr_reg:x3;
val_offset:14*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f17, x17, dyn, 0, 0, x3, 14*4, x4, x1, x2,lw)
inst_15:// rs1==x16, rd==f16,rs1_val == 24575 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x16; dest:f16; op1val:0x5fff; valaddr_reg:x3;
val_offset:15*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f16, x16, dyn, 0, 0, x3, 15*4, x4, x1, x2,lw)
inst_16:// rs1==x15, rd==f15,rs1_val == 56436 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x15; dest:f15; op1val:0xdc74; valaddr_reg:x3;
val_offset:16*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f15, x15, dyn, 0, 0, x3, 16*4, x4, x1, x2,lw)
inst_17:// rs1==x14, rd==f14,rs1_val == 71376 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x14; dest:f14; op1val:0x116d0; valaddr_reg:x3;
val_offset:17*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f14, x14, dyn, 0, 0, x3, 17*4, x4, x1, x2,lw)
inst_18:// rs1==x13, rd==f13,rs1_val == 241276 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x13; dest:f13; op1val:0x3ae7c; valaddr_reg:x3;
val_offset:18*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f13, x13, dyn, 0, 0, x3, 18*4, x4, x1, x2,lw)
inst_19:// rs1==x12, rd==f12,rs1_val == 334857 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x12; dest:f12; op1val:0x51c09; valaddr_reg:x3;
val_offset:19*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f12, x12, dyn, 0, 0, x3, 19*4, x4, x1, x2,lw)
inst_20:// rs1==x11, rd==f11,rs1_val == 896618 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x11; dest:f11; op1val:0xdae6a; valaddr_reg:x3;
val_offset:20*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f11, x11, dyn, 0, 0, x3, 20*4, x4, x1, x2,lw)
inst_21:// rs1==x10, rd==f10,rs1_val == 1848861 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x10; dest:f10; op1val:0x1c361d; valaddr_reg:x3;
val_offset:21*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f10, x10, dyn, 0, 0, x3, 21*4, x4, x1, x2,lw)
inst_22:// rs1==x9, rd==f9,rs1_val == 3864061 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x9; dest:f9; op1val:0x3af5fd; valaddr_reg:x3;
val_offset:22*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f9, x9, dyn, 0, 0, x3, 22*4, x4, x1, x2,lw)
inst_23:// rs1==x8, rd==f8,rs1_val == 6573466 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x8; dest:f8; op1val:0x644d9a; valaddr_reg:x3;
val_offset:23*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f8, x8, dyn, 0, 0, x3, 23*4, x4, x1, x2,lw)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==x7, rd==f7,rs1_val == 12789625 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x7; dest:f7; op1val:0xc32779; valaddr_reg:x8;
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f7, x7, dyn, 0, 0, x8, 0*4, x9, x1, x2,lw)
inst_25:// rs1==x6, rd==f6,rs1_val == 32105925 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x6; dest:f6; op1val:0x1e9e5c5; valaddr_reg:x8;
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f6, x6, dyn, 0, 0, x8, 1*4, x9, x1, x2,lw)
inst_26:// rs1==x5, rd==f5,rs1_val == 45276376 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x5; dest:f5; op1val:0x2b2dcd8; valaddr_reg:x8;
val_offset:2*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f5, x5, dyn, 0, 0, x8, 2*4, x9, x1, x6,lw)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==x4, rd==f4,rs1_val == 107790943 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x4; dest:f4; op1val:0x66cc25f; valaddr_reg:x8;
val_offset:3*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f4, x4, dyn, 0, 0, x8, 3*4, x9, x5, x6,lw)
inst_28:// rs1==x3, rd==f3,rs1_val == 231549045 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x3; dest:f3; op1val:0xdcd2875; valaddr_reg:x8;
val_offset:4*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f3, x3, dyn, 0, 0, x8, 4*4, x9, x5, x6,lw)
inst_29:// rs1==x2, rd==f2,rs1_val == 339827553 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x2; dest:f2; op1val:0x14415b61; valaddr_reg:x8;
val_offset:5*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f2, x2, dyn, 0, 0, x8, 5*4, x9, x5, x6,lw)
inst_30:// rs1==x1, rd==f1,rs1_val == 1027494066 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x1; dest:f1; op1val:0x3d3e50b2; valaddr_reg:x8;
val_offset:6*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f1, x1, dyn, 0, 0, x8, 6*4, x9, x5, x6,lw)
inst_31:// rs1==x0, rd==f0,rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
val_offset:7*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f0, x0, dyn, 0, 0, x8, 7*4, x9, x5, x6,lw)
inst_32:// rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.w ; op1:x31; dest:f31; op1val:0x5ea40361; valaddr_reg:x8;
val_offset:8*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.w, f31, x31, dyn, 0, 0, x8, 8*4, x9, x5, x6,lw)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.word 0;
.word 1;
.word 2;
.word 7;
.word 15;
.word 16;
.word 45;
.word 123;
.word 253;
.word 398;
.word 676;
.word 1094;
.word 4055;
.word 6781;
.word 9438;
.word 24575;
.word 56436;
.word 71376;
.word 241276;
.word 334857;
.word 896618;
.word 1848861;
.word 3864061;
.word 6573466;
test_dataset_1:
.word 12789625;
.word 32105925;
.word 45276376;
.word 107790943;
.word 231549045;
.word 339827553;
.word 1027494066;
.word 0;
.word 1587807073;
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 12*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.wu_b25-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:07 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.wu.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.h.wu instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.wu_b25 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.wu_b25)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f31, x31, dyn, 0, 0, x3, 0*4, x4, x1, x2,LREGWU)
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f30, x30, dyn, 0, 0, x3, 1*4, x4, x1, x2,LREGWU)
inst_2:// rs1==x29, rd==f29,rs1_val == 4294967295 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x29; dest:f29; op1val:0xffffffff; valaddr_reg:x3;
val_offset:2*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f29, x29, dyn, 0, 0, x3, 2*4, x4, x1, x2,LREGWU)
inst_3:// rs1==x28, rd==f28,rs1_val == 2454155456 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x28; dest:f28; op1val:0x924770c0; valaddr_reg:x3;
val_offset:3*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f28, x28, dyn, 0, 0, x3, 3*4, x4, x1, x2,LREGWU)
inst_4:// rs1==x27, rd==f27,
/* opcode: fcvt.h.wu ; op1:x27; dest:f27; op1val:0x0; valaddr_reg:x3;
val_offset:4*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f27, x27, dyn, 0, 0, x3, 4*4, x4, x1, x2,LREGWU)
inst_5:// rs1==x26, rd==f26,
/* opcode: fcvt.h.wu ; op1:x26; dest:f26; op1val:0x0; valaddr_reg:x3;
val_offset:5*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f26, x26, dyn, 0, 0, x3, 5*4, x4, x1, x2,LREGWU)
inst_6:// rs1==x25, rd==f25,
/* opcode: fcvt.h.wu ; op1:x25; dest:f25; op1val:0x0; valaddr_reg:x3;
val_offset:6*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f25, x25, dyn, 0, 0, x3, 6*4, x4, x1, x2,LREGWU)
inst_7:// rs1==x24, rd==f24,
/* opcode: fcvt.h.wu ; op1:x24; dest:f24; op1val:0x0; valaddr_reg:x3;
val_offset:7*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f24, x24, dyn, 0, 0, x3, 7*4, x4, x1, x2,LREGWU)
inst_8:// rs1==x23, rd==f23,
/* opcode: fcvt.h.wu ; op1:x23; dest:f23; op1val:0x0; valaddr_reg:x3;
val_offset:8*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f23, x23, dyn, 0, 0, x3, 8*4, x4, x1, x2,LREGWU)
inst_9:// rs1==x22, rd==f22,
/* opcode: fcvt.h.wu ; op1:x22; dest:f22; op1val:0x0; valaddr_reg:x3;
val_offset:9*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f22, x22, dyn, 0, 0, x3, 9*4, x4, x1, x2,LREGWU)
inst_10:// rs1==x21, rd==f21,
/* opcode: fcvt.h.wu ; op1:x21; dest:f21; op1val:0x0; valaddr_reg:x3;
val_offset:10*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f21, x21, dyn, 0, 0, x3, 10*4, x4, x1, x2,LREGWU)
inst_11:// rs1==x20, rd==f20,
/* opcode: fcvt.h.wu ; op1:x20; dest:f20; op1val:0x0; valaddr_reg:x3;
val_offset:11*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f20, x20, dyn, 0, 0, x3, 11*4, x4, x1, x2,LREGWU)
inst_12:// rs1==x19, rd==f19,
/* opcode: fcvt.h.wu ; op1:x19; dest:f19; op1val:0x0; valaddr_reg:x3;
val_offset:12*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f19, x19, dyn, 0, 0, x3, 12*4, x4, x1, x2,LREGWU)
inst_13:// rs1==x18, rd==f18,
/* opcode: fcvt.h.wu ; op1:x18; dest:f18; op1val:0x0; valaddr_reg:x3;
val_offset:13*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f18, x18, dyn, 0, 0, x3, 13*4, x4, x1, x2,LREGWU)
inst_14:// rs1==x17, rd==f17,
/* opcode: fcvt.h.wu ; op1:x17; dest:f17; op1val:0x0; valaddr_reg:x3;
val_offset:14*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f17, x17, dyn, 0, 0, x3, 14*4, x4, x1, x2,LREGWU)
inst_15:// rs1==x16, rd==f16,
/* opcode: fcvt.h.wu ; op1:x16; dest:f16; op1val:0x0; valaddr_reg:x3;
val_offset:15*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f16, x16, dyn, 0, 0, x3, 15*4, x4, x1, x2,LREGWU)
inst_16:// rs1==x15, rd==f15,
/* opcode: fcvt.h.wu ; op1:x15; dest:f15; op1val:0x0; valaddr_reg:x3;
val_offset:16*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f15, x15, dyn, 0, 0, x3, 16*4, x4, x1, x2,LREGWU)
inst_17:// rs1==x14, rd==f14,
/* opcode: fcvt.h.wu ; op1:x14; dest:f14; op1val:0x0; valaddr_reg:x3;
val_offset:17*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f14, x14, dyn, 0, 0, x3, 17*4, x4, x1, x2,LREGWU)
inst_18:// rs1==x13, rd==f13,
/* opcode: fcvt.h.wu ; op1:x13; dest:f13; op1val:0x0; valaddr_reg:x3;
val_offset:18*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f13, x13, dyn, 0, 0, x3, 18*4, x4, x1, x2,LREGWU)
inst_19:// rs1==x12, rd==f12,
/* opcode: fcvt.h.wu ; op1:x12; dest:f12; op1val:0x0; valaddr_reg:x3;
val_offset:19*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f12, x12, dyn, 0, 0, x3, 19*4, x4, x1, x2,LREGWU)
inst_20:// rs1==x11, rd==f11,
/* opcode: fcvt.h.wu ; op1:x11; dest:f11; op1val:0x0; valaddr_reg:x3;
val_offset:20*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f11, x11, dyn, 0, 0, x3, 20*4, x4, x1, x2,LREGWU)
inst_21:// rs1==x10, rd==f10,
/* opcode: fcvt.h.wu ; op1:x10; dest:f10; op1val:0x0; valaddr_reg:x3;
val_offset:21*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f10, x10, dyn, 0, 0, x3, 21*4, x4, x1, x2,LREGWU)
inst_22:// rs1==x9, rd==f9,
/* opcode: fcvt.h.wu ; op1:x9; dest:f9; op1val:0x0; valaddr_reg:x3;
val_offset:22*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f9, x9, dyn, 0, 0, x3, 22*4, x4, x1, x2,LREGWU)
inst_23:// rs1==x8, rd==f8,
/* opcode: fcvt.h.wu ; op1:x8; dest:f8; op1val:0x0; valaddr_reg:x3;
val_offset:23*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f8, x8, dyn, 0, 0, x3, 23*4, x4, x1, x2,LREGWU)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==x7, rd==f7,
/* opcode: fcvt.h.wu ; op1:x7; dest:f7; op1val:0x0; valaddr_reg:x8;
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f7, x7, dyn, 0, 0, x8, 0*4, x9, x1, x2,LREGWU)
inst_25:// rs1==x6, rd==f6,
/* opcode: fcvt.h.wu ; op1:x6; dest:f6; op1val:0x0; valaddr_reg:x8;
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f6, x6, dyn, 0, 0, x8, 1*4, x9, x1, x2,LREGWU)
inst_26:// rs1==x5, rd==f5,
/* opcode: fcvt.h.wu ; op1:x5; dest:f5; op1val:0x0; valaddr_reg:x8;
val_offset:2*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f5, x5, dyn, 0, 0, x8, 2*4, x9, x1, x6,LREGWU)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==x4, rd==f4,
/* opcode: fcvt.h.wu ; op1:x4; dest:f4; op1val:0x0; valaddr_reg:x8;
val_offset:3*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f4, x4, dyn, 0, 0, x8, 3*4, x9, x5, x6,LREGWU)
inst_28:// rs1==x3, rd==f3,
/* opcode: fcvt.h.wu ; op1:x3; dest:f3; op1val:0x0; valaddr_reg:x8;
val_offset:4*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f3, x3, dyn, 0, 0, x8, 4*4, x9, x5, x6,LREGWU)
inst_29:// rs1==x2, rd==f2,
/* opcode: fcvt.h.wu ; op1:x2; dest:f2; op1val:0x0; valaddr_reg:x8;
val_offset:5*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f2, x2, dyn, 0, 0, x8, 5*4, x9, x5, x6,LREGWU)
inst_30:// rs1==x1, rd==f1,
/* opcode: fcvt.h.wu ; op1:x1; dest:f1; op1val:0x0; valaddr_reg:x8;
val_offset:6*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f1, x1, dyn, 0, 0, x8, 6*4, x9, x5, x6,LREGWU)
inst_31:// rs1==x0, rd==f0,
/* opcode: fcvt.h.wu ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
val_offset:7*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f0, x0, dyn, 0, 0, x8, 7*4, x9, x5, x6,LREGWU)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.word 0;
.word 1;
.word 4294967295;
.word 2454155456;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
test_dataset_1:
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

327
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.h.wu_b26-01.S
View file

@ -1,327 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:07 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.h.wu.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.h.wu instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.h.wu_b26 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.h.wu_b26)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f31, x31, dyn, 0, 0, x3, 0*4, x4, x1, x2,LREGWU)
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f30, x30, dyn, 0, 0, x3, 1*4, x4, x1, x2,LREGWU)
inst_2:// rs1==x29, rd==f29,rs1_val == 2 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x29; dest:f29; op1val:0x2; valaddr_reg:x3;
val_offset:2*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f29, x29, dyn, 0, 0, x3, 2*4, x4, x1, x2,LREGWU)
inst_3:// rs1==x28, rd==f28,rs1_val == 7 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x28; dest:f28; op1val:0x7; valaddr_reg:x3;
val_offset:3*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f28, x28, dyn, 0, 0, x3, 3*4, x4, x1, x2,LREGWU)
inst_4:// rs1==x27, rd==f27,rs1_val == 15 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x27; dest:f27; op1val:0xf; valaddr_reg:x3;
val_offset:4*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f27, x27, dyn, 0, 0, x3, 4*4, x4, x1, x2,LREGWU)
inst_5:// rs1==x26, rd==f26,rs1_val == 16 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x26; dest:f26; op1val:0x10; valaddr_reg:x3;
val_offset:5*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f26, x26, dyn, 0, 0, x3, 5*4, x4, x1, x2,LREGWU)
inst_6:// rs1==x25, rd==f25,rs1_val == 45 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x25; dest:f25; op1val:0x2d; valaddr_reg:x3;
val_offset:6*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f25, x25, dyn, 0, 0, x3, 6*4, x4, x1, x2,LREGWU)
inst_7:// rs1==x24, rd==f24,rs1_val == 123 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x24; dest:f24; op1val:0x7b; valaddr_reg:x3;
val_offset:7*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f24, x24, dyn, 0, 0, x3, 7*4, x4, x1, x2,LREGWU)
inst_8:// rs1==x23, rd==f23,rs1_val == 253 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x23; dest:f23; op1val:0xfd; valaddr_reg:x3;
val_offset:8*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f23, x23, dyn, 0, 0, x3, 8*4, x4, x1, x2,LREGWU)
inst_9:// rs1==x22, rd==f22,rs1_val == 398 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x22; dest:f22; op1val:0x18e; valaddr_reg:x3;
val_offset:9*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f22, x22, dyn, 0, 0, x3, 9*4, x4, x1, x2,LREGWU)
inst_10:// rs1==x21, rd==f21,rs1_val == 676 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x21; dest:f21; op1val:0x2a4; valaddr_reg:x3;
val_offset:10*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f21, x21, dyn, 0, 0, x3, 10*4, x4, x1, x2,LREGWU)
inst_11:// rs1==x20, rd==f20,rs1_val == 1094 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x20; dest:f20; op1val:0x446; valaddr_reg:x3;
val_offset:11*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f20, x20, dyn, 0, 0, x3, 11*4, x4, x1, x2,LREGWU)
inst_12:// rs1==x19, rd==f19,rs1_val == 4055 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x19; dest:f19; op1val:0xfd7; valaddr_reg:x3;
val_offset:12*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f19, x19, dyn, 0, 0, x3, 12*4, x4, x1, x2,LREGWU)
inst_13:// rs1==x18, rd==f18,rs1_val == 6781 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x18; dest:f18; op1val:0x1a7d; valaddr_reg:x3;
val_offset:13*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f18, x18, dyn, 0, 0, x3, 13*4, x4, x1, x2,LREGWU)
inst_14:// rs1==x17, rd==f17,rs1_val == 9438 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x17; dest:f17; op1val:0x24de; valaddr_reg:x3;
val_offset:14*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f17, x17, dyn, 0, 0, x3, 14*4, x4, x1, x2,LREGWU)
inst_15:// rs1==x16, rd==f16,rs1_val == 24575 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x16; dest:f16; op1val:0x5fff; valaddr_reg:x3;
val_offset:15*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f16, x16, dyn, 0, 0, x3, 15*4, x4, x1, x2,LREGWU)
inst_16:// rs1==x15, rd==f15,rs1_val == 56436 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x15; dest:f15; op1val:0xdc74; valaddr_reg:x3;
val_offset:16*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f15, x15, dyn, 0, 0, x3, 16*4, x4, x1, x2,LREGWU)
inst_17:// rs1==x14, rd==f14,rs1_val == 71376 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x14; dest:f14; op1val:0x116d0; valaddr_reg:x3;
val_offset:17*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f14, x14, dyn, 0, 0, x3, 17*4, x4, x1, x2,LREGWU)
inst_18:// rs1==x13, rd==f13,rs1_val == 241276 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x13; dest:f13; op1val:0x3ae7c; valaddr_reg:x3;
val_offset:18*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f13, x13, dyn, 0, 0, x3, 18*4, x4, x1, x2,LREGWU)
inst_19:// rs1==x12, rd==f12,rs1_val == 334857 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x12; dest:f12; op1val:0x51c09; valaddr_reg:x3;
val_offset:19*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f12, x12, dyn, 0, 0, x3, 19*4, x4, x1, x2,LREGWU)
inst_20:// rs1==x11, rd==f11,rs1_val == 896618 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x11; dest:f11; op1val:0xdae6a; valaddr_reg:x3;
val_offset:20*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f11, x11, dyn, 0, 0, x3, 20*4, x4, x1, x2,LREGWU)
inst_21:// rs1==x10, rd==f10,rs1_val == 1848861 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x10; dest:f10; op1val:0x1c361d; valaddr_reg:x3;
val_offset:21*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f10, x10, dyn, 0, 0, x3, 21*4, x4, x1, x2,LREGWU)
inst_22:// rs1==x9, rd==f9,rs1_val == 3864061 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x9; dest:f9; op1val:0x3af5fd; valaddr_reg:x3;
val_offset:22*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f9, x9, dyn, 0, 0, x3, 22*4, x4, x1, x2,LREGWU)
inst_23:// rs1==x8, rd==f8,rs1_val == 6573466 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x8; dest:f8; op1val:0x644d9a; valaddr_reg:x3;
val_offset:23*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f8, x8, dyn, 0, 0, x3, 23*4, x4, x1, x2,LREGWU)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==x7, rd==f7,rs1_val == 12789625 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x7; dest:f7; op1val:0xc32779; valaddr_reg:x8;
val_offset:0*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f7, x7, dyn, 0, 0, x8, 0*4, x9, x1, x2,LREGWU)
inst_25:// rs1==x6, rd==f6,rs1_val == 32105925 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x6; dest:f6; op1val:0x1e9e5c5; valaddr_reg:x8;
val_offset:1*4; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f6, x6, dyn, 0, 0, x8, 1*4, x9, x1, x2,LREGWU)
inst_26:// rs1==x5, rd==f5,rs1_val == 45276376 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x5; dest:f5; op1val:0x2b2dcd8; valaddr_reg:x8;
val_offset:2*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f5, x5, dyn, 0, 0, x8, 2*4, x9, x1, x6,LREGWU)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==x4, rd==f4,rs1_val == 107790943 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x4; dest:f4; op1val:0x66cc25f; valaddr_reg:x8;
val_offset:3*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f4, x4, dyn, 0, 0, x8, 3*4, x9, x5, x6,LREGWU)
inst_28:// rs1==x3, rd==f3,rs1_val == 231549045 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x3; dest:f3; op1val:0xdcd2875; valaddr_reg:x8;
val_offset:4*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f3, x3, dyn, 0, 0, x8, 4*4, x9, x5, x6,LREGWU)
inst_29:// rs1==x2, rd==f2,rs1_val == 339827553 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x2; dest:f2; op1val:0x14415b61; valaddr_reg:x8;
val_offset:5*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f2, x2, dyn, 0, 0, x8, 5*4, x9, x5, x6,LREGWU)
inst_30:// rs1==x1, rd==f1,rs1_val == 1027494066 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x1; dest:f1; op1val:0x3d3e50b2; valaddr_reg:x8;
val_offset:6*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f1, x1, dyn, 0, 0, x8, 6*4, x9, x5, x6,LREGWU)
inst_31:// rs1==x0, rd==f0,rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
val_offset:7*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f0, x0, dyn, 0, 0, x8, 7*4, x9, x5, x6,LREGWU)
inst_32:// rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.h.wu ; op1:x31; dest:f31; op1val:0x5ea40361; valaddr_reg:x8;
val_offset:8*4; rmval:dyn; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP(fcvt.h.wu, f31, x31, dyn, 0, 0, x8, 8*4, x9, x5, x6,LREGWU)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.word 0;
.word 1;
.word 2;
.word 7;
.word 15;
.word 16;
.word 45;
.word 123;
.word 253;
.word 398;
.word 676;
.word 1094;
.word 4055;
.word 6781;
.word 9438;
.word 24575;
.word 56436;
.word 71376;
.word 241276;
.word 334857;
.word 896618;
.word 1848861;
.word 3864061;
.word 6573466;
test_dataset_1:
.word 12789625;
.word 32105925;
.word 45276376;
.word 107790943;
.word 231549045;
.word 339827553;
.word 1027494066;
.word 0;
.word 1587807073;
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 12*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.w.h_b1-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:30 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x8000; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x8001; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x83fe; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x3ff; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x83ff; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x400; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x8400; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x401; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x8455; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x7bff; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0xfbff; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x7c00; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0xfc00; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x7e00; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xfe00; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x7e01; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0xfe55; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x7c01; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0xfd55; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x3c00; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0xbc00; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(48128,16,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

383
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.w.h_b22-01.S
View file

@ -1,383 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:30 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b22 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b22)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3249; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x35b7; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x3a4f; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x3cd3; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x4340; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x474b; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x12 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0xca9d; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x13 and fm1 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x4ca4; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x5215; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x15 and fm1 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x554f; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,fs1 == 1 and fe1 == 0x16 and fm1 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0xd8ff; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x17 and fm1 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0xdfcf; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x18 and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x63fc; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x19 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x642d; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1a and fm1 == 0x370 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x6b70; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x1b and fm1 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x6e69; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x7186; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1d and fm1 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xf522; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x7ab3; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0x7bff; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x00 and fm1 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x82be; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x01 and fm1 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x86a5; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x02 and fm1 == 0x088 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x8888; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x03 and fm1 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x8f12; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x04 and fm1 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x93ed; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x05 and fm1 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x97e0; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x06 and fm1 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x9a74; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x07 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x9c2d; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,fs1 == 1 and fe1 == 0x08 and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0xa004; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,fs1 == 1 and fe1 == 0x09 and fm1 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0xa489; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x0a and fm1 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0xabc3; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0xad36; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
inst_32:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x176 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb176; valaddr_reg:x8;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
inst_33:// fs1 == 1 and fe1 == 0x0d and fm1 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb797; valaddr_reg:x8;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
inst_34:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb941; valaddr_reg:x8;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbe32; valaddr_reg:x8;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
inst_36:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xc1be; valaddr_reg:x8;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
inst_37:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xc442; valaddr_reg:x8;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
inst_38:// fs1 == 1 and fe1 == 0x09 and fm1 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa656; valaddr_reg:x8;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
inst_39:// fs1 == 1 and fe1 == 0x16 and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xda01; valaddr_reg:x8;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
inst_40:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xad36; valaddr_reg:x8;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(12873,16,FLEN)
NAN_BOXED(13751,16,FLEN)
NAN_BOXED(14927,16,FLEN)
NAN_BOXED(15571,16,FLEN)
NAN_BOXED(17216,16,FLEN)
NAN_BOXED(18251,16,FLEN)
NAN_BOXED(51869,16,FLEN)
NAN_BOXED(19620,16,FLEN)
NAN_BOXED(21013,16,FLEN)
NAN_BOXED(21839,16,FLEN)
NAN_BOXED(55551,16,FLEN)
NAN_BOXED(57295,16,FLEN)
NAN_BOXED(25596,16,FLEN)
NAN_BOXED(25645,16,FLEN)
NAN_BOXED(27504,16,FLEN)
NAN_BOXED(28265,16,FLEN)
NAN_BOXED(29062,16,FLEN)
NAN_BOXED(62754,16,FLEN)
NAN_BOXED(31411,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33470,16,FLEN)
NAN_BOXED(34469,16,FLEN)
NAN_BOXED(34952,16,FLEN)
NAN_BOXED(36626,16,FLEN)
test_dataset_1:
NAN_BOXED(37869,16,FLEN)
NAN_BOXED(38880,16,FLEN)
NAN_BOXED(39540,16,FLEN)
NAN_BOXED(39981,16,FLEN)
NAN_BOXED(40964,16,FLEN)
NAN_BOXED(42121,16,FLEN)
NAN_BOXED(43971,16,FLEN)
NAN_BOXED(44342,16,FLEN)
NAN_BOXED(45430,16,FLEN)
NAN_BOXED(46999,16,FLEN)
NAN_BOXED(47425,16,FLEN)
NAN_BOXED(48690,16,FLEN)
NAN_BOXED(49598,16,FLEN)
NAN_BOXED(50242,16,FLEN)
NAN_BOXED(42582,16,FLEN)
NAN_BOXED(55809,16,FLEN)
NAN_BOXED(44342,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 28*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

418
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.w.h_b23-01.S
View file

@ -1,418 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:30 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b23 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b23)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x77fc; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x77fc; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x77fc; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x77fc; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x77fc; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x77fd; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x77fd; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x77fd; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x77fd; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x77fd; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x77fe; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x77fe; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x77fe; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x77fe; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x77fe; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x77ff; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x77ff; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0x77ff; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x77ff; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0x77ff; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x7800; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x7800; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x7800; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x7800; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x7800; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x7801; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x7801; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x7801; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x7801; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x7801; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x7802; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x7802; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
inst_32:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
inst_33:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
inst_35:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
inst_37:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
inst_39:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
inst_41:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
inst_42:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
inst_43:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
inst_45:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(30716,16,FLEN)
NAN_BOXED(30716,16,FLEN)
NAN_BOXED(30716,16,FLEN)
NAN_BOXED(30716,16,FLEN)
NAN_BOXED(30716,16,FLEN)
NAN_BOXED(30717,16,FLEN)
NAN_BOXED(30717,16,FLEN)
NAN_BOXED(30717,16,FLEN)
NAN_BOXED(30717,16,FLEN)
NAN_BOXED(30717,16,FLEN)
NAN_BOXED(30718,16,FLEN)
NAN_BOXED(30718,16,FLEN)
NAN_BOXED(30718,16,FLEN)
NAN_BOXED(30718,16,FLEN)
NAN_BOXED(30718,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(30720,16,FLEN)
NAN_BOXED(30720,16,FLEN)
NAN_BOXED(30720,16,FLEN)
NAN_BOXED(30720,16,FLEN)
test_dataset_1:
NAN_BOXED(30720,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(30723,16,FLEN)
NAN_BOXED(30723,16,FLEN)
NAN_BOXED(30723,16,FLEN)
NAN_BOXED(30723,16,FLEN)
NAN_BOXED(30723,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30722,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 38*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

838
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.w.h_b24-01.S
View file

@ -1,838 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:30 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b24 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b24)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x211e; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x211e; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x211e; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x211e; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x211e; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x2e66; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x2e66; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x2e66; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x2e66; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x2e66; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0xf0; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0xf0; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0xf0; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0xf0; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0xf0; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0xbb1e; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0xbb1e; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xbb1e; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0xbb1e; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0xbb1e; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x2f0a; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x2f0a; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x2f0a; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x2f0a; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x2f0a; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0xaf0a; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0xaf0a; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0xaf0a; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0xaf0a; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0xaf0a; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0xae66; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0xae66; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
inst_32:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
inst_33:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
inst_34:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
inst_35:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
inst_36:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
inst_37:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
inst_38:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
inst_39:// fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xa11e; valaddr_reg:x8;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
inst_40:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
inst_41:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
inst_42:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
inst_43:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
inst_44:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
inst_45:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
inst_46:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
inst_47:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
inst_48:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
inst_49:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
inst_50:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
inst_51:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
inst_52:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
inst_53:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
inst_54:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
inst_55:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
inst_56:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
inst_57:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
inst_58:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
inst_59:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c00; valaddr_reg:x8;
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
inst_60:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
inst_61:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
inst_62:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
inst_63:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
inst_64:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
inst_65:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
inst_66:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
inst_67:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
inst_68:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
inst_69:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
inst_70:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
inst_71:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
inst_72:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
inst_73:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
inst_74:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc70; valaddr_reg:x8;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
inst_75:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
inst_76:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
inst_77:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
inst_78:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
inst_79:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbbeb; valaddr_reg:x8;
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
inst_80:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
inst_81:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 57*FLEN/8, x9, x5, x6,FLREG)
inst_82:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 58*FLEN/8, x9, x5, x6,FLREG)
inst_83:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 59*FLEN/8, x9, x5, x6,FLREG)
inst_84:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 60*FLEN/8, x9, x5, x6,FLREG)
inst_85:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 61*FLEN/8, x9, x5, x6,FLREG)
inst_86:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 62*FLEN/8, x9, x5, x6,FLREG)
inst_87:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 63*FLEN/8, x9, x5, x6,FLREG)
inst_88:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 64*FLEN/8, x9, x5, x6,FLREG)
inst_89:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 65*FLEN/8, x9, x5, x6,FLREG)
inst_90:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 66*FLEN/8, x9, x5, x6,FLREG)
inst_91:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 67*FLEN/8, x9, x5, x6,FLREG)
inst_92:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 68*FLEN/8, x9, x5, x6,FLREG)
inst_93:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 69*FLEN/8, x9, x5, x6,FLREG)
inst_94:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x8;
val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 70*FLEN/8, x9, x5, x6,FLREG)
inst_95:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 71*FLEN/8, x9, x5, x6,FLREG)
inst_96:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 72*FLEN/8, x9, x5, x6,FLREG)
inst_97:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 73*FLEN/8, x9, x5, x6,FLREG)
inst_98:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 74*FLEN/8, x9, x5, x6,FLREG)
inst_99:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:75*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 75*FLEN/8, x9, x5, x6,FLREG)
inst_100:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:76*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 76*FLEN/8, x9, x5, x6,FLREG)
inst_101:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:77*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 77*FLEN/8, x9, x5, x6,FLREG)
inst_102:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:78*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 78*FLEN/8, x9, x5, x6,FLREG)
inst_103:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:79*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 79*FLEN/8, x9, x5, x6,FLREG)
inst_104:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:80*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 80*FLEN/8, x9, x5, x6,FLREG)
inst_105:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:81*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 81*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(12042,16,FLEN)
test_dataset_1:
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(44646,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 158*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.w.h_b27-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:30 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b27 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b27)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x7c01; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0xfc01; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x7d55; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0xfd55; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x7e01; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0xfe01; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x7e55; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0xfe55; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64513,16,FLEN)
NAN_BOXED(32085,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65025,16,FLEN)
NAN_BOXED(32341,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.w.h_b28-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:30 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b28 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b28)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x3892; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x3c00; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x3d00; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x3e00; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x3f00; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x4000; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x4080; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x4100; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x4180; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x72dc; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x77ff; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x7c00; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x7c01; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x7e01; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x8000; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0xb6c0; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0xbc00; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0xc180; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0xc100; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0xc080; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0xc000; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0xbf00; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0xbe00; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0xbd00; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0xf659; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0xf800; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0xfc00; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,16,FLEN)
NAN_BOXED(14482,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15616,16,FLEN)
NAN_BOXED(15872,16,FLEN)
NAN_BOXED(16128,16,FLEN)
NAN_BOXED(16384,16,FLEN)
NAN_BOXED(16512,16,FLEN)
NAN_BOXED(16640,16,FLEN)
NAN_BOXED(16768,16,FLEN)
NAN_BOXED(29404,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(46784,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(49536,16,FLEN)
NAN_BOXED(49408,16,FLEN)
NAN_BOXED(49280,16,FLEN)
NAN_BOXED(49152,16,FLEN)
NAN_BOXED(48896,16,FLEN)
NAN_BOXED(48640,16,FLEN)
test_dataset_1:
NAN_BOXED(48384,16,FLEN)
NAN_BOXED(63065,16,FLEN)
NAN_BOXED(63488,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

663
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.w.h_b29-01.S
View file

@ -1,663 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:30 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.w.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.w.h_b29 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.w.h_b29)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x3248; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f30; dest:x30; op1val:0x3248; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f29; dest:x29; op1val:0x3248; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f28; dest:x28; op1val:0x3248; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f27; dest:x27; op1val:0x3248; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f26; dest:x26; op1val:0x3249; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f25; dest:x25; op1val:0x3249; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f24; dest:x24; op1val:0x3249; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f23; dest:x23; op1val:0x3249; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f22; dest:x22; op1val:0x3249; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f21; dest:x21; op1val:0x324a; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f20; dest:x20; op1val:0x324a; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f19; dest:x19; op1val:0x324a; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f18; dest:x18; op1val:0x324a; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f17; dest:x17; op1val:0x324a; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f16; dest:x16; op1val:0x324b; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f15; dest:x15; op1val:0x324b; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f14; dest:x14; op1val:0x324b; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f13; dest:x13; op1val:0x324b; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f12; dest:x12; op1val:0x324b; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f11; dest:x11; op1val:0x324c; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f10; dest:x10; op1val:0x324c; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f9; dest:x9; op1val:0x324c; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f8; dest:x8; op1val:0x324c; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f7; dest:x7; op1val:0x324c; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f6; dest:x6; op1val:0x324d; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f5; dest:x5; op1val:0x324d; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f4; dest:x4; op1val:0x324d; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f3; dest:x3; op1val:0x324d; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f2; dest:x2; op1val:0x324d; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f1; dest:x1; op1val:0x324e; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f0; dest:x0; op1val:0x324e; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
inst_32:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
inst_33:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
inst_34:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
inst_35:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
inst_36:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
inst_37:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
inst_38:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
inst_39:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
inst_40:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
inst_41:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
inst_42:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
inst_43:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
inst_44:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
inst_45:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
inst_46:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
inst_47:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
inst_48:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
inst_49:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
inst_50:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
inst_51:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
inst_52:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
inst_53:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
inst_54:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
inst_55:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
inst_56:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
inst_57:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
inst_58:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
inst_59:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
inst_60:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
inst_61:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
inst_62:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
inst_63:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
inst_64:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
inst_65:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
inst_66:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
inst_67:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
inst_68:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
inst_69:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
inst_70:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
inst_71:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
inst_72:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
inst_73:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
inst_74:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
inst_75:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
inst_76:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
inst_77:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
inst_78:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
inst_79:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
inst_80:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.w.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.h, x31, f31, dyn, 32, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(12872,16,FLEN)
NAN_BOXED(12872,16,FLEN)
NAN_BOXED(12872,16,FLEN)
NAN_BOXED(12872,16,FLEN)
NAN_BOXED(12872,16,FLEN)
NAN_BOXED(12873,16,FLEN)
NAN_BOXED(12873,16,FLEN)
NAN_BOXED(12873,16,FLEN)
NAN_BOXED(12873,16,FLEN)
NAN_BOXED(12873,16,FLEN)
NAN_BOXED(12874,16,FLEN)
NAN_BOXED(12874,16,FLEN)
NAN_BOXED(12874,16,FLEN)
NAN_BOXED(12874,16,FLEN)
NAN_BOXED(12874,16,FLEN)
NAN_BOXED(12875,16,FLEN)
NAN_BOXED(12875,16,FLEN)
NAN_BOXED(12875,16,FLEN)
NAN_BOXED(12875,16,FLEN)
NAN_BOXED(12875,16,FLEN)
NAN_BOXED(12876,16,FLEN)
NAN_BOXED(12876,16,FLEN)
NAN_BOXED(12876,16,FLEN)
NAN_BOXED(12876,16,FLEN)
test_dataset_1:
NAN_BOXED(12876,16,FLEN)
NAN_BOXED(12877,16,FLEN)
NAN_BOXED(12877,16,FLEN)
NAN_BOXED(12877,16,FLEN)
NAN_BOXED(12877,16,FLEN)
NAN_BOXED(12877,16,FLEN)
NAN_BOXED(12878,16,FLEN)
NAN_BOXED(12878,16,FLEN)
NAN_BOXED(12878,16,FLEN)
NAN_BOXED(12878,16,FLEN)
NAN_BOXED(12878,16,FLEN)
NAN_BOXED(12879,16,FLEN)
NAN_BOXED(12879,16,FLEN)
NAN_BOXED(12879,16,FLEN)
NAN_BOXED(12879,16,FLEN)
NAN_BOXED(12879,16,FLEN)
NAN_BOXED(45640,16,FLEN)
NAN_BOXED(45640,16,FLEN)
NAN_BOXED(45640,16,FLEN)
NAN_BOXED(45640,16,FLEN)
NAN_BOXED(45640,16,FLEN)
NAN_BOXED(45641,16,FLEN)
NAN_BOXED(45641,16,FLEN)
NAN_BOXED(45641,16,FLEN)
NAN_BOXED(45641,16,FLEN)
NAN_BOXED(45641,16,FLEN)
NAN_BOXED(45642,16,FLEN)
NAN_BOXED(45642,16,FLEN)
NAN_BOXED(45642,16,FLEN)
NAN_BOXED(45642,16,FLEN)
NAN_BOXED(45642,16,FLEN)
NAN_BOXED(45643,16,FLEN)
NAN_BOXED(45643,16,FLEN)
NAN_BOXED(45643,16,FLEN)
NAN_BOXED(45643,16,FLEN)
NAN_BOXED(45643,16,FLEN)
NAN_BOXED(45644,16,FLEN)
NAN_BOXED(45644,16,FLEN)
NAN_BOXED(45644,16,FLEN)
NAN_BOXED(45644,16,FLEN)
NAN_BOXED(45644,16,FLEN)
NAN_BOXED(45645,16,FLEN)
NAN_BOXED(45645,16,FLEN)
NAN_BOXED(45645,16,FLEN)
NAN_BOXED(45645,16,FLEN)
NAN_BOXED(45645,16,FLEN)
NAN_BOXED(45646,16,FLEN)
NAN_BOXED(45646,16,FLEN)
NAN_BOXED(45646,16,FLEN)
NAN_BOXED(45646,16,FLEN)
NAN_BOXED(45646,16,FLEN)
NAN_BOXED(45647,16,FLEN)
NAN_BOXED(45647,16,FLEN)
NAN_BOXED(45647,16,FLEN)
NAN_BOXED(45647,16,FLEN)
NAN_BOXED(45647,16,FLEN)
NAN_BOXED(12878,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 108*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.wu.h_b1-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:49 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0x8000; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0x8001; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0x83fe; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0x3ff; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0x83ff; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x400; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x8400; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0x401; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0x8455; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0x7bff; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0xfbff; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0x7c00; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0xfc00; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0x7e00; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0xfe00; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0x7e01; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0xfe55; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0x7c01; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0xfd55; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0x3c00; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0xbc00; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(1,16,FLEN)
NAN_BOXED(32769,16,FLEN)
NAN_BOXED(2,16,FLEN)
NAN_BOXED(33790,16,FLEN)
NAN_BOXED(1023,16,FLEN)
NAN_BOXED(33791,16,FLEN)
NAN_BOXED(1024,16,FLEN)
NAN_BOXED(33792,16,FLEN)
NAN_BOXED(1025,16,FLEN)
NAN_BOXED(33877,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(32256,16,FLEN)
NAN_BOXED(65024,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(48128,16,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

383
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.wu.h_b22-01.S
View file

@ -1,383 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:49 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b22 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b22)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3249; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0x35b7; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x3a4f; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0x3cd3; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x4340; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0x474b; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x12 and fm1 == 0x29d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0xca9d; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x13 and fm1 == 0x0a4 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0x4ca4; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x14 and fm1 == 0x215 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x5215; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x15 and fm1 == 0x14f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x554f; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,fs1 == 1 and fe1 == 0x16 and fm1 == 0x0ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0xd8ff; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x17 and fm1 == 0x3cf and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0xdfcf; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x18 and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0x63fc; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x19 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0x642d; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1a and fm1 == 0x370 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0x6b70; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x1b and fm1 == 0x269 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0x6e69; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x186 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0x7186; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1d and fm1 == 0x122 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0xf522; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0x7ab3; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0x7bff; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x00 and fm1 == 0x2be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0x82be; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x01 and fm1 == 0x2a5 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0x86a5; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x02 and fm1 == 0x088 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0x8888; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x03 and fm1 == 0x312 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0x8f12; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x04 and fm1 == 0x3ed and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0x93ed; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x05 and fm1 == 0x3e0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0x97e0; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x06 and fm1 == 0x274 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0x9a74; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x07 and fm1 == 0x02d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0x9c2d; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,fs1 == 1 and fe1 == 0x08 and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0xa004; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,fs1 == 1 and fe1 == 0x09 and fm1 == 0x089 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0xa489; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x0a and fm1 == 0x3c3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0xabc3; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0xad36; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
inst_32:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x176 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb176; valaddr_reg:x8;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
inst_33:// fs1 == 1 and fe1 == 0x0d and fm1 == 0x397 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb797; valaddr_reg:x8;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
inst_34:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x141 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb941; valaddr_reg:x8;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x232 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbe32; valaddr_reg:x8;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
inst_36:// fs1 == 1 and fe1 == 0x10 and fm1 == 0x1be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xc1be; valaddr_reg:x8;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
inst_37:// fs1 == 1 and fe1 == 0x11 and fm1 == 0x042 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xc442; valaddr_reg:x8;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
inst_38:// fs1 == 1 and fe1 == 0x09 and fm1 == 0x256 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xa656; valaddr_reg:x8;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
inst_39:// fs1 == 1 and fe1 == 0x16 and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xda01; valaddr_reg:x8;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
inst_40:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x136 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xad36; valaddr_reg:x8;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(12873,16,FLEN)
NAN_BOXED(13751,16,FLEN)
NAN_BOXED(14927,16,FLEN)
NAN_BOXED(15571,16,FLEN)
NAN_BOXED(17216,16,FLEN)
NAN_BOXED(18251,16,FLEN)
NAN_BOXED(51869,16,FLEN)
NAN_BOXED(19620,16,FLEN)
NAN_BOXED(21013,16,FLEN)
NAN_BOXED(21839,16,FLEN)
NAN_BOXED(55551,16,FLEN)
NAN_BOXED(57295,16,FLEN)
NAN_BOXED(25596,16,FLEN)
NAN_BOXED(25645,16,FLEN)
NAN_BOXED(27504,16,FLEN)
NAN_BOXED(28265,16,FLEN)
NAN_BOXED(29062,16,FLEN)
NAN_BOXED(62754,16,FLEN)
NAN_BOXED(31411,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(33470,16,FLEN)
NAN_BOXED(34469,16,FLEN)
NAN_BOXED(34952,16,FLEN)
NAN_BOXED(36626,16,FLEN)
test_dataset_1:
NAN_BOXED(37869,16,FLEN)
NAN_BOXED(38880,16,FLEN)
NAN_BOXED(39540,16,FLEN)
NAN_BOXED(39981,16,FLEN)
NAN_BOXED(40964,16,FLEN)
NAN_BOXED(42121,16,FLEN)
NAN_BOXED(43971,16,FLEN)
NAN_BOXED(44342,16,FLEN)
NAN_BOXED(45430,16,FLEN)
NAN_BOXED(46999,16,FLEN)
NAN_BOXED(47425,16,FLEN)
NAN_BOXED(48690,16,FLEN)
NAN_BOXED(49598,16,FLEN)
NAN_BOXED(50242,16,FLEN)
NAN_BOXED(42582,16,FLEN)
NAN_BOXED(55809,16,FLEN)
NAN_BOXED(44342,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 28*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

418
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.wu.h_b23-01.S
View file

@ -1,418 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:49 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b23 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b23)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x77fc; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0x77fc; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x77fc; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0x77fc; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x77fc; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0x77fd; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0x77fd; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0x77fd; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x77fd; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x77fd; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0x77fe; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0x77fe; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0x77fe; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0x77fe; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0x77fe; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0x77ff; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0x77ff; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0x77ff; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0x77ff; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0x77ff; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0x7800; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0x7800; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0x7800; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0x7800; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0x7800; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0x7801; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0x7801; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0x7801; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0x7801; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0x7801; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0x7802; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0x7802; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
inst_32:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
inst_33:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
inst_34:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
inst_35:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
inst_36:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
inst_37:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
inst_38:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
inst_39:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7803; valaddr_reg:x8;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
inst_40:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
inst_41:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
inst_42:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
inst_43:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
inst_44:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7804; valaddr_reg:x8;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
inst_45:// fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7802; valaddr_reg:x8;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(30716,16,FLEN)
NAN_BOXED(30716,16,FLEN)
NAN_BOXED(30716,16,FLEN)
NAN_BOXED(30716,16,FLEN)
NAN_BOXED(30716,16,FLEN)
NAN_BOXED(30717,16,FLEN)
NAN_BOXED(30717,16,FLEN)
NAN_BOXED(30717,16,FLEN)
NAN_BOXED(30717,16,FLEN)
NAN_BOXED(30717,16,FLEN)
NAN_BOXED(30718,16,FLEN)
NAN_BOXED(30718,16,FLEN)
NAN_BOXED(30718,16,FLEN)
NAN_BOXED(30718,16,FLEN)
NAN_BOXED(30718,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(30720,16,FLEN)
NAN_BOXED(30720,16,FLEN)
NAN_BOXED(30720,16,FLEN)
NAN_BOXED(30720,16,FLEN)
test_dataset_1:
NAN_BOXED(30720,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(30722,16,FLEN)
NAN_BOXED(30723,16,FLEN)
NAN_BOXED(30723,16,FLEN)
NAN_BOXED(30723,16,FLEN)
NAN_BOXED(30723,16,FLEN)
NAN_BOXED(30723,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30724,16,FLEN)
NAN_BOXED(30722,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 38*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

838
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.wu.h_b24-01.S
View file

@ -1,838 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:49 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b24 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b24)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c0a; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0x3c0a; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x3c0a; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0x3c0a; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x3c0a; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0x211e; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0x211e; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0x211e; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x211e; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x211e; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0xbc70; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0xbc70; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0xbc70; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0xbc70; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0xbc70; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0xa11e; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0xa11e; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0xa11e; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0xa11e; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0xa11e; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0x3c00; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0x3c00; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0x3c00; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0x3c00; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0x3c00; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0xbbeb; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0xbbeb; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0xbbeb; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0xbbeb; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0xbbeb; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0xbc00; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0xbc00; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
inst_32:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
inst_33:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
inst_34:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
inst_35:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
inst_36:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
inst_37:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
inst_38:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
inst_39:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc66; valaddr_reg:x8;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
inst_40:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xf0; valaddr_reg:x8;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
inst_41:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xf0; valaddr_reg:x8;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
inst_42:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xf0; valaddr_reg:x8;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
inst_43:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xf0; valaddr_reg:x8;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
inst_44:// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xf0; valaddr_reg:x8;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
inst_45:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
inst_46:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
inst_47:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
inst_48:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
inst_49:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b33; valaddr_reg:x8;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
inst_50:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xaf0a; valaddr_reg:x8;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
inst_51:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xaf0a; valaddr_reg:x8;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
inst_52:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xaf0a; valaddr_reg:x8;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
inst_53:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xaf0a; valaddr_reg:x8;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
inst_54:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xaf0a; valaddr_reg:x8;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
inst_55:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
inst_56:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
inst_57:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
inst_58:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
inst_59:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3beb; valaddr_reg:x8;
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
inst_60:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2e66; valaddr_reg:x8;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
inst_61:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2e66; valaddr_reg:x8;
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
inst_62:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2e66; valaddr_reg:x8;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
inst_63:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2e66; valaddr_reg:x8;
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
inst_64:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2e66; valaddr_reg:x8;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
inst_65:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2f0a; valaddr_reg:x8;
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
inst_66:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2f0a; valaddr_reg:x8;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
inst_67:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2f0a; valaddr_reg:x8;
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
inst_68:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2f0a; valaddr_reg:x8;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
inst_69:// fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x2f0a; valaddr_reg:x8;
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
inst_70:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
inst_71:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
inst_72:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
inst_73:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
inst_74:// fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3b1e; valaddr_reg:x8;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
inst_75:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
inst_76:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
inst_77:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
inst_78:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
inst_79:// fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xae66; valaddr_reg:x8;
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
inst_80:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
inst_81:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 57*FLEN/8, x9, x5, x6,FLREG)
inst_82:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 58*FLEN/8, x9, x5, x6,FLREG)
inst_83:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 59*FLEN/8, x9, x5, x6,FLREG)
inst_84:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c66; valaddr_reg:x8;
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 60*FLEN/8, x9, x5, x6,FLREG)
inst_85:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 61*FLEN/8, x9, x5, x6,FLREG)
inst_86:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 62*FLEN/8, x9, x5, x6,FLREG)
inst_87:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 63*FLEN/8, x9, x5, x6,FLREG)
inst_88:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 64*FLEN/8, x9, x5, x6,FLREG)
inst_89:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb33; valaddr_reg:x8;
val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 65*FLEN/8, x9, x5, x6,FLREG)
inst_90:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 66*FLEN/8, x9, x5, x6,FLREG)
inst_91:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 67*FLEN/8, x9, x5, x6,FLREG)
inst_92:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 68*FLEN/8, x9, x5, x6,FLREG)
inst_93:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 69*FLEN/8, x9, x5, x6,FLREG)
inst_94:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc0a; valaddr_reg:x8;
val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 70*FLEN/8, x9, x5, x6,FLREG)
inst_95:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 71*FLEN/8, x9, x5, x6,FLREG)
inst_96:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 72*FLEN/8, x9, x5, x6,FLREG)
inst_97:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 73*FLEN/8, x9, x5, x6,FLREG)
inst_98:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 74*FLEN/8, x9, x5, x6,FLREG)
inst_99:// fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3c70; valaddr_reg:x8;
val_offset:75*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 75*FLEN/8, x9, x5, x6,FLREG)
inst_100:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb1e; valaddr_reg:x8;
val_offset:76*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 76*FLEN/8, x9, x5, x6,FLREG)
inst_101:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb1e; valaddr_reg:x8;
val_offset:77*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 77*FLEN/8, x9, x5, x6,FLREG)
inst_102:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb1e; valaddr_reg:x8;
val_offset:78*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 78*FLEN/8, x9, x5, x6,FLREG)
inst_103:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb1e; valaddr_reg:x8;
val_offset:79*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 79*FLEN/8, x9, x5, x6,FLREG)
inst_104:// fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbb1e; valaddr_reg:x8;
val_offset:80*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 80*FLEN/8, x9, x5, x6,FLREG)
inst_105:// fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xbc00; valaddr_reg:x8;
val_offset:81*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 81*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(15370,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(8478,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(48240,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(41246,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15360,16,FLEN)
test_dataset_1:
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48107,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(48230,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(240,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(15155,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(44810,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(15339,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(11878,16,FLEN)
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(12042,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(15134,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(44646,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(15462,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(47923,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(48138,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(15472,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(47902,16,FLEN)
NAN_BOXED(48128,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 158*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.wu.h_b27-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:49 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b27 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b27)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x7c01; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0xfc01; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x7d55; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0xfd55; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x7e01; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0xfe01; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0x7e55; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0xfe55; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(64513,16,FLEN)
NAN_BOXED(32085,16,FLEN)
NAN_BOXED(64853,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(65025,16,FLEN)
NAN_BOXED(32341,16,FLEN)
NAN_BOXED(65109,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.wu.h_b28-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:49 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b28 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b28)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0e and fm1 == 0x092 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0x3892; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x3c00; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0x3d00; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x3e00; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0x3f00; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0x4000; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0x4080; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x4100; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x4180; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2dc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0x72dc; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0x77ff; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0x7c00; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0x7c01; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0x7e01; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0x8000; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x0d and fm1 == 0x2c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0xb6c0; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0xbc00; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x10 and fm1 == 0x180 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0xc180; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x10 and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0xc100; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x10 and fm1 == 0x080 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0xc080; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x10 and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0xc000; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,fs1 == 1 and fe1 == 0x0f and fm1 == 0x300 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0xbf00; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x200 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0xbe00; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,fs1 == 1 and fe1 == 0x0f and fm1 == 0x100 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0xbd00; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 0, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,fs1 == 1 and fe1 == 0x1d and fm1 == 0x259 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0xf659; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,fs1 == 1 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0xf800; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 0, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0xfc00; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 0, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 0, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 0, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 0, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,16,FLEN)
NAN_BOXED(14482,16,FLEN)
NAN_BOXED(15360,16,FLEN)
NAN_BOXED(15616,16,FLEN)
NAN_BOXED(15872,16,FLEN)
NAN_BOXED(16128,16,FLEN)
NAN_BOXED(16384,16,FLEN)
NAN_BOXED(16512,16,FLEN)
NAN_BOXED(16640,16,FLEN)
NAN_BOXED(16768,16,FLEN)
NAN_BOXED(29404,16,FLEN)
NAN_BOXED(30719,16,FLEN)
NAN_BOXED(31744,16,FLEN)
NAN_BOXED(31745,16,FLEN)
NAN_BOXED(32257,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(46784,16,FLEN)
NAN_BOXED(48128,16,FLEN)
NAN_BOXED(49536,16,FLEN)
NAN_BOXED(49408,16,FLEN)
NAN_BOXED(49280,16,FLEN)
NAN_BOXED(49152,16,FLEN)
NAN_BOXED(48896,16,FLEN)
NAN_BOXED(48640,16,FLEN)
test_dataset_1:
NAN_BOXED(48384,16,FLEN)
NAN_BOXED(63065,16,FLEN)
NAN_BOXED(63488,16,FLEN)
NAN_BOXED(64512,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

663
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fcvt.wu.h_b29-01.S
View file

@ -1,663 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:40:49 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fcvt.wu.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fcvt.wu.h_b29 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fcvt.wu.h_b29)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x3248; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2,FLREG)
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f30; dest:x30; op1val:0x3248; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x30, f30, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2,FLREG)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f29; dest:x29; op1val:0x3248; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x29, f29, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2,FLREG)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f28; dest:x28; op1val:0x3248; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x28, f28, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f27; dest:x27; op1val:0x3248; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x27, f27, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f26; dest:x26; op1val:0x3249; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x26, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f25; dest:x25; op1val:0x3249; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x25, f25, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f24; dest:x24; op1val:0x3249; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x24, f24, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f23; dest:x23; op1val:0x3249; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x23, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f22; dest:x22; op1val:0x3249; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x22, f22, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2,FLREG)
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f21; dest:x21; op1val:0x324a; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x21, f21, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2,FLREG)
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f20; dest:x20; op1val:0x324a; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x20, f20, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2,FLREG)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f19; dest:x19; op1val:0x324a; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x19, f19, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2,FLREG)
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f18; dest:x18; op1val:0x324a; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x18, f18, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2,FLREG)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f17; dest:x17; op1val:0x324a; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x17, f17, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2,FLREG)
inst_15:// rs1==f16, rd==x16,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f16; dest:x16; op1val:0x324b; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x16, f16, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2,FLREG)
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f15; dest:x15; op1val:0x324b; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x15, f15, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2,FLREG)
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f14; dest:x14; op1val:0x324b; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x14, f14, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2,FLREG)
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f13; dest:x13; op1val:0x324b; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x13, f13, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2,FLREG)
inst_19:// rs1==f12, rd==x12,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f12; dest:x12; op1val:0x324b; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x12, f12, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2,FLREG)
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f11; dest:x11; op1val:0x324c; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x11, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2,FLREG)
inst_21:// rs1==f10, rd==x10,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f10; dest:x10; op1val:0x324c; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x10, f10, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2,FLREG)
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f9; dest:x9; op1val:0x324c; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x9, f9, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2,FLREG)
inst_23:// rs1==f8, rd==x8,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f8; dest:x8; op1val:0x324c; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x8, f8, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2,FLREG)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f7; dest:x7; op1val:0x324c; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x7, f7, dyn, 128, 0, x8, 0*FLEN/8, x9, x1, x2,FLREG)
inst_25:// rs1==f6, rd==x6,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f6; dest:x6; op1val:0x324d; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x6, f6, dyn, 0, 0, x8, 1*FLEN/8, x9, x1, x2,FLREG)
inst_26:// rs1==f5, rd==x5,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f5; dest:x5; op1val:0x324d; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x5, f5, dyn, 32, 0, x8, 2*FLEN/8, x9, x1, x6,FLREG)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f4; dest:x4; op1val:0x324d; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x4, f4, dyn, 64, 0, x8, 3*FLEN/8, x9, x5, x6,FLREG)
inst_28:// rs1==f3, rd==x3,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f3; dest:x3; op1val:0x324d; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x3, f3, dyn, 96, 0, x8, 4*FLEN/8, x9, x5, x6,FLREG)
inst_29:// rs1==f2, rd==x2,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f2; dest:x2; op1val:0x324d; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x2, f2, dyn, 128, 0, x8, 5*FLEN/8, x9, x5, x6,FLREG)
inst_30:// rs1==f1, rd==x1,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f1; dest:x1; op1val:0x324e; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x1, f1, dyn, 0, 0, x8, 6*FLEN/8, x9, x5, x6,FLREG)
inst_31:// rs1==f0, rd==x0,fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f0; dest:x0; op1val:0x324e; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x0, f0, dyn, 32, 0, x8, 7*FLEN/8, x9, x5, x6,FLREG)
inst_32:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 8*FLEN/8, x9, x5, x6,FLREG)
inst_33:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 9*FLEN/8, x9, x5, x6,FLREG)
inst_34:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 10*FLEN/8, x9, x5, x6,FLREG)
inst_35:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 11*FLEN/8, x9, x5, x6,FLREG)
inst_36:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 12*FLEN/8, x9, x5, x6,FLREG)
inst_37:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 13*FLEN/8, x9, x5, x6,FLREG)
inst_38:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 14*FLEN/8, x9, x5, x6,FLREG)
inst_39:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324f; valaddr_reg:x8;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 15*FLEN/8, x9, x5, x6,FLREG)
inst_40:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 16*FLEN/8, x9, x5, x6,FLREG)
inst_41:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 17*FLEN/8, x9, x5, x6,FLREG)
inst_42:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 18*FLEN/8, x9, x5, x6,FLREG)
inst_43:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 19*FLEN/8, x9, x5, x6,FLREG)
inst_44:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x248 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb248; valaddr_reg:x8;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 20*FLEN/8, x9, x5, x6,FLREG)
inst_45:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 21*FLEN/8, x9, x5, x6,FLREG)
inst_46:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 22*FLEN/8, x9, x5, x6,FLREG)
inst_47:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 23*FLEN/8, x9, x5, x6,FLREG)
inst_48:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 24*FLEN/8, x9, x5, x6,FLREG)
inst_49:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb249; valaddr_reg:x8;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 25*FLEN/8, x9, x5, x6,FLREG)
inst_50:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 26*FLEN/8, x9, x5, x6,FLREG)
inst_51:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 27*FLEN/8, x9, x5, x6,FLREG)
inst_52:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 28*FLEN/8, x9, x5, x6,FLREG)
inst_53:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 29*FLEN/8, x9, x5, x6,FLREG)
inst_54:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24a and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24a; valaddr_reg:x8;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 30*FLEN/8, x9, x5, x6,FLREG)
inst_55:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 31*FLEN/8, x9, x5, x6,FLREG)
inst_56:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 32*FLEN/8, x9, x5, x6,FLREG)
inst_57:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 33*FLEN/8, x9, x5, x6,FLREG)
inst_58:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 34*FLEN/8, x9, x5, x6,FLREG)
inst_59:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24b and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24b; valaddr_reg:x8;
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 35*FLEN/8, x9, x5, x6,FLREG)
inst_60:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 36*FLEN/8, x9, x5, x6,FLREG)
inst_61:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 37*FLEN/8, x9, x5, x6,FLREG)
inst_62:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 38*FLEN/8, x9, x5, x6,FLREG)
inst_63:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 39*FLEN/8, x9, x5, x6,FLREG)
inst_64:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24c and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24c; valaddr_reg:x8;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 40*FLEN/8, x9, x5, x6,FLREG)
inst_65:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 41*FLEN/8, x9, x5, x6,FLREG)
inst_66:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 42*FLEN/8, x9, x5, x6,FLREG)
inst_67:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 43*FLEN/8, x9, x5, x6,FLREG)
inst_68:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 44*FLEN/8, x9, x5, x6,FLREG)
inst_69:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24d and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24d; valaddr_reg:x8;
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 45*FLEN/8, x9, x5, x6,FLREG)
inst_70:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 46*FLEN/8, x9, x5, x6,FLREG)
inst_71:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 47*FLEN/8, x9, x5, x6,FLREG)
inst_72:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 48*FLEN/8, x9, x5, x6,FLREG)
inst_73:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 49*FLEN/8, x9, x5, x6,FLREG)
inst_74:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24e; valaddr_reg:x8;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 50*FLEN/8, x9, x5, x6,FLREG)
inst_75:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 0, 0, x8, 51*FLEN/8, x9, x5, x6,FLREG)
inst_76:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 52*FLEN/8, x9, x5, x6,FLREG)
inst_77:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 64, 0, x8, 53*FLEN/8, x9, x5, x6,FLREG)
inst_78:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 96, 0, x8, 54*FLEN/8, x9, x5, x6,FLREG)
inst_79:// fs1 == 1 and fe1 == 0x0c and fm1 == 0x24f and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0xb24f; valaddr_reg:x8;
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 128, 0, x8, 55*FLEN/8, x9, x5, x6,FLREG)
inst_80:// fs1 == 0 and fe1 == 0x0c and fm1 == 0x24e and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff
/* opcode: fcvt.wu.h ; op1:f31; dest:x31; op1val:0x324e; valaddr_reg:x8;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.h, x31, f31, dyn, 32, 0, x8, 56*FLEN/8, x9, x5, x6,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(12872,16,FLEN)
NAN_BOXED(12872,16,FLEN)
NAN_BOXED(12872,16,FLEN)
NAN_BOXED(12872,16,FLEN)
NAN_BOXED(12872,16,FLEN)
NAN_BOXED(12873,16,FLEN)
NAN_BOXED(12873,16,FLEN)
NAN_BOXED(12873,16,FLEN)
NAN_BOXED(12873,16,FLEN)
NAN_BOXED(12873,16,FLEN)
NAN_BOXED(12874,16,FLEN)
NAN_BOXED(12874,16,FLEN)
NAN_BOXED(12874,16,FLEN)
NAN_BOXED(12874,16,FLEN)
NAN_BOXED(12874,16,FLEN)
NAN_BOXED(12875,16,FLEN)
NAN_BOXED(12875,16,FLEN)
NAN_BOXED(12875,16,FLEN)
NAN_BOXED(12875,16,FLEN)
NAN_BOXED(12875,16,FLEN)
NAN_BOXED(12876,16,FLEN)
NAN_BOXED(12876,16,FLEN)
NAN_BOXED(12876,16,FLEN)
NAN_BOXED(12876,16,FLEN)
test_dataset_1:
NAN_BOXED(12876,16,FLEN)
NAN_BOXED(12877,16,FLEN)
NAN_BOXED(12877,16,FLEN)
NAN_BOXED(12877,16,FLEN)
NAN_BOXED(12877,16,FLEN)
NAN_BOXED(12877,16,FLEN)
NAN_BOXED(12878,16,FLEN)
NAN_BOXED(12878,16,FLEN)
NAN_BOXED(12878,16,FLEN)
NAN_BOXED(12878,16,FLEN)
NAN_BOXED(12878,16,FLEN)
NAN_BOXED(12879,16,FLEN)
NAN_BOXED(12879,16,FLEN)
NAN_BOXED(12879,16,FLEN)
NAN_BOXED(12879,16,FLEN)
NAN_BOXED(12879,16,FLEN)
NAN_BOXED(45640,16,FLEN)
NAN_BOXED(45640,16,FLEN)
NAN_BOXED(45640,16,FLEN)
NAN_BOXED(45640,16,FLEN)
NAN_BOXED(45640,16,FLEN)
NAN_BOXED(45641,16,FLEN)
NAN_BOXED(45641,16,FLEN)
NAN_BOXED(45641,16,FLEN)
NAN_BOXED(45641,16,FLEN)
NAN_BOXED(45641,16,FLEN)
NAN_BOXED(45642,16,FLEN)
NAN_BOXED(45642,16,FLEN)
NAN_BOXED(45642,16,FLEN)
NAN_BOXED(45642,16,FLEN)
NAN_BOXED(45642,16,FLEN)
NAN_BOXED(45643,16,FLEN)
NAN_BOXED(45643,16,FLEN)
NAN_BOXED(45643,16,FLEN)
NAN_BOXED(45643,16,FLEN)
NAN_BOXED(45643,16,FLEN)
NAN_BOXED(45644,16,FLEN)
NAN_BOXED(45644,16,FLEN)
NAN_BOXED(45644,16,FLEN)
NAN_BOXED(45644,16,FLEN)
NAN_BOXED(45644,16,FLEN)
NAN_BOXED(45645,16,FLEN)
NAN_BOXED(45645,16,FLEN)
NAN_BOXED(45645,16,FLEN)
NAN_BOXED(45645,16,FLEN)
NAN_BOXED(45645,16,FLEN)
NAN_BOXED(45646,16,FLEN)
NAN_BOXED(45646,16,FLEN)
NAN_BOXED(45646,16,FLEN)
NAN_BOXED(45646,16,FLEN)
NAN_BOXED(45646,16,FLEN)
NAN_BOXED(45647,16,FLEN)
NAN_BOXED(45647,16,FLEN)
NAN_BOXED(45647,16,FLEN)
NAN_BOXED(45647,16,FLEN)
NAN_BOXED(45647,16,FLEN)
NAN_BOXED(12878,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 108*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

5889
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b1-01.S
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File diff suppressed because it is too large Load diff

1309
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b2-01.S
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File diff suppressed because it is too large Load diff

479
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b20-01.S
View file

@ -1,479 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Sat May 6 11:18:48 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fdiv.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fdiv.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fdiv_b20 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b20)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x24a and fs2 == 1 and fe2 == 0x0a and fm2 == 0x24a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f31; dest:f31; op1val:0x764a; op2val:0xaa4a;
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rs2 == rd, rs1==f29, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f29; op2:f29; dest:f29; op1val:0x7ad2; op2val:0x7ad2;
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f29, f29, f29, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:
// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ae and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f28; op2:f30; dest:f28; op1val:0x77ae; op2val:0x7bff;
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f28, f28, f30, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f31, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f2 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f31; op2:f28; dest:f30; op1val:0x79f2; op2val:0x7bff;
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f30, f31, f28, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:
// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f26; op2:f26; dest:f27; op1val:0x7677; op2val:0x7677;
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f27, f26, f26, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x150 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f27; op2:f25; dest:f26; op1val:0x7950; op2val:0x7bff;
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f26, f27, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1df and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f24; op2:f27; dest:f25; op1val:0x75df; op2val:0x8000;
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f25, f24, f27, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x30e and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f25; op2:f23; dest:f24; op1val:0x7b0e; op2val:0xfbff;
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f24, f25, f23, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x234 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f22; op2:f24; dest:f23; op1val:0x7a34; op2val:0x0;
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f23, f22, f24, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f23; op2:f21; dest:f22; op1val:0x79e7; op2val:0x7bff;
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f22, f23, f21, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x1b and fm1 == 0x188 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f20; op2:f22; dest:f21; op1val:0x6d88; op2val:0x0;
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x14e and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f21; op2:f19; dest:f20; op1val:0x794e; op2val:0x0;
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f20, f21, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e7 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f18; op2:f20; dest:f19; op1val:0x6ee7; op2val:0x7bff;
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f19, f18, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x1c and fm1 == 0x13c and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f19; op2:f17; dest:f18; op1val:0x713c; op2val:0xfbff;
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f18, f19, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f16; op2:f18; dest:f17; op1val:0x7ab7; op2val:0xfbff;
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f17, f16, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ec and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f17; op2:f15; dest:f16; op1val:0x75ec; op2val:0xfbff;
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f16, f17, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1db and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f14; op2:f16; dest:f15; op1val:0x79db; op2val:0x0;
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f15, f14, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x381 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f15; op2:f13; dest:f14; op1val:0x7781; op2val:0xfbff;
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f14, f15, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ef and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f12; op2:f14; dest:f13; op1val:0x74ef; op2val:0x0;
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f13, f12, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c8 and fs2 == 1 and fe2 == 0x1d and fm2 == 0x3c0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f13; op2:f11; dest:f12; op1val:0x7ac8; op2val:0xf7c0;
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f12, f13, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f10; op2:f12; dest:f11; op1val:0x78ea; op2val:0x7bff;
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f11, f10, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x09f and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f11; op2:f9; dest:f10; op1val:0x789f; op2val:0xfbff;
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f10, f11, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f8; op2:f10; dest:f9; op1val:0x792c; op2val:0x0;
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f9, f8, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x1c and fm1 == 0x164 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f9; op2:f7; dest:f8; op1val:0x7164; op2val:0x7bff;
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f8, f9, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f6, rs2==f8, rd==f7,fs1 == 0 and fe1 == 0x1c and fm1 == 0x342 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f6; op2:f8; dest:f7; op1val:0x7342; op2val:0x8000;
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f7, f6, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0x18 and fm1 == 0x24d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f7; op2:f5; dest:f6; op1val:0x624d; op2val:0x0;
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f6, f7, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f4, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0x1c and fm1 == 0x261 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x008 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f4; op2:f6; dest:f5; op1val:0x7261; op2val:0x8008;
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f5, f4, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x35b and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f5; op2:f3; dest:f4; op1val:0x7b5b; op2val:0x0;
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f4, f5, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x062 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f2; op2:f4; dest:f3; op1val:0x7862; op2val:0x0;
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f3, f2, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f3, rs2==f1, rd==f2,fs1 == 0 and fe1 == 0x1d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f3; op2:f1; dest:f2; op1val:0x7677; op2val:0x8000;
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f2, f3, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x17f and fs2 == 1 and fe2 == 0x16 and fm2 == 0x266 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f0; op2:f2; dest:f1; op1val:0x757f; op2val:0xda66;
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f1, f0, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c6 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f1; op2:f30; dest:f31; op1val:0x7ac6; op2val:0xfbff;
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f1, f30, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:
// rs2==f0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a6 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f0; dest:f31; op1val:0x75a6; op2val:0x8000;
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f0, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
inst_33:
// rd==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x346 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f31; op2:f30; dest:f0; op1val:0x7b46; op2val:0x7bff;
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f0, f31, f30, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_34:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x145 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7945; op2val:0x8000;
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0de and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x78de; op2val:0xfbff;
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x79d5; op2val:0x8000;
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d2 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7ad2; op2val:0x0;
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x277 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7677; op2val:0xfbff;
valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(30282,16,FLEN)
NAN_BOXED(43594,16,FLEN)
NAN_BOXED(31442,16,FLEN)
NAN_BOXED(31442,16,FLEN)
NAN_BOXED(30638,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31218,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30327,16,FLEN)
NAN_BOXED(30327,16,FLEN)
NAN_BOXED(31056,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30175,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31502,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31284,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31207,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28040,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31054,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(28391,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28988,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31415,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30188,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31195,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30593,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(29935,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31432,16,FLEN)
NAN_BOXED(63424,16,FLEN)
NAN_BOXED(30954,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30879,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31020,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29028,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29506,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(25165,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29281,16,FLEN)
NAN_BOXED(32776,16,FLEN)
NAN_BOXED(31579,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30818,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30327,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30079,16,FLEN)
NAN_BOXED(55910,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(30118,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31558,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31045,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(30942,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(31189,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(31442,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30327,16,FLEN)
NAN_BOXED(64511,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 78*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b21-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b3-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b4-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b5-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b6-01.S
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@ -1,449 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Sat May 6 11:18:48 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fdiv.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fdiv.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fdiv_b6 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b6)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f31; dest:f31; op1val:0x0; op2val:0x8000;
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rs2 == rd, rs1==f29, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f29; op2:f29; dest:f29; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f29, f29, f29, dyn, 32, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:
// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f28; op2:f30; dest:f28; op1val:0x0; op2val:0x8000;
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f28, f28, f30, dyn, 64, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f31, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f31; op2:f28; dest:f30; op1val:0x0; op2val:0x8000;
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f30, f31, f28, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:
// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f26; op2:f26; dest:f27; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f27, f26, f26, dyn, 128, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f27; op2:f25; dest:f26; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f26, f27, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f24; op2:f27; dest:f25; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f25, f24, f27, dyn, 32, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f25; op2:f23; dest:f24; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f24, f25, f23, dyn, 64, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f22; op2:f24; dest:f23; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f23, f22, f24, dyn, 96, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f23; op2:f21; dest:f22; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f22, f23, f21, dyn, 128, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f20, rs2==f22, rd==f21,
/* opcode: fdiv.h ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f21, rs2==f19, rd==f20,
/* opcode: fdiv.h ; op1:f21; op2:f19; dest:f20; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f20, f21, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f18, rs2==f20, rd==f19,
/* opcode: fdiv.h ; op1:f18; op2:f20; dest:f19; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f19, f18, f20, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f19, rs2==f17, rd==f18,
/* opcode: fdiv.h ; op1:f19; op2:f17; dest:f18; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f18, f19, f17, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f16, rs2==f18, rd==f17,
/* opcode: fdiv.h ; op1:f16; op2:f18; dest:f17; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f17, f16, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f17, rs2==f15, rd==f16,
/* opcode: fdiv.h ; op1:f17; op2:f15; dest:f16; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f16, f17, f15, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f14, rs2==f16, rd==f15,
/* opcode: fdiv.h ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f15, f14, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f15, rs2==f13, rd==f14,
/* opcode: fdiv.h ; op1:f15; op2:f13; dest:f14; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f14, f15, f13, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rs2==f14, rd==f13,
/* opcode: fdiv.h ; op1:f12; op2:f14; dest:f13; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f13, f12, f14, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f13, rs2==f11, rd==f12,
/* opcode: fdiv.h ; op1:f13; op2:f11; dest:f12; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f12, f13, f11, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f10, rs2==f12, rd==f11,
/* opcode: fdiv.h ; op1:f10; op2:f12; dest:f11; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f11, f10, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f11, rs2==f9, rd==f10,
/* opcode: fdiv.h ; op1:f11; op2:f9; dest:f10; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f10, f11, f9, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f8, rs2==f10, rd==f9,
/* opcode: fdiv.h ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f9, f8, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f9, rs2==f7, rd==f8,
/* opcode: fdiv.h ; op1:f9; op2:f7; dest:f8; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f8, f9, f7, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f6, rs2==f8, rd==f7,
/* opcode: fdiv.h ; op1:f6; op2:f8; dest:f7; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f7, f6, f8, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f7, rs2==f5, rd==f6,
/* opcode: fdiv.h ; op1:f7; op2:f5; dest:f6; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f6, f7, f5, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f4, rs2==f6, rd==f5,
/* opcode: fdiv.h ; op1:f4; op2:f6; dest:f5; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f5, f4, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f5, rs2==f3, rd==f4,
/* opcode: fdiv.h ; op1:f5; op2:f3; dest:f4; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f4, f5, f3, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f2, rs2==f4, rd==f3,
/* opcode: fdiv.h ; op1:f2; op2:f4; dest:f3; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f3, f2, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f3, rs2==f1, rd==f2,
/* opcode: fdiv.h ; op1:f3; op2:f1; dest:f2; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f2, f3, f1, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f0, rs2==f2, rd==f1,
/* opcode: fdiv.h ; op1:f0; op2:f2; dest:f1; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f1, f0, f2, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f1,
/* opcode: fdiv.h ; op1:f1; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f1, f30, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:
// rs2==f0,
/* opcode: fdiv.h ; op1:f30; op2:f0; dest:f31; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f0, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
inst_33:
// rd==f0,
/* opcode: fdiv.h ; op1:f31; op2:f30; dest:f0; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f0, f31, f30, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_34:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x8000;
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 32;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 32, 0, x3, 68*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0x8000;
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 128;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 128, 0, x3, 70*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32768,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(32768,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 72*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

649
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fdiv_b7-01.S
View file

@ -1,649 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Sat May 6 11:18:48 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fdiv.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fdiv.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fdiv_b7 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*);def TEST_CASE_1=True;",fdiv_b7)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs2 == rd != rs1, rs1==f30, rs2==f31, rd==f31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x39c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f31; dest:f31; op1val:0x739c; op2val:0x7bff;
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f31, dyn, 96, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rs2 == rd, rs1==f29, rs2==f29, rd==f29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f29; op2:f29; dest:f29; op1val:0x75ea; op2val:0x75ea;
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f29, f29, f29, dyn, 96, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:
// rs1 == rd != rs2, rs1==f28, rs2==f30, rd==f28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x100 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f28; op2:f30; dest:f28; op1val:0x7900; op2val:0x7bff;
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f28, f28, f30, dyn, 96, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f31, rs2==f28, rd==f30,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f31; op2:f28; dest:f30; op1val:0x62bf; op2val:0x7bff;
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f30, f31, f28, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:
// rs1 == rs2 != rd, rs1==f26, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f26; op2:f26; dest:f27; op1val:0x7425; op2val:0x7425;
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f27, f26, f26, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f27, rs2==f25, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3f6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f27; op2:f25; dest:f26; op1val:0x7bf6; op2val:0x7bff;
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f26, f27, f25, dyn, 96, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f24, rs2==f27, rd==f25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f24; op2:f27; dest:f25; op1val:0x7ab0; op2val:0x7bff;
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f25, f24, f27, dyn, 96, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f25, rs2==f23, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x11c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f25; op2:f23; dest:f24; op1val:0x791c; op2val:0x7bff;
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f24, f25, f23, dyn, 96, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f22, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x113 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f22; op2:f24; dest:f23; op1val:0x7913; op2val:0x7bff;
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f23, f22, f24, dyn, 96, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f23, rs2==f21, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x02e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f23; op2:f21; dest:f22; op1val:0x782e; op2val:0x7bff;
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f22, f23, f21, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f20; op2:f22; dest:f21; op1val:0x795e; op2val:0x7bff;
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f21, f20, f22, dyn, 96, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f21, rs2==f19, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x210 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f21; op2:f19; dest:f20; op1val:0x7a10; op2val:0x7bff;
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f20, f21, f19, dyn, 96, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f18, rs2==f20, rd==f19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f18; op2:f20; dest:f19; op1val:0x74d1; op2val:0x7bff;
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f19, f18, f20, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f19, rs2==f17, rd==f18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2eb and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f19; op2:f17; dest:f18; op1val:0x7aeb; op2val:0x7bff;
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f18, f19, f17, dyn, 96, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f16, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1bf and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f16; op2:f18; dest:f17; op1val:0x79bf; op2val:0x7bff;
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f17, f16, f18, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f17, rs2==f15, rd==f16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1b5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f17; op2:f15; dest:f16; op1val:0x79b5; op2val:0x7bff;
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f16, f17, f15, dyn, 96, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x251 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f14; op2:f16; dest:f15; op1val:0x7651; op2val:0x7bff;
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f15, f14, f16, dyn, 96, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f15, rs2==f13, rd==f14,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f15; op2:f13; dest:f14; op1val:0x771c; op2val:0x7bff;
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f14, f15, f13, dyn, 96, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rs2==f14, rd==f13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x307 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f12; op2:f14; dest:f13; op1val:0x7b07; op2val:0x7bff;
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f13, f12, f14, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f13, rs2==f11, rd==f12,fs1 == 0 and fe1 == 0x1c and fm1 == 0x059 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f13; op2:f11; dest:f12; op1val:0x7059; op2val:0x7bff;
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f12, f13, f11, dyn, 96, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f10, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b8 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f10; op2:f12; dest:f11; op1val:0x7bb8; op2val:0x7bff;
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f11, f10, f12, dyn, 96, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f11, rs2==f9, rd==f10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x102 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f11; op2:f9; dest:f10; op1val:0x7902; op2val:0x7bff;
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f10, f11, f9, dyn, 96, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x00e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f8; op2:f10; dest:f9; op1val:0x780e; op2val:0x7bff;
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f9, f8, f10, dyn, 96, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f9, rs2==f7, rd==f8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x19c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f9; op2:f7; dest:f8; op1val:0x759c; op2val:0x7bff;
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f8, f9, f7, dyn, 96, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f6, rs2==f8, rd==f7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ab and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f6; op2:f8; dest:f7; op1val:0x78ab; op2val:0x7bff;
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f7, f6, f8, dyn, 96, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f7, rs2==f5, rd==f6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x174 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f7; op2:f5; dest:f6; op1val:0x7974; op2val:0x7bff;
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f6, f7, f5, dyn, 96, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f4, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f4; op2:f6; dest:f5; op1val:0x7ad9; op2val:0x7bff;
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f5, f4, f6, dyn, 96, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f5, rs2==f3, rd==f4,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2e1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f5; op2:f3; dest:f4; op1val:0x7ae1; op2val:0x7bff;
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f4, f5, f3, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x33b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f2; op2:f4; dest:f3; op1val:0x7b3b; op2val:0x7bff;
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f3, f2, f4, dyn, 96, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f3, rs2==f1, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2a6 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f3; op2:f1; dest:f2; op1val:0x7aa6; op2val:0x7bff;
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f2, f3, f1, dyn, 96, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f0, rs2==f2, rd==f1,fs1 == 0 and fe1 == 0x1d and fm1 == 0x08e and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f0; op2:f2; dest:f1; op1val:0x748e; op2val:0x7bff;
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f1, f0, f2, dyn, 96, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f1; op2:f30; dest:f31; op1val:0x7ad4; op2val:0x7bff;
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f1, f30, dyn, 96, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:
// rs2==f0,fs1 == 0 and fe1 == 0x1b and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f0; dest:f31; op1val:0x6da9; op2val:0x7bff;
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f0, dyn, 96, 0, x3, 64*FLEN/8, x4, x1, x2)
inst_33:
// rd==f0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x290 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f31; op2:f30; dest:f0; op1val:0x7690; op2val:0x7bff;
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f0, f31, f30, dyn, 96, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_34:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0b3 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x74b3; op2val:0x7bff;
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 68*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2fa and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7afa; op2val:0x7bff;
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 70*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e9 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x78e9; op2val:0x7bff;
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1be and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x79be; op2val:0x7bff;
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 74*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x30b and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b0b; op2val:0x7bff;
valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 76*FLEN/8, x4, x1, x2)
inst_39:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x00a and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x780a; op2val:0x7bff;
valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_40:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0f3 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x0f3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x74f3; op2val:0x5cf3;
valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 80*FLEN/8, x4, x1, x2)
inst_41:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0cb and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0cb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x78cb; op2val:0x60cb;
valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 82*FLEN/8, x4, x1, x2)
inst_42:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x250 and fs2 == 0 and fe2 == 0x16 and fm2 == 0x250 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7250; op2val:0x5a50;
valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x2)
inst_43:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e1 and fs2 == 0 and fe2 == 0x18 and fm2 == 0x0e1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x78e1; op2val:0x60e1;
valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 86*FLEN/8, x4, x1, x2)
inst_44:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x16e and fs2 == 0 and fe2 == 0x14 and fm2 == 0x16e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x696e; op2val:0x516e;
valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 88*FLEN/8, x4, x1, x2)
inst_45:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x104 and fs2 == 0 and fe2 == 0x17 and fm2 == 0x104 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7504; op2val:0x5d04;
valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 90*FLEN/8, x4, x1, x2)
inst_46:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x32b and fs2 == 0 and fe2 == 0x18 and fm2 == 0x32b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b2b; op2val:0x632b;
valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 92*FLEN/8, x4, x1, x2)
inst_47:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x35c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x775c; op2val:0x7bff;
valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 94*FLEN/8, x4, x1, x2)
inst_48:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x126 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7926; op2val:0x7bff;
valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 96*FLEN/8, x4, x1, x2)
inst_49:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x078 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7878; op2val:0x7bff;
valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 98*FLEN/8, x4, x1, x2)
inst_50:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x385 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b85; op2val:0x7bff;
valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 100*FLEN/8, x4, x1, x2)
inst_51:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e5 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x76e5; op2val:0x7bff;
valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 102*FLEN/8, x4, x1, x2)
inst_52:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x399 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7399; op2val:0x7bff;
valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 104*FLEN/8, x4, x1, x2)
inst_53:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d1 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7bd1; op2val:0x7bff;
valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 106*FLEN/8, x4, x1, x2)
inst_54:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1ea and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x75ea; op2val:0x7bff;
valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 108*FLEN/8, x4, x1, x2)
inst_55:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x025 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fdiv.h ; op1:f30; op2:f29; dest:f31; op1val:0x7425; op2val:0x7bff;
valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fdiv.h, f31, f30, f29, dyn, 96, 0, x3, 110*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(29596,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30186,16,FLEN)
NAN_BOXED(30186,16,FLEN)
NAN_BOXED(30976,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(25279,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(31734,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31408,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31004,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30995,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30766,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31070,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31248,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29905,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31467,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31167,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31157,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30289,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30492,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31495,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28761,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31672,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30978,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30108,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30891,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31092,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31449,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31457,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31547,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31398,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29838,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31444,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(28073,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30352,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29875,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31482,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30953,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31166,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31499,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30730,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29939,16,FLEN)
NAN_BOXED(23795,16,FLEN)
NAN_BOXED(30923,16,FLEN)
NAN_BOXED(24779,16,FLEN)
NAN_BOXED(29264,16,FLEN)
NAN_BOXED(23120,16,FLEN)
NAN_BOXED(30945,16,FLEN)
NAN_BOXED(24801,16,FLEN)
NAN_BOXED(26990,16,FLEN)
NAN_BOXED(20846,16,FLEN)
NAN_BOXED(29956,16,FLEN)
NAN_BOXED(23812,16,FLEN)
NAN_BOXED(31531,16,FLEN)
NAN_BOXED(25387,16,FLEN)
NAN_BOXED(30556,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31014,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30840,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31621,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30437,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29593,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31697,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(30186,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(29733,16,FLEN)
NAN_BOXED(31743,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 112*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fle_b1-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/flh-align-01.S
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@ -1,256 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:56:28 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_flh.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the flh instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the flh-align covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*);def TEST_CASE_1=True;",flh-align)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==x31, rd==f31,ea_align == 0 and (imm_val % 4) == 0, imm_val < 0
// opcode:flh op1:x31; dest:f31; immval:-0x4; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,159,x31,f31,-0x4,flh,0,x4)
inst_1:// rs1==x30, rd==f30,ea_align == 0 and (imm_val % 4) == 1,
// opcode:flh op1:x30; dest:f30; immval:-0x3; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,159,x30,f30,-0x3,flh,0,x4)
inst_2:// rs1==x29, rd==f29,ea_align == 0 and (imm_val % 4) == 2,
// opcode:flh op1:x29; dest:f29; immval:-0x6; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,159,x29,f29,-0x6,flh,0,x4)
inst_3:// rs1==x28, rd==f28,ea_align == 0 and (imm_val % 4) == 3, imm_val > 0
// opcode:flh op1:x28; dest:f28; immval:0x7ff; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,159,x28,f28,0x7ff,flh,0,x4)
inst_4:// rs1==x27, rd==f27,imm_val == 0,
// opcode:flh op1:x27; dest:f27; immval:0x0; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,159,x27,f27,0x0,flh,0,x4)
inst_5:// rs1==x26, rd==f26,
// opcode:flh op1:x26; dest:f26; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x26,f26,-0x800,flh,0,x4)
inst_6:// rs1==x25, rd==f25,
// opcode:flh op1:x25; dest:f25; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x25,f25,-0x800,flh,0,x4)
inst_7:// rs1==x24, rd==f24,
// opcode:flh op1:x24; dest:f24; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x24,f24,-0x800,flh,0,x4)
inst_8:// rs1==x23, rd==f23,
// opcode:flh op1:x23; dest:f23; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x23,f23,-0x800,flh,0,x4)
inst_9:// rs1==x22, rd==f22,
// opcode:flh op1:x22; dest:f22; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x22,f22,-0x800,flh,0,x4)
inst_10:// rs1==x21, rd==f21,
// opcode:flh op1:x21; dest:f21; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x21,f21,-0x800,flh,0,x4)
inst_11:// rs1==x20, rd==f20,
// opcode:flh op1:x20; dest:f20; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x20,f20,-0x800,flh,0,x4)
inst_12:// rs1==x19, rd==f19,
// opcode:flh op1:x19; dest:f19; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x19,f19,-0x800,flh,0,x4)
inst_13:// rs1==x18, rd==f18,
// opcode:flh op1:x18; dest:f18; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x18,f18,-0x800,flh,0,x4)
inst_14:// rs1==x17, rd==f17,
// opcode:flh op1:x17; dest:f17; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x17,f17,-0x800,flh,0,x4)
inst_15:// rs1==x16, rd==f16,
// opcode:flh op1:x16; dest:f16; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x16,f16,-0x800,flh,0,x4)
inst_16:// rs1==x15, rd==f15,
// opcode:flh op1:x15; dest:f15; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x15,f15,-0x800,flh,0,x4)
inst_17:// rs1==x14, rd==f14,
// opcode:flh op1:x14; dest:f14; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x14,f14,-0x800,flh,0,x4)
inst_18:// rs1==x13, rd==f13,
// opcode:flh op1:x13; dest:f13; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x13,f13,-0x800,flh,0,x4)
inst_19:// rs1==x12, rd==f12,
// opcode:flh op1:x12; dest:f12; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x12,f12,-0x800,flh,0,x4)
inst_20:// rs1==x11, rd==f11,
// opcode:flh op1:x11; dest:f11; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x11,f11,-0x800,flh,0,x4)
inst_21:// rs1==x10, rd==f10,
// opcode:flh op1:x10; dest:f10; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x10,f10,-0x800,flh,0,x4)
inst_22:// rs1==x9, rd==f9,
// opcode:flh op1:x9; dest:f9; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x9,f9,-0x800,flh,0,x4)
inst_23:// rs1==x8, rd==f8,
// opcode:flh op1:x8; dest:f8; immval:-0x800; align:0; flagreg:x4
TEST_LOAD_F(x1,x2,0,x8,f8,-0x800,flh,0,x4)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==x7, rd==f7,
// opcode:flh op1:x7; dest:f7; immval:-0x800; align:0; flagreg:x9
TEST_LOAD_F(x1,x2,0,x7,f7,-0x800,flh,0,x9)
inst_25:// rs1==x6, rd==f6,
// opcode:flh op1:x6; dest:f6; immval:-0x800; align:0; flagreg:x9
TEST_LOAD_F(x1,x2,0,x6,f6,-0x800,flh,0,x9)
inst_26:// rs1==x5, rd==f5,
// opcode:flh op1:x5; dest:f5; immval:-0x800; align:0; flagreg:x9
TEST_LOAD_F(x1,x6,0,x5,f5,-0x800,flh,0,x9)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==x4, rd==f4,
// opcode:flh op1:x4; dest:f4; immval:-0x800; align:0; flagreg:x9
TEST_LOAD_F(x5,x6,0,x4,f4,-0x800,flh,0,x9)
inst_28:// rs1==x3, rd==f3,
// opcode:flh op1:x3; dest:f3; immval:-0x800; align:0; flagreg:x9
TEST_LOAD_F(x5,x6,0,x3,f3,-0x800,flh,0,x9)
inst_29:// rs1==x2, rd==f2,
// opcode:flh op1:x2; dest:f2; immval:-0x800; align:0; flagreg:x9
TEST_LOAD_F(x5,x6,0,x2,f2,-0x800,flh,0,x9)
inst_30:// rs1==x1, rd==f1,
// opcode:flh op1:x1; dest:f1; immval:-0x800; align:0; flagreg:x9
TEST_LOAD_F(x5,x6,0,x1,f1,-0x800,flh,0,x9)
inst_31:// rd==f0,
// opcode:flh op1:x31; dest:f0; immval:-0x800; align:0; flagreg:x9
TEST_LOAD_F(x5,x6,0,x31,f0,-0x800,flh,0,x9)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
test_dataset_1:
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/flt_b1-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/flt_b19-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b1-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b14-01.S
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@ -1,519 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Tue Jan 30 08:43:40 2024 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmadd.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmadd_b14 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmadd_b14)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f30, rs2==f29, rs3==f29, rd==f31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f29; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x7a0f; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f29, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f29, rs2==f31, rs3==f30, rd==f29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0f and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f29; op2:f31; op3:f30; dest:f29; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x3eb9; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f29, f29, f31, f30, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_2:
// rs1 == rs2 == rs3 != rd, rs1==f28, rs2==f28, rs3==f28, rd==f30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x10 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f28; op2:f28; op3:f28; dest:f30; op1val:0x7ac0; op2val:0x7ac0;
op3val:0x7ac0; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f30, f28, f28, f28, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_3:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f27, rs2==f27, rs3==f31, rd==f28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f27; op2:f27; op3:f31; dest:f28; op1val:0x7ac0; op2val:0x7ac0;
op3val:0x46b9; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f28, f27, f27, f31, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_4:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f26, rs2==f30, rs3==f26, rd==f27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f26; op2:f30; op3:f26; dest:f27; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x7ac0; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f27, f26, f30, f26, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_5:
// rd == rs2 == rs3 != rs1, rs1==f31, rs2==f25, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f31; op2:f25; op3:f25; dest:f25; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x7a0f; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f25, f31, f25, f25, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_6:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f25, rs2==f24, rs3==f27, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x14 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f25; op2:f24; op3:f27; dest:f26; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x52b9; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f26, f25, f24, f27, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_7:
// rs1 == rs2 == rs3 == rd, rs1==f23, rs2==f23, rs3==f23, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x15 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f23; op2:f23; op3:f23; dest:f23; op1val:0x7ac0; op2val:0x7ac0;
op3val:0x7ac0; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f23, f23, f23, f23, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_8:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f22, rs2==f26, rs3==f24, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x16 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f22; op2:f26; op3:f24; dest:f24; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x5ab9; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f24, f22, f26, f24, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_9:
// rs1 == rs2 == rd != rs3, rs1==f21, rs2==f21, rs3==f22, rd==f21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x17 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f21; op2:f21; op3:f22; dest:f21; op1val:0x7ac0; op2val:0x7ac0;
op3val:0x5eb9; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f21, f21, f21, f22, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_10:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f24, rs2==f22, rs3==f21, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x18 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f24; op2:f22; op3:f21; dest:f22; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x62b9; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f22, f24, f22, f21, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_11:
// rs1 == rd == rs3 != rs2, rs1==f20, rs2==f19, rs3==f20, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f20; op2:f19; op3:f20; dest:f20; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x7ac0; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f20, f20, f19, f20, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f18, rs2==f20, rs3==f17, rd==f19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x1a and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f18; op2:f20; op3:f17; dest:f19; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x6ab9; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f19, f18, f20, f17, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f19, rs2==f17, rs3==f16, rd==f18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x6eb9; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f18, f19, f17, f16, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f16, rs2==f18, rs3==f19, rd==f17,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x72b9; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f17, f16, f18, f19, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f17, rs2==f15, rs3==f18, rd==f16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f17; op2:f15; op3:f18; dest:f16; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x76b9; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f16, f17, f15, f18, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f14, rs2==f16, rs3==f13, rd==f15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f14; op2:f16; op3:f13; dest:f15; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x7ab9; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f15, f14, f16, f13, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f15, rs2==f13, rs3==f12, rd==f14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x7bff; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f14, f15, f13, f12, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rs2==f14, rs3==f15, rd==f13,
/* opcode: fmadd.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f13, f12, f14, f15, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f13, rs2==f11, rs3==f14, rd==f12,
/* opcode: fmadd.h ; op1:f13; op2:f11; op3:f14; dest:f12; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f12, f13, f11, f14, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f10, rs2==f12, rs3==f9, rd==f11,
/* opcode: fmadd.h ; op1:f10; op2:f12; op3:f9; dest:f11; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f11, f10, f12, f9, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f11, rs2==f9, rs3==f8, rd==f10,
/* opcode: fmadd.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f10, f11, f9, f8, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f8, rs2==f10, rs3==f11, rd==f9,
/* opcode: fmadd.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f9, f8, f10, f11, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f9, rs2==f7, rs3==f10, rd==f8,
/* opcode: fmadd.h ; op1:f9; op2:f7; op3:f10; dest:f8; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f8, f9, f7, f10, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f6, rs2==f8, rs3==f5, rd==f7,
/* opcode: fmadd.h ; op1:f6; op2:f8; op3:f5; dest:f7; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f7, f6, f8, f5, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f7, rs2==f5, rs3==f4, rd==f6,
/* opcode: fmadd.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f6, f7, f5, f4, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f4, rs2==f6, rs3==f7, rd==f5,
/* opcode: fmadd.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f5, f4, f6, f7, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f5, rs2==f3, rs3==f6, rd==f4,
/* opcode: fmadd.h ; op1:f5; op2:f3; op3:f6; dest:f4; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f4, f5, f3, f6, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f2, rs2==f4, rs3==f1, rd==f3,
/* opcode: fmadd.h ; op1:f2; op2:f4; op3:f1; dest:f3; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f3, f2, f4, f1, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f3, rs2==f1, rs3==f0, rd==f2,
/* opcode: fmadd.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f2, f3, f1, f0, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f0, rs2==f2, rs3==f3, rd==f1,
/* opcode: fmadd.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f1, f0, f2, f3, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f1,
/* opcode: fmadd.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f1, f30, f29, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)
inst_32:
// rs2==f0,
/* opcode: fmadd.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f0, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
inst_33:
// rs3==f2,
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f2; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f2, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)
inst_34:
// rd==f0,
/* opcode: fmadd.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f0, f31, f30, f29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x0e and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x3ab9; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x10 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x42b9; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x11 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x46b9; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 111*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x12 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x4ab9; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
inst_39:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x13 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x4eb9; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2)
inst_40:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x15 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x56b9; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
inst_41:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x17 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x5eb9; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 123*FLEN/8, x4, x1, x2)
inst_42:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2c0 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x20f and fs3 == 0 and fe3 == 0x19 and fm3 == 0x2b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ac0; op2val:0x7a0f;
op3val:0x66b9; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(16057,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(18105,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(21177,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(23225,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(24249,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(25273,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(27321,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(28345,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(29369,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(30393,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31417,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(15033,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(17081,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(18105,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(19129,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(20153,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(22201,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(24249,16,FLEN)
NAN_BOXED(31424,16,FLEN)
NAN_BOXED(31247,16,FLEN)
NAN_BOXED(26297,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 86*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

101439
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b15-01.S
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File diff suppressed because it is too large Load diff

2174
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b16-01.S
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File diff suppressed because it is too large Load diff

2174
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b17-01.S
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File diff suppressed because it is too large Load diff

2989
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b18-01.S
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File diff suppressed because it is too large Load diff

1369
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b2-01.S
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File diff suppressed because it is too large Load diff

11409
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b3-01.S
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File diff suppressed because it is too large Load diff

1574
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b4-01.S
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File diff suppressed because it is too large Load diff

2374
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b5-01.S
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File diff suppressed because it is too large Load diff

499
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b6-01.S
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@ -1,499 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Tue Jan 30 08:43:40 2024 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmadd.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmadd_b6 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmadd_b6)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f30, rs2==f29, rs3==f29, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f29; dest:f31; op1val:0x0; op2val:0xfbff;
op3val:0xfbff; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f29, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f29, rs2==f31, rs3==f30, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f29; op2:f31; op3:f30; dest:f29; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, f29, f29, f31, f30, dyn, 32, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_2:
// rs1 == rs2 == rs3 != rd, rs1==f28, rs2==f28, rs3==f28, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f28; op2:f28; op3:f28; dest:f30; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, f30, f28, f28, f28, dyn, 64, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_3:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f27, rs2==f27, rs3==f31, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f27; op2:f27; op3:f31; dest:f28; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f28, f27, f27, f31, dyn, 96, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_4:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f26, rs2==f30, rs3==f26, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f26; op2:f30; op3:f26; dest:f27; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, f27, f26, f30, f26, dyn, 128, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_5:
// rd == rs2 == rs3 != rs1, rs1==f31, rs2==f25, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f31; op2:f25; op3:f25; dest:f25; op1val:0x0; op2val:0x7bff;
op3val:0x7bff; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f25, f31, f25, f25, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_6:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f25, rs2==f24, rs3==f27, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f25; op2:f24; op3:f27; dest:f26; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmadd.h, f26, f25, f24, f27, dyn, 32, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_7:
// rs1 == rs2 == rs3 == rd, rs1==f23, rs2==f23, rs3==f23, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f23; op2:f23; op3:f23; dest:f23; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, f23, f23, f23, f23, dyn, 64, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_8:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f22, rs2==f26, rs3==f24, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f22; op2:f26; op3:f24; dest:f24; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f24, f22, f26, f24, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_9:
// rs1 == rs2 == rd != rs3, rs1==f21, rs2==f21, rs3==f22, rd==f21,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f21; op2:f21; op3:f22; dest:f21; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, f21, f21, f21, f22, dyn, 128, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_10:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f24, rs2==f22, rs3==f21, rd==f22,
/* opcode: fmadd.h ; op1:f24; op2:f22; op3:f21; dest:f22; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f22, f24, f22, f21, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_11:
// rs1 == rd == rs3 != rs2, rs1==f20, rs2==f19, rs3==f20, rd==f20,
/* opcode: fmadd.h ; op1:f20; op2:f19; op3:f20; dest:f20; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f20, f20, f19, f20, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f18, rs2==f20, rs3==f17, rd==f19,
/* opcode: fmadd.h ; op1:f18; op2:f20; op3:f17; dest:f19; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f19, f18, f20, f17, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f19, rs2==f17, rs3==f16, rd==f18,
/* opcode: fmadd.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f18, f19, f17, f16, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f16, rs2==f18, rs3==f19, rd==f17,
/* opcode: fmadd.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f17, f16, f18, f19, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f17, rs2==f15, rs3==f18, rd==f16,
/* opcode: fmadd.h ; op1:f17; op2:f15; op3:f18; dest:f16; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f16, f17, f15, f18, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f14, rs2==f16, rs3==f13, rd==f15,
/* opcode: fmadd.h ; op1:f14; op2:f16; op3:f13; dest:f15; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f15, f14, f16, f13, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f15, rs2==f13, rs3==f12, rd==f14,
/* opcode: fmadd.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f14, f15, f13, f12, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rs2==f14, rs3==f15, rd==f13,
/* opcode: fmadd.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f13, f12, f14, f15, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f13, rs2==f11, rs3==f14, rd==f12,
/* opcode: fmadd.h ; op1:f13; op2:f11; op3:f14; dest:f12; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f12, f13, f11, f14, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f10, rs2==f12, rs3==f9, rd==f11,
/* opcode: fmadd.h ; op1:f10; op2:f12; op3:f9; dest:f11; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f11, f10, f12, f9, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f11, rs2==f9, rs3==f8, rd==f10,
/* opcode: fmadd.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f10, f11, f9, f8, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f8, rs2==f10, rs3==f11, rd==f9,
/* opcode: fmadd.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f9, f8, f10, f11, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f9, rs2==f7, rs3==f10, rd==f8,
/* opcode: fmadd.h ; op1:f9; op2:f7; op3:f10; dest:f8; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f8, f9, f7, f10, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f6, rs2==f8, rs3==f5, rd==f7,
/* opcode: fmadd.h ; op1:f6; op2:f8; op3:f5; dest:f7; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f7, f6, f8, f5, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f7, rs2==f5, rs3==f4, rd==f6,
/* opcode: fmadd.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f6, f7, f5, f4, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f4, rs2==f6, rs3==f7, rd==f5,
/* opcode: fmadd.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f5, f4, f6, f7, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f5, rs2==f3, rs3==f6, rd==f4,
/* opcode: fmadd.h ; op1:f5; op2:f3; op3:f6; dest:f4; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f4, f5, f3, f6, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f2, rs2==f4, rs3==f1, rd==f3,
/* opcode: fmadd.h ; op1:f2; op2:f4; op3:f1; dest:f3; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f3, f2, f4, f1, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f3, rs2==f1, rs3==f0, rd==f2,
/* opcode: fmadd.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f2, f3, f1, f0, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f0, rs2==f2, rs3==f3, rd==f1,
/* opcode: fmadd.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f1, f0, f2, f3, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f1,
/* opcode: fmadd.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f1, f30, f29, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)
inst_32:
// rs2==f0,
/* opcode: fmadd.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f0, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
inst_33:
// rs3==f2,
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f2; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f2, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)
inst_34:
// rd==f0,
/* opcode: fmadd.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f0, f31, f30, f29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 64, 0, x3, 108*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 111*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
inst_39:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 64, 0, x3, 117*FLEN/8, x4, x1, x2)
inst_40:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 128, 0, x3, 120*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 82*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

729
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b7-01.S
View file

@ -1,729 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Tue Jan 30 08:43:40 2024 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmadd.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmadd.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmadd_b7 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmadd_b7)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f30, rs2==f29, rs3==f29, rd==f31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f29; dest:f31; op1val:0x78fb; op2val:0xbcc3;
op3val:0xbcc3; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f29, dyn, 96, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f29, rs2==f31, rs3==f30, rd==f29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25b and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0bd and fs3 == 0 and fe3 == 0x1e and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f29; op2:f31; op3:f30; dest:f29; op1val:0x7a5b; op2val:0xbcbd;
op3val:0x7b89; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f29, f29, f31, f30, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_2:
// rs1 == rs2 == rs3 != rd, rs1==f28, rs2==f28, rs3==f28, rd==f30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f28; op2:f28; op3:f28; dest:f30; op1val:0x79ea; op2val:0x79ea;
op3val:0x79ea; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f30, f28, f28, f28, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_3:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f27, rs2==f27, rs3==f31, rd==f28,fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f27; op2:f27; op3:f31; dest:f28; op1val:0x676c; op2val:0x676c;
op3val:0x7772; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f28, f27, f27, f31, dyn, 96, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_4:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f26, rs2==f30, rs3==f26, rd==f27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f26; op2:f30; op3:f26; dest:f27; op1val:0x7b8b; op2val:0xb980;
op3val:0x7b8b; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f27, f26, f30, f26, dyn, 96, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_5:
// rd == rs2 == rs3 != rs1, rs1==f31, rs2==f25, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f31; op2:f25; op3:f25; dest:f25; op1val:0x7b34; op2val:0xb005;
op3val:0xb005; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f25, f31, f25, f25, dyn, 96, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_6:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f25, rs2==f24, rs3==f27, rd==f26,fs1 == 0 and fe1 == 0x1d and fm1 == 0x380 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x034 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3e3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f25; op2:f24; op3:f27; dest:f26; op1val:0x7780; op2val:0xb834;
op3val:0x73e3; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f26, f25, f24, f27, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_7:
// rs1 == rs2 == rs3 == rd, rs1==f23, rs2==f23, rs3==f23, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f23; op2:f23; op3:f23; dest:f23; op1val:0x7859; op2val:0x7859;
op3val:0x7859; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f23, f23, f23, f23, dyn, 96, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_8:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f22, rs2==f26, rs3==f24, rd==f24,fs1 == 0 and fe1 == 0x18 and fm1 == 0x2b8 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x020 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2ee and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f22; op2:f26; op3:f24; dest:f24; op1val:0x62b8; op2val:0xcc20;
op3val:0x72ee; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f24, f22, f26, f24, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_9:
// rs1 == rs2 == rd != rs3, rs1==f21, rs2==f21, rs3==f22, rd==f21,fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f21; op2:f21; op3:f22; dest:f21; op1val:0x7478; op2val:0x7478;
op3val:0x7b53; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f21, f21, f21, f22, dyn, 96, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_10:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f24, rs2==f22, rs3==f21, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x2ab and fs3 == 0 and fe3 == 0x1c and fm3 == 0x11a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f24; op2:f22; op3:f21; dest:f22; op1val:0x7a1f; op2val:0xb2ab;
op3val:0x711a; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f22, f24, f22, f21, dyn, 96, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_11:
// rs1 == rd == rs3 != rs2, rs1==f20, rs2==f19, rs3==f20, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f20; op2:f19; op3:f20; dest:f20; op1val:0x7a5f; op2val:0xb192;
op3val:0x7a5f; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f20, f20, f19, f20, dyn, 96, 0, x3, 33*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f18, rs2==f20, rs3==f17, rd==f19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0ef and fs2 == 1 and fe2 == 0x0c and fm2 == 0x291 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x00d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f18; op2:f20; op3:f17; dest:f19; op1val:0x78ef; op2val:0xb291;
op3val:0x700d; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f19, f18, f20, f17, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f19, rs2==f17, rs3==f16, rd==f18,fs1 == 0 and fe1 == 0x15 and fm1 == 0x354 and fs2 == 1 and fe2 == 0x17 and fm2 == 0x39b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x5754; op2val:0xdf9b;
op3val:0x7af7; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f18, f19, f17, f16, dyn, 96, 0, x3, 39*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f16, rs2==f18, rs3==f19, rd==f17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x2b3 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01d and fs3 == 0 and fe3 == 0x1c and fm3 == 0x2e4 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x72b3; op2val:0xbc1d;
op3val:0x72e4; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f17, f16, f18, f19, dyn, 96, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f17, rs2==f15, rs3==f18, rd==f16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3db and fs2 == 1 and fe2 == 0x0e and fm2 == 0x31a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f9 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f17; op2:f15; op3:f18; dest:f16; op1val:0x7bdb; op2val:0xbb1a;
op3val:0x7af9; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f16, f17, f15, f18, dyn, 96, 0, x3, 45*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f14, rs2==f16, rs3==f13, rd==f15,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x2a5 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f14; op2:f16; op3:f13; dest:f15; op1val:0x74a0; op2val:0xc2a5;
op3val:0x7bb0; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f15, f14, f16, f13, dyn, 96, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f15, rs2==f13, rs3==f12, rd==f14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x04f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x784f; op2val:0xbd07;
op3val:0x796b; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f14, f15, f13, f12, dyn, 96, 0, x3, 51*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rs2==f14, rs3==f15, rd==f13,fs1 == 0 and fe1 == 0x1c and fm1 == 0x28c and fs2 == 1 and fe2 == 0x11 and fm2 == 0x098 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x386 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x728c; op2val:0xc498;
op3val:0x7b86; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f13, f12, f14, f15, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f13, rs2==f11, rs3==f14, rd==f12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x185 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x199 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ba and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f13; op2:f11; op3:f14; dest:f12; op1val:0x7985; op2val:0xbd99;
op3val:0x7bba; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f12, f13, f11, f14, dyn, 96, 0, x3, 57*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f10, rs2==f12, rs3==f9, rd==f11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x159 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0c7 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f10; op2:f12; op3:f9; dest:f11; op1val:0x7b25; op2val:0xb559;
op3val:0x74c7; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f11, f10, f12, f9, dyn, 96, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f11, rs2==f9, rs3==f8, rd==f10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1c6 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x35a and fs3 == 0 and fe3 == 0x1c and fm3 == 0x14e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x75c6; op2val:0xb75a;
op3val:0x714e; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f10, f11, f9, f8, dyn, 96, 0, x3, 63*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f8, rs2==f10, rs3==f11, rd==f9,fs1 == 0 and fe1 == 0x1c and fm1 == 0x0a9 and fs2 == 1 and fe2 == 0x0d and fm2 == 0x327 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x02a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x70a9; op2val:0xb727;
op3val:0x6c2a; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f9, f8, f10, f11, dyn, 96, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f9, rs2==f7, rs3==f10, rd==f8,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0d1 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x000 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0d2 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f9; op2:f7; op3:f10; dest:f8; op1val:0x74d1; op2val:0xc000;
op3val:0x78d2; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f8, f9, f7, f10, dyn, 96, 0, x3, 69*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f6, rs2==f8, rs3==f5, rd==f7,fs1 == 0 and fe1 == 0x16 and fm1 == 0x2f4 and fs2 == 1 and fe2 == 0x16 and fm2 == 0x23b and fs3 == 0 and fe3 == 0x1e and fm3 == 0x16b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f6; op2:f8; op3:f5; dest:f7; op1val:0x5af4; op2val:0xda3b;
op3val:0x796b; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f7, f6, f8, f5, dyn, 96, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f7, rs2==f5, rs3==f4, rd==f6,fs1 == 0 and fe1 == 0x1d and fm1 == 0x167 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0f5 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x7567; op2val:0xbb56;
op3val:0x74f5; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f6, f7, f5, f4, dyn, 96, 0, x3, 75*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f4, rs2==f6, rs3==f7, rd==f5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x28b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0b2 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x7a8b; op2val:0xb8b2;
op3val:0x77b0; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f5, f4, f6, f7, dyn, 96, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f5, rs2==f3, rs3==f6, rd==f4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x10c and fs2 == 1 and fe2 == 0x0f and fm2 == 0x218 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3b2 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f5; op2:f3; op3:f6; dest:f4; op1val:0x750c; op2val:0xbe18;
op3val:0x77b2; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f4, f5, f3, f6, dyn, 96, 0, x3, 81*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f2, rs2==f4, rs3==f1, rd==f3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1a2 and fs2 == 1 and fe2 == 0x0b and fm2 == 0x12d and fs3 == 0 and fe3 == 0x1a and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f2; op2:f4; op3:f1; dest:f3; op1val:0x79a2; op2val:0xad2d;
op3val:0x6b4b; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f3, f2, f4, f1, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f3, rs2==f1, rs3==f0, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3cc and fs2 == 1 and fe2 == 0x09 and fm2 == 0x201 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x1da and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x7bcc; op2val:0xa601;
op3val:0x65da; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f2, f3, f1, f0, dyn, 96, 0, x3, 87*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f0, rs2==f2, rs3==f3, rd==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1fe and fs2 == 1 and fe2 == 0x0f and fm2 == 0x081 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2c1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x79fe; op2val:0xbc81;
op3val:0x7ac1; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f1, f0, f2, f3, dyn, 96, 0, x3, 90*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f1,fs1 == 0 and fe1 == 0x19 and fm1 == 0x0a0 and fs2 == 1 and fe2 == 0x14 and fm2 == 0x172 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x24c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x64a0; op2val:0xd172;
op3val:0x7a4c; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f1, f30, f29, dyn, 96, 0, x3, 93*FLEN/8, x4, x1, x2)
inst_32:
// rs2==f0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1db and fs2 == 1 and fe2 == 0x0f and fm2 == 0x251 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x75db; op2val:0xbe51;
op3val:0x78a0; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f0, f29, dyn, 96, 0, x3, 96*FLEN/8, x4, x1, x2)
inst_33:
// rs3==f2,fs1 == 0 and fe1 == 0x18 and fm1 == 0x0a7 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x123 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1fa and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f2; dest:f31; op1val:0x60a7; op2val:0xc523;
op3val:0x69fa; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f2, dyn, 96, 0, x3, 99*FLEN/8, x4, x1, x2)
inst_34:
// rd==f0,fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x147 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3a3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x71c9; op2val:0xc547;
op3val:0x7ba3; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f0, f31, f30, f29, dyn, 96, 0, x3, 102*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x249 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7249; op2val:0xc3b0;
op3val:0x7a0b; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 105*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x36f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x00d and fs3 == 0 and fe3 == 0x1e and fm3 == 0x388 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b6f; op2val:0xbc0d;
op3val:0x7b88; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 108*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x181 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x01e and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1ac and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7581; op2val:0xbc1e;
op3val:0x75ac; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 111*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x032 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1e9 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x233 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7832; op2val:0xbde9;
op3val:0x7a33; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 114*FLEN/8, x4, x1, x2)
inst_39:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2e9 and fs2 == 1 and fe2 == 0x11 and fm2 == 0x2ec and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1fb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6ee9; op2val:0xc6ec;
op3val:0x79fb; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 117*FLEN/8, x4, x1, x2)
inst_40:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0f and fm2 == 0x050 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2df and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a5f; op2val:0xbc50;
op3val:0x7adf; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 120*FLEN/8, x4, x1, x2)
inst_41:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x0b0 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x273 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x390 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x68b0; op2val:0xce73;
op3val:0x7b90; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 123*FLEN/8, x4, x1, x2)
inst_42:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x1d5 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x373 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x173 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6dd5; op2val:0xc373;
op3val:0x7573; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 126*FLEN/8, x4, x1, x2)
inst_43:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0e2 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x201 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x357 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78e2; op2val:0xbe01;
op3val:0x7b57; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 129*FLEN/8, x4, x1, x2)
inst_44:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x16f and fs2 == 1 and fe2 == 0x10 and fm2 == 0x16e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x363 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x756f; op2val:0xc16e;
op3val:0x7b63; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 132*FLEN/8, x4, x1, x2)
inst_45:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x05b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x092 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x785b; op2val:0xb892;
op3val:0x74ff; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 135*FLEN/8, x4, x1, x2)
inst_46:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x111 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x075 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x1ad and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7511; op2val:0xb875;
op3val:0x71ad; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 138*FLEN/8, x4, x1, x2)
inst_47:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x100 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x390 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0c3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d00; op2val:0xbf90;
op3val:0x70c3; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 141*FLEN/8, x4, x1, x2)
inst_48:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x182 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f8 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7982; op2val:0xbdc7;
op3val:0x7bf8; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 144*FLEN/8, x4, x1, x2)
inst_49:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x12a and fs2 == 1 and fe2 == 0x0d and fm2 == 0x0cf and fs3 == 0 and fe3 == 0x1a and fm3 == 0x236 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x712a; op2val:0xb4cf;
op3val:0x6a36; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 147*FLEN/8, x4, x1, x2)
inst_50:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3e3 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x053 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x044 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7be3; op2val:0xb853;
op3val:0x7844; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 150*FLEN/8, x4, x1, x2)
inst_51:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x27d and fs2 == 1 and fe2 == 0x0e and fm2 == 0x0ad and fs3 == 0 and fe3 == 0x1c and fm3 == 0x397 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x767d; op2val:0xb8ad;
op3val:0x7397; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 153*FLEN/8, x4, x1, x2)
inst_52:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0bf and fs2 == 1 and fe2 == 0x0f and fm2 == 0x190 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78bf; op2val:0xbd90;
op3val:0x7a9b; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 156*FLEN/8, x4, x1, x2)
inst_53:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x349 and fs2 == 1 and fe2 == 0x0e and fm2 == 0x367 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2be and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7749; op2val:0xbb67;
op3val:0x76be; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 159*FLEN/8, x4, x1, x2)
inst_54:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x320 and fs2 == 1 and fe2 == 0x13 and fm2 == 0x01c and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6b20; op2val:0xcc1c;
op3val:0x7b53; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 162*FLEN/8, x4, x1, x2)
inst_55:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x030 and fs2 == 1 and fe2 == 0x12 and fm2 == 0x389 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3e4 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6830; op2val:0xcb89;
op3val:0x77e4; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 165*FLEN/8, x4, x1, x2)
inst_56:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0c3 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x1ee and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78fb; op2val:0xbcc3;
op3val:0x79ee; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 168*FLEN/8, x4, x1, x2)
inst_57:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1ea and fs2 == 1 and fe2 == 0x0f and fm2 == 0x0fc and fs3 == 0 and fe3 == 0x1e and fm3 == 0x360 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x79ea; op2val:0xbcfc;
op3val:0x7b60; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 171*FLEN/8, x4, x1, x2)
inst_58:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x36c and fs2 == 1 and fe2 == 0x13 and fm2 == 0x002 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x372 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x676c; op2val:0xcc02;
op3val:0x7772; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 174*FLEN/8, x4, x1, x2)
inst_59:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x38b and fs2 == 1 and fe2 == 0x0e and fm2 == 0x180 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x130 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b8b; op2val:0xb980;
op3val:0x7930; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 177*FLEN/8, x4, x1, x2)
inst_60:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x334 and fs2 == 1 and fe2 == 0x0c and fm2 == 0x005 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x33e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b34; op2val:0xb005;
op3val:0x6f3e; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 180*FLEN/8, x4, x1, x2)
inst_61:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x059 and fs2 == 1 and fe2 == 0x0f and fm2 == 0x038 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x096 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7859; op2val:0xbc38;
op3val:0x7896; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 183*FLEN/8, x4, x1, x2)
inst_62:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x078 and fs2 == 1 and fe2 == 0x10 and fm2 == 0x28e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x353 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7478; op2val:0xc28e;
op3val:0x7b53; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 186*FLEN/8, x4, x1, x2)
inst_63:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x25f and fs2 == 1 and fe2 == 0x0c and fm2 == 0x192 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x070 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmadd.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a5f; op2val:0xb192;
op3val:0x7070; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmadd.h, f31, f30, f29, f28, dyn, 96, 0, x3, 189*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(48323,16,FLEN)
NAN_BOXED(48323,16,FLEN)
NAN_BOXED(31323,16,FLEN)
NAN_BOXED(48317,16,FLEN)
NAN_BOXED(31625,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(26476,16,FLEN)
NAN_BOXED(26476,16,FLEN)
NAN_BOXED(30578,16,FLEN)
NAN_BOXED(31627,16,FLEN)
NAN_BOXED(47488,16,FLEN)
NAN_BOXED(31627,16,FLEN)
NAN_BOXED(31540,16,FLEN)
NAN_BOXED(45061,16,FLEN)
NAN_BOXED(45061,16,FLEN)
NAN_BOXED(30592,16,FLEN)
NAN_BOXED(47156,16,FLEN)
NAN_BOXED(29667,16,FLEN)
NAN_BOXED(30809,16,FLEN)
NAN_BOXED(30809,16,FLEN)
NAN_BOXED(30809,16,FLEN)
NAN_BOXED(25272,16,FLEN)
NAN_BOXED(52256,16,FLEN)
NAN_BOXED(29422,16,FLEN)
NAN_BOXED(29816,16,FLEN)
NAN_BOXED(29816,16,FLEN)
NAN_BOXED(31571,16,FLEN)
NAN_BOXED(31263,16,FLEN)
NAN_BOXED(45739,16,FLEN)
NAN_BOXED(28954,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(45458,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(30959,16,FLEN)
NAN_BOXED(45713,16,FLEN)
NAN_BOXED(28685,16,FLEN)
NAN_BOXED(22356,16,FLEN)
NAN_BOXED(57243,16,FLEN)
NAN_BOXED(31479,16,FLEN)
NAN_BOXED(29363,16,FLEN)
NAN_BOXED(48157,16,FLEN)
NAN_BOXED(29412,16,FLEN)
NAN_BOXED(31707,16,FLEN)
NAN_BOXED(47898,16,FLEN)
NAN_BOXED(31481,16,FLEN)
NAN_BOXED(29856,16,FLEN)
NAN_BOXED(49829,16,FLEN)
NAN_BOXED(31664,16,FLEN)
NAN_BOXED(30799,16,FLEN)
NAN_BOXED(48391,16,FLEN)
NAN_BOXED(31083,16,FLEN)
NAN_BOXED(29324,16,FLEN)
NAN_BOXED(50328,16,FLEN)
NAN_BOXED(31622,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(48537,16,FLEN)
NAN_BOXED(31674,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(46425,16,FLEN)
NAN_BOXED(29895,16,FLEN)
NAN_BOXED(30150,16,FLEN)
NAN_BOXED(46938,16,FLEN)
NAN_BOXED(29006,16,FLEN)
NAN_BOXED(28841,16,FLEN)
NAN_BOXED(46887,16,FLEN)
NAN_BOXED(27690,16,FLEN)
NAN_BOXED(29905,16,FLEN)
NAN_BOXED(49152,16,FLEN)
NAN_BOXED(30930,16,FLEN)
NAN_BOXED(23284,16,FLEN)
NAN_BOXED(55867,16,FLEN)
NAN_BOXED(31083,16,FLEN)
NAN_BOXED(30055,16,FLEN)
NAN_BOXED(47958,16,FLEN)
NAN_BOXED(29941,16,FLEN)
NAN_BOXED(31371,16,FLEN)
NAN_BOXED(47282,16,FLEN)
NAN_BOXED(30640,16,FLEN)
NAN_BOXED(29964,16,FLEN)
NAN_BOXED(48664,16,FLEN)
NAN_BOXED(30642,16,FLEN)
NAN_BOXED(31138,16,FLEN)
NAN_BOXED(44333,16,FLEN)
NAN_BOXED(27467,16,FLEN)
NAN_BOXED(31692,16,FLEN)
NAN_BOXED(42497,16,FLEN)
NAN_BOXED(26074,16,FLEN)
NAN_BOXED(31230,16,FLEN)
NAN_BOXED(48257,16,FLEN)
NAN_BOXED(31425,16,FLEN)
NAN_BOXED(25760,16,FLEN)
NAN_BOXED(53618,16,FLEN)
NAN_BOXED(31308,16,FLEN)
NAN_BOXED(30171,16,FLEN)
NAN_BOXED(48721,16,FLEN)
NAN_BOXED(30880,16,FLEN)
NAN_BOXED(24743,16,FLEN)
NAN_BOXED(50467,16,FLEN)
NAN_BOXED(27130,16,FLEN)
NAN_BOXED(29129,16,FLEN)
NAN_BOXED(50503,16,FLEN)
NAN_BOXED(31651,16,FLEN)
NAN_BOXED(29257,16,FLEN)
NAN_BOXED(50096,16,FLEN)
NAN_BOXED(31243,16,FLEN)
NAN_BOXED(31599,16,FLEN)
NAN_BOXED(48141,16,FLEN)
NAN_BOXED(31624,16,FLEN)
NAN_BOXED(30081,16,FLEN)
NAN_BOXED(48158,16,FLEN)
NAN_BOXED(30124,16,FLEN)
NAN_BOXED(30770,16,FLEN)
NAN_BOXED(48617,16,FLEN)
NAN_BOXED(31283,16,FLEN)
NAN_BOXED(28393,16,FLEN)
NAN_BOXED(50924,16,FLEN)
NAN_BOXED(31227,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(48208,16,FLEN)
NAN_BOXED(31455,16,FLEN)
NAN_BOXED(26800,16,FLEN)
NAN_BOXED(52851,16,FLEN)
NAN_BOXED(31632,16,FLEN)
NAN_BOXED(28117,16,FLEN)
NAN_BOXED(50035,16,FLEN)
NAN_BOXED(30067,16,FLEN)
NAN_BOXED(30946,16,FLEN)
NAN_BOXED(48641,16,FLEN)
NAN_BOXED(31575,16,FLEN)
NAN_BOXED(30063,16,FLEN)
NAN_BOXED(49518,16,FLEN)
NAN_BOXED(31587,16,FLEN)
NAN_BOXED(30811,16,FLEN)
NAN_BOXED(47250,16,FLEN)
NAN_BOXED(29951,16,FLEN)
NAN_BOXED(29969,16,FLEN)
NAN_BOXED(47221,16,FLEN)
NAN_BOXED(29101,16,FLEN)
NAN_BOXED(27904,16,FLEN)
NAN_BOXED(49040,16,FLEN)
NAN_BOXED(28867,16,FLEN)
NAN_BOXED(31106,16,FLEN)
NAN_BOXED(48583,16,FLEN)
NAN_BOXED(31736,16,FLEN)
NAN_BOXED(28970,16,FLEN)
NAN_BOXED(46287,16,FLEN)
NAN_BOXED(27190,16,FLEN)
NAN_BOXED(31715,16,FLEN)
NAN_BOXED(47187,16,FLEN)
NAN_BOXED(30788,16,FLEN)
NAN_BOXED(30333,16,FLEN)
NAN_BOXED(47277,16,FLEN)
NAN_BOXED(29591,16,FLEN)
NAN_BOXED(30911,16,FLEN)
NAN_BOXED(48528,16,FLEN)
NAN_BOXED(31387,16,FLEN)
NAN_BOXED(30537,16,FLEN)
NAN_BOXED(47975,16,FLEN)
NAN_BOXED(30398,16,FLEN)
NAN_BOXED(27424,16,FLEN)
NAN_BOXED(52252,16,FLEN)
NAN_BOXED(31571,16,FLEN)
NAN_BOXED(26672,16,FLEN)
NAN_BOXED(52105,16,FLEN)
NAN_BOXED(30692,16,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(48323,16,FLEN)
NAN_BOXED(31214,16,FLEN)
NAN_BOXED(31210,16,FLEN)
NAN_BOXED(48380,16,FLEN)
NAN_BOXED(31584,16,FLEN)
NAN_BOXED(26476,16,FLEN)
NAN_BOXED(52226,16,FLEN)
NAN_BOXED(30578,16,FLEN)
NAN_BOXED(31627,16,FLEN)
NAN_BOXED(47488,16,FLEN)
NAN_BOXED(31024,16,FLEN)
NAN_BOXED(31540,16,FLEN)
NAN_BOXED(45061,16,FLEN)
NAN_BOXED(28478,16,FLEN)
NAN_BOXED(30809,16,FLEN)
NAN_BOXED(48184,16,FLEN)
NAN_BOXED(30870,16,FLEN)
NAN_BOXED(29816,16,FLEN)
NAN_BOXED(49806,16,FLEN)
NAN_BOXED(31571,16,FLEN)
NAN_BOXED(31327,16,FLEN)
NAN_BOXED(45458,16,FLEN)
NAN_BOXED(28784,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 128*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmadd_b8-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmax_b1-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmax_b19-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmin_b1-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmin_b19-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b1-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b14-01.S
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@ -1,519 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Tue Jan 30 08:43:45 2024 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmsub.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmsub_b14 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmsub_b14)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd == rs3 != rs2, rs1==f31, rs2==f30, rs3==f31, rd==f31,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f31; op2:f30; op3:f31; dest:f31; op1val:0x704c; op2val:0x7ac6;
op3val:0x704c; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f31, f30, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f30, rs2==f31, rs3==f29, rd==f30,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x10 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f31; op3:f29; dest:f30; op1val:0x704c; op2val:0x7ac6;
op3val:0x421b; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f30, f30, f31, f29, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_2:
// rd == rs2 == rs3 != rs1, rs1==f29, rs2==f28, rs3==f28, rd==f28,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f29; op2:f28; op3:f28; dest:f28; op1val:0x704c; op2val:0x7ac6;
op3val:0x7ac6; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f28, f29, f28, f28, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_3:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f28, rs2==f29, rs3==f27, rd==f27,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x12 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f28; op2:f29; op3:f27; dest:f27; op1val:0x704c; op2val:0x7ac6;
op3val:0x4a1b; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f27, f28, f29, f27, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_4:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f27, rs2==f26, rs3==f30, rd==f26,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x13 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f27; op2:f26; op3:f30; dest:f26; op1val:0x704c; op2val:0x7ac6;
op3val:0x4e1b; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f26, f27, f26, f30, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_5:
// rs1 == rs2 == rs3 == rd, rs1==f25, rs2==f25, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f25; op2:f25; op3:f25; dest:f25; op1val:0x704c; op2val:0x704c;
op3val:0x704c; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f25, f25, f25, f25, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_6:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f26, rs2==f24, rs3==f24, rd==f29,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x15 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f26; op2:f24; op3:f24; dest:f29; op1val:0x704c; op2val:0x7ac6;
op3val:0x7ac6; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f29, f26, f24, f24, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_7:
// rs1 == rs2 == rd != rs3, rs1==f23, rs2==f23, rs3==f26, rd==f23,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f23; op2:f23; op3:f26; dest:f23; op1val:0x704c; op2val:0x704c;
op3val:0x5a1b; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f23, f23, f23, f26, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_8:
// rs1 == rs2 == rs3 != rd, rs1==f22, rs2==f22, rs3==f22, rd==f24,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f22; op2:f22; op3:f22; dest:f24; op1val:0x704c; op2val:0x704c;
op3val:0x704c; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f24, f22, f22, f22, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_9:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f21, rs2==f21, rs3==f23, rd==f22,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f21; op2:f21; op3:f23; dest:f22; op1val:0x704c; op2val:0x704c;
op3val:0x621b; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f22, f21, f21, f23, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_10:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f20, rs2==f27, rs3==f20, rd==f21,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f20; op2:f27; op3:f20; dest:f21; op1val:0x704c; op2val:0x7ac6;
op3val:0x704c; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f21, f20, f27, f20, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_11:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f24, rs2==f19, rs3==f21, rd==f20,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x1a and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f24; op2:f19; op3:f21; dest:f20; op1val:0x704c; op2val:0x7ac6;
op3val:0x6a1b; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f20, f24, f19, f21, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f18, rs2==f20, rs3==f17, rd==f19,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f18; op2:f20; op3:f17; dest:f19; op1val:0x704c; op2val:0x7ac6;
op3val:0x6e1b; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f19, f18, f20, f17, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f19, rs2==f17, rs3==f16, rd==f18,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x704c; op2val:0x7ac6;
op3val:0x721b; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f18, f19, f17, f16, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f16, rs2==f18, rs3==f19, rd==f17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x704c; op2val:0x7ac6;
op3val:0x761b; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f17, f16, f18, f19, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f17, rs2==f15, rs3==f18, rd==f16,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f17; op2:f15; op3:f18; dest:f16; op1val:0x704c; op2val:0x7ac6;
op3val:0x7a1b; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f16, f17, f15, f18, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f14, rs2==f16, rs3==f13, rd==f15,fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f14; op2:f16; op3:f13; dest:f15; op1val:0x704c; op2val:0x7ac6;
op3val:0x7bff; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f15, f14, f16, f13, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f15, rs2==f13, rs3==f12, rd==f14,
/* opcode: fmsub.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f14, f15, f13, f12, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rs2==f14, rs3==f15, rd==f13,
/* opcode: fmsub.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f13, f12, f14, f15, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f13, rs2==f11, rs3==f14, rd==f12,
/* opcode: fmsub.h ; op1:f13; op2:f11; op3:f14; dest:f12; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f12, f13, f11, f14, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f10, rs2==f12, rs3==f9, rd==f11,
/* opcode: fmsub.h ; op1:f10; op2:f12; op3:f9; dest:f11; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f11, f10, f12, f9, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f11, rs2==f9, rs3==f8, rd==f10,
/* opcode: fmsub.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f10, f11, f9, f8, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f8, rs2==f10, rs3==f11, rd==f9,
/* opcode: fmsub.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f9, f8, f10, f11, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f9, rs2==f7, rs3==f10, rd==f8,
/* opcode: fmsub.h ; op1:f9; op2:f7; op3:f10; dest:f8; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f8, f9, f7, f10, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f6, rs2==f8, rs3==f5, rd==f7,
/* opcode: fmsub.h ; op1:f6; op2:f8; op3:f5; dest:f7; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f7, f6, f8, f5, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f7, rs2==f5, rs3==f4, rd==f6,
/* opcode: fmsub.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f6, f7, f5, f4, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f4, rs2==f6, rs3==f7, rd==f5,
/* opcode: fmsub.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f5, f4, f6, f7, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f5, rs2==f3, rs3==f6, rd==f4,
/* opcode: fmsub.h ; op1:f5; op2:f3; op3:f6; dest:f4; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f4, f5, f3, f6, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f2, rs2==f4, rs3==f1, rd==f3,
/* opcode: fmsub.h ; op1:f2; op2:f4; op3:f1; dest:f3; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f3, f2, f4, f1, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f3, rs2==f1, rs3==f0, rd==f2,
/* opcode: fmsub.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f2, f3, f1, f0, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f0, rs2==f2, rs3==f3, rd==f1,
/* opcode: fmsub.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f1, f0, f2, f3, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f1,
/* opcode: fmsub.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f1, f30, f29, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)
inst_32:
// rs2==f0,
/* opcode: fmsub.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f0, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
inst_33:
// rs3==f2,
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f2; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f2, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)
inst_34:
// rd==f0,
/* opcode: fmsub.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f0, f31, f30, f29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x0f and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x7ac6;
op3val:0x3e1b; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 105*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x11 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x7ac6;
op3val:0x461b; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x14 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x7ac6;
op3val:0x521b; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 111*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x15 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x7ac6;
op3val:0x561b; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 114*FLEN/8, x4, x1, x2)
inst_39:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x16 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x7ac6;
op3val:0x5a1b; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 117*FLEN/8, x4, x1, x2)
inst_40:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x17 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x7ac6;
op3val:0x5e1b; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 120*FLEN/8, x4, x1, x2)
inst_41:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x18 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x7ac6;
op3val:0x621b; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 123*FLEN/8, x4, x1, x2)
inst_42:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x04c and fs2 == 0 and fe2 == 0x1e and fm2 == 0x2c6 and fs3 == 0 and fe3 == 0x19 and fm3 == 0x21b and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x704c; op2val:0x7ac6;
op3val:0x661b; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 126*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(16923,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(18971,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(19995,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(23067,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(25115,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(27163,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(28187,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(29211,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(30235,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(31259,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(15899,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(17947,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(21019,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(22043,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(23067,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(24091,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(25115,16,FLEN)
NAN_BOXED(28748,16,FLEN)
NAN_BOXED(31430,16,FLEN)
NAN_BOXED(26139,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 86*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

101459
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b15-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b16-01.S
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2174
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b17-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b18-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b2-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b3-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b4-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b5-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b6-01.S
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@ -1,499 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Tue Jan 30 08:43:45 2024 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmsub.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmsub_b6 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmsub_b6)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd == rs3 != rs2, rs1==f31, rs2==f30, rs3==f31, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f31; op2:f30; op3:f31; dest:f31; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f31, f30, f31, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f30, rs2==f31, rs3==f29, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f31; op3:f29; dest:f30; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f30, f30, f31, f29, dyn, 32, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_2:
// rd == rs2 == rs3 != rs1, rs1==f29, rs2==f28, rs3==f28, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f29; op2:f28; op3:f28; dest:f28; op1val:0x0; op2val:0xfbff;
op3val:0xfbff; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f28, f29, f28, f28, dyn, 64, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_3:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f28, rs2==f29, rs3==f27, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f28; op2:f29; op3:f27; dest:f27; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f27, f28, f29, f27, dyn, 96, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_4:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f27, rs2==f26, rs3==f30, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f27; op2:f26; op3:f30; dest:f26; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f26, f27, f26, f30, dyn, 128, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_5:
// rs1 == rs2 == rs3 == rd, rs1==f25, rs2==f25, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f25; op2:f25; op3:f25; dest:f25; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f25, f25, f25, f25, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_6:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f26, rs2==f24, rs3==f24, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f26; op2:f24; op3:f24; dest:f29; op1val:0x0; op2val:0x7bff;
op3val:0x7bff; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f29, f26, f24, f24, dyn, 32, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_7:
// rs1 == rs2 == rd != rs3, rs1==f23, rs2==f23, rs3==f26, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f23; op2:f23; op3:f26; dest:f23; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f23, f23, f23, f26, dyn, 64, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_8:
// rs1 == rs2 == rs3 != rd, rs1==f22, rs2==f22, rs3==f22, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f22; op2:f22; op3:f22; dest:f24; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f24, f22, f22, f22, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_9:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f21, rs2==f21, rs3==f23, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f21; op2:f21; op3:f23; dest:f22; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f22, f21, f21, f23, dyn, 128, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_10:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f20, rs2==f27, rs3==f20, rd==f21,
/* opcode: fmsub.h ; op1:f20; op2:f27; op3:f20; dest:f21; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f21, f20, f27, f20, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_11:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f24, rs2==f19, rs3==f21, rd==f20,
/* opcode: fmsub.h ; op1:f24; op2:f19; op3:f21; dest:f20; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f20, f24, f19, f21, dyn, 0, 0, x3, 33*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f18, rs2==f20, rs3==f17, rd==f19,
/* opcode: fmsub.h ; op1:f18; op2:f20; op3:f17; dest:f19; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f19, f18, f20, f17, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f19, rs2==f17, rs3==f16, rd==f18,
/* opcode: fmsub.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f18, f19, f17, f16, dyn, 0, 0, x3, 39*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f16, rs2==f18, rs3==f19, rd==f17,
/* opcode: fmsub.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f17, f16, f18, f19, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f17, rs2==f15, rs3==f18, rd==f16,
/* opcode: fmsub.h ; op1:f17; op2:f15; op3:f18; dest:f16; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f16, f17, f15, f18, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f14, rs2==f16, rs3==f13, rd==f15,
/* opcode: fmsub.h ; op1:f14; op2:f16; op3:f13; dest:f15; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f15, f14, f16, f13, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f15, rs2==f13, rs3==f12, rd==f14,
/* opcode: fmsub.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f14, f15, f13, f12, dyn, 0, 0, x3, 51*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rs2==f14, rs3==f15, rd==f13,
/* opcode: fmsub.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f13, f12, f14, f15, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f13, rs2==f11, rs3==f14, rd==f12,
/* opcode: fmsub.h ; op1:f13; op2:f11; op3:f14; dest:f12; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f12, f13, f11, f14, dyn, 0, 0, x3, 57*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f10, rs2==f12, rs3==f9, rd==f11,
/* opcode: fmsub.h ; op1:f10; op2:f12; op3:f9; dest:f11; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f11, f10, f12, f9, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f11, rs2==f9, rs3==f8, rd==f10,
/* opcode: fmsub.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f10, f11, f9, f8, dyn, 0, 0, x3, 63*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f8, rs2==f10, rs3==f11, rd==f9,
/* opcode: fmsub.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f9, f8, f10, f11, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f9, rs2==f7, rs3==f10, rd==f8,
/* opcode: fmsub.h ; op1:f9; op2:f7; op3:f10; dest:f8; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f8, f9, f7, f10, dyn, 0, 0, x3, 69*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f6, rs2==f8, rs3==f5, rd==f7,
/* opcode: fmsub.h ; op1:f6; op2:f8; op3:f5; dest:f7; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f7, f6, f8, f5, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f7, rs2==f5, rs3==f4, rd==f6,
/* opcode: fmsub.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f6, f7, f5, f4, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f4, rs2==f6, rs3==f7, rd==f5,
/* opcode: fmsub.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f5, f4, f6, f7, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f5, rs2==f3, rs3==f6, rd==f4,
/* opcode: fmsub.h ; op1:f5; op2:f3; op3:f6; dest:f4; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f4, f5, f3, f6, dyn, 0, 0, x3, 81*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f2, rs2==f4, rs3==f1, rd==f3,
/* opcode: fmsub.h ; op1:f2; op2:f4; op3:f1; dest:f3; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f3, f2, f4, f1, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f3, rs2==f1, rs3==f0, rd==f2,
/* opcode: fmsub.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f2, f3, f1, f0, dyn, 0, 0, x3, 87*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f0, rs2==f2, rs3==f3, rd==f1,
/* opcode: fmsub.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f1, f0, f2, f3, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f1,
/* opcode: fmsub.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f1, f30, f29, dyn, 0, 0, x3, 93*FLEN/8, x4, x1, x2)
inst_32:
// rs2==f0,
/* opcode: fmsub.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f0, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
inst_33:
// rs3==f2,
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f2; dest:f31; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f2, dyn, 0, 0, x3, 99*FLEN/8, x4, x1, x2)
inst_34:
// rd==f0,
/* opcode: fmsub.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x0; op2val:0x0;
op3val:0x0; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f0, f31, f30, f29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x0; op2val:0xfbff;
op3val:0x0; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 105*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:0 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 0, 0, x3, 108*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:32 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 32, 0, x3, 111*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:64 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 64, 0, x3, 114*FLEN/8, x4, x1, x2)
inst_39:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 117*FLEN/8, x4, x1, x2)
inst_40:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fs3 == 0 and fe3 == 0x00 and fm3 == 0x000 and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x0; op2val:0x7bff;
op3val:0x0; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:128 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 128, 0, x3, 120*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 82*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

729
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b7-01.S
View file

@ -1,729 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Tue Jan 30 08:43:45 2024 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmsub.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmsub.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmsub_b7 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmsub_b7)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd == rs3 != rs2, rs1==f31, rs2==f30, rs3==f31, rd==f31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f31; op2:f30; op3:f31; dest:f31; op1val:0x752d; op2val:0x3774;
op3val:0x752d; valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f31, f30, f31, dyn, 96, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd != rs2 and rs1 == rd != rs3 and rs3 != rs2, rs1==f30, rs2==f31, rs3==f29, rd==f30,fs1 == 0 and fe1 == 0x1e and fm1 == 0x134 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x31f and fs3 == 0 and fe3 == 0x1b and fm3 == 0x0a2 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f31; op3:f29; dest:f30; op1val:0x7934; op2val:0x2f1f;
op3val:0x6ca2; valaddr_reg:x3; val_offset:3*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f30, f30, f31, f29, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_2:
// rd == rs2 == rs3 != rs1, rs1==f29, rs2==f28, rs3==f28, rd==f28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f29; op2:f28; op3:f28; dest:f28; op1val:0x7848; op2val:0x3975;
op3val:0x3975; valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f28, f29, f28, f28, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_3:
// rs3 == rd != rs1 and rs3 == rd != rs2 and rs2 != rs1, rs1==f28, rs2==f29, rs3==f27, rd==f27,fs1 == 0 and fe1 == 0x1a and fm1 == 0x36c and fs2 == 0 and fe2 == 0x12 and fm2 == 0x05f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x00e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f28; op2:f29; op3:f27; dest:f27; op1val:0x6b6c; op2val:0x485f;
op3val:0x780e; valaddr_reg:x3; val_offset:9*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f27, f28, f29, f27, dyn, 96, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_4:
// rs2 == rd != rs1 and rs2 == rd != rs3 and rs3 != rs1, rs1==f27, rs2==f26, rs3==f30, rd==f26,fs1 == 0 and fe1 == 0x1a and fm1 == 0x0cc and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2ef and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f27; op2:f26; op3:f30; dest:f26; op1val:0x68cc; op2val:0x49c7;
op3val:0x76ef; valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f26, f27, f26, f30, dyn, 96, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_5:
// rs1 == rs2 == rs3 == rd, rs1==f25, rs2==f25, rs3==f25, rd==f25,fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f25; op2:f25; op3:f25; dest:f25; op1val:0x6c78; op2val:0x6c78;
op3val:0x6c78; valaddr_reg:x3; val_offset:15*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f25, f25, f25, f25, dyn, 96, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_6:
// rs2 == rs3 != rs1 and rs2 == rs3 != rd and rd != rs1, rs1==f26, rs2==f24, rs3==f24, rd==f29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f26; op2:f24; op3:f24; dest:f29; op1val:0x76ca; op2val:0x3fca;
op3val:0x3fca; valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f29, f26, f24, f24, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_7:
// rs1 == rs2 == rd != rs3, rs1==f23, rs2==f23, rs3==f26, rd==f23,fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f23; op2:f23; op3:f26; dest:f23; op1val:0x6feb; op2val:0x6feb;
op3val:0x7323; valaddr_reg:x3; val_offset:21*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f23, f23, f23, f26, dyn, 96, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_8:
// rs1 == rs2 == rs3 != rd, rs1==f22, rs2==f22, rs3==f22, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f22; op2:f22; op3:f22; dest:f24; op1val:0x7904; op2val:0x7904;
op3val:0x7904; valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f24, f22, f22, f22, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_9:
// rs1 == rs2 != rs3 and rs1 == rs2 != rd and rd != rs3, rs1==f21, rs2==f21, rs3==f23, rd==f22,fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f21; op2:f21; op3:f23; dest:f22; op1val:0x789d; op2val:0x789d;
op3val:0x7658; valaddr_reg:x3; val_offset:27*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f22, f21, f21, f23, dyn, 96, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_10:
// rs1 == rs3 != rs2 and rs1 == rs3 != rd and rd != rs2, rs1==f20, rs2==f27, rs3==f20, rd==f21,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f20; op2:f27; op3:f20; dest:f21; op1val:0x7bce; op2val:0x2a1c;
op3val:0x7bce; valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f21, f20, f27, f20, dyn, 96, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_11:
// rs1 != rs2 and rs1 != rd and rs1 != rs3 and rs2 != rs3 and rs2 != rd and rs3 != rd, rs1==f24, rs2==f19, rs3==f21, rd==f20,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2dd and fs2 == 0 and fe2 == 0x0d and fm2 == 0x165 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0a1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f24; op2:f19; op3:f21; dest:f20; op1val:0x7add; op2val:0x3565;
op3val:0x74a1; valaddr_reg:x3; val_offset:33*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f20, f24, f19, f21, dyn, 96, 0, x3, 33*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f18, rs2==f20, rs3==f17, rd==f19,fs1 == 0 and fe1 == 0x1c and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x288 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x389 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f18; op2:f20; op3:f17; dest:f19; op1val:0x709d; op2val:0x3a88;
op3val:0x6f89; valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f19, f18, f20, f17, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f19, rs2==f17, rs3==f16, rd==f18,fs1 == 0 and fe1 == 0x1d and fm1 == 0x0ee and fs2 == 0 and fe2 == 0x10 and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x286 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f19; op2:f17; op3:f16; dest:f18; op1val:0x74ee; op2val:0x414a;
op3val:0x7a86; valaddr_reg:x3; val_offset:39*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f18, f19, f17, f16, dyn, 96, 0, x3, 39*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f16, rs2==f18, rs3==f19, rd==f17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x1c7 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0a6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f16; op2:f18; op3:f19; dest:f17; op1val:0x71c7; op2val:0x426f;
op3val:0x78a6; valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f17, f16, f18, f19, dyn, 96, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f17, rs2==f15, rs3==f18, rd==f16,fs1 == 0 and fe1 == 0x1e and fm1 == 0x11b and fs2 == 0 and fe2 == 0x0e and fm2 == 0x0a9 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1f4 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f17; op2:f15; op3:f18; dest:f16; op1val:0x791b; op2val:0x38a9;
op3val:0x75f4; valaddr_reg:x3; val_offset:45*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f16, f17, f15, f18, dyn, 96, 0, x3, 45*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f14, rs2==f16, rs3==f13, rd==f15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x061 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x356 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x004 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f14; op2:f16; op3:f13; dest:f15; op1val:0x7861; op2val:0x2f56;
op3val:0x6c04; valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f15, f14, f16, f13, dyn, 96, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f15, rs2==f13, rs3==f12, rd==f14,fs1 == 0 and fe1 == 0x1a and fm1 == 0x3a0 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x2e8 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x296 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f15; op2:f13; op3:f12; dest:f14; op1val:0x6ba0; op2val:0x42e8;
op3val:0x7296; valaddr_reg:x3; val_offset:51*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f14, f15, f13, f12, dyn, 96, 0, x3, 51*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rs2==f14, rs3==f15, rd==f13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x170 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x107 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2d6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f12; op2:f14; op3:f15; dest:f13; op1val:0x7970; op2val:0x3907;
op3val:0x76d6; valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f13, f12, f14, f15, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f13, rs2==f11, rs3==f14, rd==f12,fs1 == 0 and fe1 == 0x1d and fm1 == 0x106 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0ae and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f13; op2:f11; op3:f14; dest:f12; op1val:0x7506; op2val:0x3f74;
op3val:0x78ae; valaddr_reg:x3; val_offset:57*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f12, f13, f11, f14, dyn, 96, 0, x3, 57*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f10, rs2==f12, rs3==f9, rd==f11,fs1 == 0 and fe1 == 0x1d and fm1 == 0x33f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x14a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x0cb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f10; op2:f12; op3:f9; dest:f11; op1val:0x773f; op2val:0x394a;
op3val:0x74cb; valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f11, f10, f12, f9, dyn, 96, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f11, rs2==f9, rs3==f8, rd==f10,fs1 == 0 and fe1 == 0x1e and fm1 == 0x25a and fs2 == 0 and fe2 == 0x0e and fm2 == 0x30a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x196 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f11; op2:f9; op3:f8; dest:f10; op1val:0x7a5a; op2val:0x3b0a;
op3val:0x7996; valaddr_reg:x3; val_offset:63*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f10, f11, f9, f8, dyn, 96, 0, x3, 63*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f8, rs2==f10, rs3==f11, rd==f9,fs1 == 0 and fe1 == 0x1c and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0b4 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x097 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f8; op2:f10; op3:f11; dest:f9; op1val:0x73ce; op2val:0x40b4;
op3val:0x7897; valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f9, f8, f10, f11, dyn, 96, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f9, rs2==f7, rs3==f10, rd==f8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x033 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2aa and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f9; op2:f7; op3:f10; dest:f8; op1val:0x7833; op2val:0x3eaa;
op3val:0x7aff; valaddr_reg:x3; val_offset:69*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f8, f9, f7, f10, dyn, 96, 0, x3, 69*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f6, rs2==f8, rs3==f5, rd==f7,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1d5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x250 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x09a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f6; op2:f8; op3:f5; dest:f7; op1val:0x79d5; op2val:0x3650;
op3val:0x749a; valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f7, f6, f8, f5, dyn, 96, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f7, rs2==f5, rs3==f4, rd==f6,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x0b and fm2 == 0x3b5 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f7; op2:f5; op3:f4; dest:f6; op1val:0x7bd6; op2val:0x2fb5;
op3val:0x6f8d; valaddr_reg:x3; val_offset:75*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f6, f7, f5, f4, dyn, 96, 0, x3, 75*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f4, rs2==f6, rs3==f7, rd==f5,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2af and fs2 == 0 and fe2 == 0x0f and fm2 == 0x33e and fs3 == 0 and fe3 == 0x1e and fm3 == 0x20d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f4; op2:f6; op3:f7; dest:f5; op1val:0x76af; op2val:0x3f3e;
op3val:0x7a0d; valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f5, f4, f6, f7, dyn, 96, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f5, rs2==f3, rs3==f6, rd==f4,fs1 == 0 and fe1 == 0x1c and fm1 == 0x0dc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x26f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3d1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f5; op2:f3; op3:f6; dest:f4; op1val:0x70dc; op2val:0x426f;
op3val:0x77d1; valaddr_reg:x3; val_offset:81*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f4, f5, f3, f6, dyn, 96, 0, x3, 81*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f2, rs2==f4, rs3==f1, rd==f3,fs1 == 0 and fe1 == 0x1a and fm1 == 0x104 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x042 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x157 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f2; op2:f4; op3:f1; dest:f3; op1val:0x6904; op2val:0x4c42;
op3val:0x7957; valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f3, f2, f4, f1, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f3, rs2==f1, rs3==f0, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x21d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1fe and fs3 == 0 and fe3 == 0x1e and fm3 == 0x094 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f3; op2:f1; op3:f0; dest:f2; op1val:0x7a1d; op2val:0x39fe;
op3val:0x7894; valaddr_reg:x3; val_offset:87*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f2, f3, f1, f0, dyn, 96, 0, x3, 87*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f0, rs2==f2, rs3==f3, rd==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x300 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x1bb and fs3 == 0 and fe3 == 0x1d and fm3 == 0x104 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f0; op2:f2; op3:f3; dest:f1; op1val:0x7b00; op2val:0x35bb;
op3val:0x7504; valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f1, f0, f2, f3, dyn, 96, 0, x3, 90*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x18f and fs2 == 0 and fe2 == 0x0e and fm2 == 0x2d6 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x0c0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f1; op2:f30; op3:f29; dest:f31; op1val:0x798f; op2val:0x3ad6;
op3val:0x78c0; valaddr_reg:x3; val_offset:93*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f1, f30, f29, dyn, 96, 0, x3, 93*FLEN/8, x4, x1, x2)
inst_32:
// rs2==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a3 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x24b and fs3 == 0 and fe3 == 0x1d and fm3 == 0x34b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f0; op3:f29; dest:f31; op1val:0x78a3; op2val:0x3a4b;
op3val:0x774b; valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f0, f29, dyn, 96, 0, x3, 96*FLEN/8, x4, x1, x2)
inst_33:
// rs3==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2b7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x07f and fs3 == 0 and fe3 == 0x1e and fm3 == 0x38d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f2; dest:f31; op1val:0x7ab7; op2val:0x3c7f;
op3val:0x7b8d; valaddr_reg:x3; val_offset:99*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f2, dyn, 96, 0, x3, 99*FLEN/8, x4, x1, x2)
inst_34:
// rd==f0,fs1 == 0 and fe1 == 0x1d and fm1 == 0x394 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x19a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x14f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f31; op2:f30; op3:f29; dest:f0; op1val:0x7794; op2val:0x3d9a;
op3val:0x794f; valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f0, f31, f30, f29, dyn, 96, 0, x3, 102*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x3c3 and fs2 == 0 and fe2 == 0x12 and fm2 == 0x1c7 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x19b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6bc3; op2val:0x49c7;
op3val:0x799b; valaddr_reg:x3; val_offset:105*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 105*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x12c and fs2 == 0 and fe2 == 0x0f and fm2 == 0x223 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x3f0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x792c; op2val:0x3e23;
op3val:0x7bf0; valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 108*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x292 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x18a and fs3 == 0 and fe3 == 0x1d and fm3 == 0x08d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a92; op2val:0x358a;
op3val:0x748d; valaddr_reg:x3; val_offset:111*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 111*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x22b and fs2 == 0 and fe2 == 0x0f and fm2 == 0x2ee and fs3 == 0 and fe3 == 0x1e and fm3 == 0x158 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x762b; op2val:0x3eee;
op3val:0x7958; valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 114*FLEN/8, x4, x1, x2)
inst_39:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x1c6 and fs2 == 0 and fe2 == 0x13 and fm2 == 0x11c and fs3 == 0 and fe3 == 0x1d and fm3 == 0x362 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x65c6; op2val:0x4d1c;
op3val:0x7762; valaddr_reg:x3; val_offset:117*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 117*FLEN/8, x4, x1, x2)
inst_40:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x160 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x193 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x37d and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7160; op2val:0x3993;
op3val:0x6f7d; valaddr_reg:x3; val_offset:120*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 120*FLEN/8, x4, x1, x2)
inst_41:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x38b and fs2 == 0 and fe2 == 0x12 and fm2 == 0x283 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x224 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6b8b; op2val:0x4a83;
op3val:0x7a24; valaddr_reg:x3; val_offset:123*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 123*FLEN/8, x4, x1, x2)
inst_42:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x023 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3b0 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x3eb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7023; op2val:0x3fb0;
op3val:0x73eb; valaddr_reg:x3; val_offset:126*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 126*FLEN/8, x4, x1, x2)
inst_43:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x240 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x076 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2f7 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7640; op2val:0x4076;
op3val:0x7af7; valaddr_reg:x3; val_offset:129*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 129*FLEN/8, x4, x1, x2)
inst_44:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x127 and fs2 == 0 and fe2 == 0x11 and fm2 == 0x195 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x32f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6d27; op2val:0x4595;
op3val:0x772f; valaddr_reg:x3; val_offset:132*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 132*FLEN/8, x4, x1, x2)
inst_45:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x064 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x270 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x310 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7864; op2val:0x3e70;
op3val:0x7b10; valaddr_reg:x3; val_offset:135*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 135*FLEN/8, x4, x1, x2)
inst_46:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28d and fs2 == 0 and fe2 == 0x0f and fm2 == 0x039 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x2e8 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7a8d; op2val:0x3c39;
op3val:0x7ae8; valaddr_reg:x3; val_offset:138*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 138*FLEN/8, x4, x1, x2)
inst_47:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x073 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x1fa and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2a4 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7473; op2val:0x3dfa;
op3val:0x76a4; valaddr_reg:x3; val_offset:141*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 141*FLEN/8, x4, x1, x2)
inst_48:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1bc and fs2 == 0 and fe2 == 0x10 and fm2 == 0x0ef and fs3 == 0 and fe3 == 0x1e and fm3 == 0x311 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75bc; op2val:0x40ef;
op3val:0x7b11; valaddr_reg:x3; val_offset:144*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 144*FLEN/8, x4, x1, x2)
inst_49:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a8 and fs2 == 0 and fe2 == 0x0c and fm2 == 0x10b and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7ba8; op2val:0x310b;
op3val:0x70d3; valaddr_reg:x3; val_offset:147*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 147*FLEN/8, x4, x1, x2)
inst_50:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x1a2 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x143 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x36b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x71a2; op2val:0x3d43;
op3val:0x736b; valaddr_reg:x3; val_offset:150*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 150*FLEN/8, x4, x1, x2)
inst_51:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x376 and fs2 == 0 and fe2 == 0x10 and fm2 == 0x028 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x3c1 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7376; op2val:0x4028;
op3val:0x77c1; valaddr_reg:x3; val_offset:153*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 153*FLEN/8, x4, x1, x2)
inst_52:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0b5 and fs2 == 0 and fe2 == 0x0d and fm2 == 0x322 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x033 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x78b5; op2val:0x3722;
op3val:0x7433; valaddr_reg:x3; val_offset:156*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 156*FLEN/8, x4, x1, x2)
inst_53:
// fs1 == 0 and fe1 == 0x17 and fm1 == 0x034 and fs2 == 0 and fe2 == 0x15 and fm2 == 0x25f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x2b3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x5c34; op2val:0x565f;
op3val:0x76b3; valaddr_reg:x3; val_offset:159*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 159*FLEN/8, x4, x1, x2)
inst_54:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x1e7 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x222 and fs3 == 0 and fe3 == 0x1e and fm3 == 0x087 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x75e7; op2val:0x3e22;
op3val:0x7887; valaddr_reg:x3; val_offset:162*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 162*FLEN/8, x4, x1, x2)
inst_55:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x39e and fs2 == 0 and fe2 == 0x0e and fm2 == 0x1cb and fs3 == 0 and fe3 == 0x1e and fm3 == 0x185 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7b9e; op2val:0x39cb;
op3val:0x7985; valaddr_reg:x3; val_offset:165*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 165*FLEN/8, x4, x1, x2)
inst_56:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x12d and fs2 == 0 and fe2 == 0x0d and fm2 == 0x374 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x0d3 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x752d; op2val:0x3774;
op3val:0x70d3; valaddr_reg:x3; val_offset:168*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 168*FLEN/8, x4, x1, x2)
inst_57:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x048 and fs2 == 0 and fe2 == 0x0e and fm2 == 0x175 and fs3 == 0 and fe3 == 0x1d and fm3 == 0x1d9 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7848; op2val:0x3975;
op3val:0x75d9; valaddr_reg:x3; val_offset:171*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 171*FLEN/8, x4, x1, x2)
inst_58:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x078 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x131 and fs3 == 0 and fe3 == 0x1b and fm3 == 0x1cd and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6c78; op2val:0x3d31;
op3val:0x6dcd; valaddr_reg:x3; val_offset:174*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 174*FLEN/8, x4, x1, x2)
inst_59:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2ca and fs2 == 0 and fe2 == 0x0f and fm2 == 0x3ca and fs3 == 0 and fe3 == 0x1e and fm3 == 0x29c and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x76ca; op2val:0x3fca;
op3val:0x7a9c; valaddr_reg:x3; val_offset:177*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 177*FLEN/8, x4, x1, x2)
inst_60:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x3eb and fs2 == 0 and fe2 == 0x0f and fm2 == 0x336 and fs3 == 0 and fe3 == 0x1c and fm3 == 0x323 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x6feb; op2val:0x3f36;
op3val:0x7323; valaddr_reg:x3; val_offset:180*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 180*FLEN/8, x4, x1, x2)
inst_61:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x104 and fs2 == 0 and fe2 == 0x0f and fm2 == 0x20a and fs3 == 0 and fe3 == 0x1e and fm3 == 0x393 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7904; op2val:0x3e0a;
op3val:0x7b93; valaddr_reg:x3; val_offset:183*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 183*FLEN/8, x4, x1, x2)
inst_62:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x09d and fs2 == 0 and fe2 == 0x0e and fm2 == 0x17f and fs3 == 0 and fe3 == 0x1d and fm3 == 0x258 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x789d; op2val:0x397f;
op3val:0x7658; valaddr_reg:x3; val_offset:186*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 186*FLEN/8, x4, x1, x2)
inst_63:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ce and fs2 == 0 and fe2 == 0x0a and fm2 == 0x21c and fs3 == 0 and fe3 == 0x1a and fm3 == 0x1f6 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff and rs3_nan_prefix == 0xffff
/* opcode: fmsub.h ; op1:f30; op2:f29; op3:f28; dest:f31; op1val:0x7bce; op2val:0x2a1c;
op3val:0x69f6; valaddr_reg:x3; val_offset:189*FLEN/8; rmval:dyn;
testreg:x2; fcsr_val:96 */
TEST_FPR4_OP(fmsub.h, f31, f30, f29, f28, dyn, 96, 0, x3, 189*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(29997,16,FLEN)
NAN_BOXED(14196,16,FLEN)
NAN_BOXED(29997,16,FLEN)
NAN_BOXED(31028,16,FLEN)
NAN_BOXED(12063,16,FLEN)
NAN_BOXED(27810,16,FLEN)
NAN_BOXED(30792,16,FLEN)
NAN_BOXED(14709,16,FLEN)
NAN_BOXED(14709,16,FLEN)
NAN_BOXED(27500,16,FLEN)
NAN_BOXED(18527,16,FLEN)
NAN_BOXED(30734,16,FLEN)
NAN_BOXED(26828,16,FLEN)
NAN_BOXED(18887,16,FLEN)
NAN_BOXED(30447,16,FLEN)
NAN_BOXED(27768,16,FLEN)
NAN_BOXED(27768,16,FLEN)
NAN_BOXED(27768,16,FLEN)
NAN_BOXED(30410,16,FLEN)
NAN_BOXED(16330,16,FLEN)
NAN_BOXED(16330,16,FLEN)
NAN_BOXED(28651,16,FLEN)
NAN_BOXED(28651,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(30980,16,FLEN)
NAN_BOXED(30980,16,FLEN)
NAN_BOXED(30980,16,FLEN)
NAN_BOXED(30877,16,FLEN)
NAN_BOXED(30877,16,FLEN)
NAN_BOXED(30296,16,FLEN)
NAN_BOXED(31694,16,FLEN)
NAN_BOXED(10780,16,FLEN)
NAN_BOXED(31694,16,FLEN)
NAN_BOXED(31453,16,FLEN)
NAN_BOXED(13669,16,FLEN)
NAN_BOXED(29857,16,FLEN)
NAN_BOXED(28829,16,FLEN)
NAN_BOXED(14984,16,FLEN)
NAN_BOXED(28553,16,FLEN)
NAN_BOXED(29934,16,FLEN)
NAN_BOXED(16714,16,FLEN)
NAN_BOXED(31366,16,FLEN)
NAN_BOXED(29127,16,FLEN)
NAN_BOXED(17007,16,FLEN)
NAN_BOXED(30886,16,FLEN)
NAN_BOXED(31003,16,FLEN)
NAN_BOXED(14505,16,FLEN)
NAN_BOXED(30196,16,FLEN)
NAN_BOXED(30817,16,FLEN)
NAN_BOXED(12118,16,FLEN)
NAN_BOXED(27652,16,FLEN)
NAN_BOXED(27552,16,FLEN)
NAN_BOXED(17128,16,FLEN)
NAN_BOXED(29334,16,FLEN)
NAN_BOXED(31088,16,FLEN)
NAN_BOXED(14599,16,FLEN)
NAN_BOXED(30422,16,FLEN)
NAN_BOXED(29958,16,FLEN)
NAN_BOXED(16244,16,FLEN)
NAN_BOXED(30894,16,FLEN)
NAN_BOXED(30527,16,FLEN)
NAN_BOXED(14666,16,FLEN)
NAN_BOXED(29899,16,FLEN)
NAN_BOXED(31322,16,FLEN)
NAN_BOXED(15114,16,FLEN)
NAN_BOXED(31126,16,FLEN)
NAN_BOXED(29646,16,FLEN)
NAN_BOXED(16564,16,FLEN)
NAN_BOXED(30871,16,FLEN)
NAN_BOXED(30771,16,FLEN)
NAN_BOXED(16042,16,FLEN)
NAN_BOXED(31487,16,FLEN)
NAN_BOXED(31189,16,FLEN)
NAN_BOXED(13904,16,FLEN)
NAN_BOXED(29850,16,FLEN)
NAN_BOXED(31702,16,FLEN)
NAN_BOXED(12213,16,FLEN)
NAN_BOXED(28557,16,FLEN)
NAN_BOXED(30383,16,FLEN)
NAN_BOXED(16190,16,FLEN)
NAN_BOXED(31245,16,FLEN)
NAN_BOXED(28892,16,FLEN)
NAN_BOXED(17007,16,FLEN)
NAN_BOXED(30673,16,FLEN)
NAN_BOXED(26884,16,FLEN)
NAN_BOXED(19522,16,FLEN)
NAN_BOXED(31063,16,FLEN)
NAN_BOXED(31261,16,FLEN)
NAN_BOXED(14846,16,FLEN)
NAN_BOXED(30868,16,FLEN)
NAN_BOXED(31488,16,FLEN)
NAN_BOXED(13755,16,FLEN)
NAN_BOXED(29956,16,FLEN)
NAN_BOXED(31119,16,FLEN)
NAN_BOXED(15062,16,FLEN)
NAN_BOXED(30912,16,FLEN)
NAN_BOXED(30883,16,FLEN)
NAN_BOXED(14923,16,FLEN)
NAN_BOXED(30539,16,FLEN)
NAN_BOXED(31415,16,FLEN)
NAN_BOXED(15487,16,FLEN)
NAN_BOXED(31629,16,FLEN)
NAN_BOXED(30612,16,FLEN)
NAN_BOXED(15770,16,FLEN)
NAN_BOXED(31055,16,FLEN)
NAN_BOXED(27587,16,FLEN)
NAN_BOXED(18887,16,FLEN)
NAN_BOXED(31131,16,FLEN)
NAN_BOXED(31020,16,FLEN)
NAN_BOXED(15907,16,FLEN)
NAN_BOXED(31728,16,FLEN)
NAN_BOXED(31378,16,FLEN)
NAN_BOXED(13706,16,FLEN)
NAN_BOXED(29837,16,FLEN)
NAN_BOXED(30251,16,FLEN)
NAN_BOXED(16110,16,FLEN)
NAN_BOXED(31064,16,FLEN)
NAN_BOXED(26054,16,FLEN)
NAN_BOXED(19740,16,FLEN)
NAN_BOXED(30562,16,FLEN)
NAN_BOXED(29024,16,FLEN)
NAN_BOXED(14739,16,FLEN)
NAN_BOXED(28541,16,FLEN)
NAN_BOXED(27531,16,FLEN)
NAN_BOXED(19075,16,FLEN)
NAN_BOXED(31268,16,FLEN)
NAN_BOXED(28707,16,FLEN)
NAN_BOXED(16304,16,FLEN)
NAN_BOXED(29675,16,FLEN)
NAN_BOXED(30272,16,FLEN)
NAN_BOXED(16502,16,FLEN)
NAN_BOXED(31479,16,FLEN)
NAN_BOXED(27943,16,FLEN)
NAN_BOXED(17813,16,FLEN)
NAN_BOXED(30511,16,FLEN)
NAN_BOXED(30820,16,FLEN)
NAN_BOXED(15984,16,FLEN)
NAN_BOXED(31504,16,FLEN)
NAN_BOXED(31373,16,FLEN)
NAN_BOXED(15417,16,FLEN)
NAN_BOXED(31464,16,FLEN)
NAN_BOXED(29811,16,FLEN)
NAN_BOXED(15866,16,FLEN)
NAN_BOXED(30372,16,FLEN)
NAN_BOXED(30140,16,FLEN)
NAN_BOXED(16623,16,FLEN)
NAN_BOXED(31505,16,FLEN)
NAN_BOXED(31656,16,FLEN)
NAN_BOXED(12555,16,FLEN)
NAN_BOXED(28883,16,FLEN)
NAN_BOXED(29090,16,FLEN)
NAN_BOXED(15683,16,FLEN)
NAN_BOXED(29547,16,FLEN)
NAN_BOXED(29558,16,FLEN)
NAN_BOXED(16424,16,FLEN)
NAN_BOXED(30657,16,FLEN)
NAN_BOXED(30901,16,FLEN)
NAN_BOXED(14114,16,FLEN)
NAN_BOXED(29747,16,FLEN)
NAN_BOXED(23604,16,FLEN)
NAN_BOXED(22111,16,FLEN)
NAN_BOXED(30387,16,FLEN)
NAN_BOXED(30183,16,FLEN)
NAN_BOXED(15906,16,FLEN)
NAN_BOXED(30855,16,FLEN)
NAN_BOXED(31646,16,FLEN)
NAN_BOXED(14795,16,FLEN)
NAN_BOXED(31109,16,FLEN)
NAN_BOXED(29997,16,FLEN)
NAN_BOXED(14196,16,FLEN)
NAN_BOXED(28883,16,FLEN)
NAN_BOXED(30792,16,FLEN)
NAN_BOXED(14709,16,FLEN)
NAN_BOXED(30169,16,FLEN)
NAN_BOXED(27768,16,FLEN)
NAN_BOXED(15665,16,FLEN)
NAN_BOXED(28109,16,FLEN)
NAN_BOXED(30410,16,FLEN)
NAN_BOXED(16330,16,FLEN)
NAN_BOXED(31388,16,FLEN)
NAN_BOXED(28651,16,FLEN)
NAN_BOXED(16182,16,FLEN)
NAN_BOXED(29475,16,FLEN)
NAN_BOXED(30980,16,FLEN)
NAN_BOXED(15882,16,FLEN)
NAN_BOXED(31635,16,FLEN)
NAN_BOXED(30877,16,FLEN)
NAN_BOXED(14719,16,FLEN)
NAN_BOXED(30296,16,FLEN)
NAN_BOXED(31694,16,FLEN)
NAN_BOXED(10780,16,FLEN)
NAN_BOXED(27126,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 128*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmsub_b8-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmul_b1-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmul_b3-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmul_b4-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmul_b5-01.S
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tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmul_b6-01.S
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@ -1,469 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Sat May 6 11:14:00 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmul.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmul.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmul_b6 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmul_b6)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f30, rs2==f29, rd==f31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xfbff;
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs2 == rd != rs1, rs1==f31, rs2==f30, rd==f30,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f31; op2:f30; dest:f30; op1val:0x0; op2val:0xfbff;
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 32;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f30, f31, f30, dyn, 32, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:
// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f28; op2:f28; dest:f28; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 64;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f28, f28, f28, dyn, 64, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:
// rs1 == rs2 != rd, rs1==f27, rs2==f27, rd==f29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f27; op2:f27; dest:f29; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f29, f27, f27, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:
// rs1 == rd != rs2, rs1==f26, rs2==f31, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f26; op2:f31; dest:f26; op1val:0x0; op2val:0xfbff;
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 128;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f26, f26, f31, dyn, 128, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f29, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f29; op2:f26; dest:f27; op1val:0x0; op2val:0x7bff;
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f27, f29, f26, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f24, rs2==f23, rd==f25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x20 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f24; op2:f23; dest:f25; op1val:0x0; op2val:0x7bff;
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 32;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f25, f24, f23, dyn, 32, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f23; op2:f25; dest:f24; op1val:0x0; op2val:0x7bff;
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 64;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f24, f23, f25, dyn, 64, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f25, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f25; op2:f24; dest:f23; op1val:0x0; op2val:0x7bff;
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f23, f25, f24, dyn, 96, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f21, rs2==f20, rd==f22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 0 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x80 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f21; op2:f20; dest:f22; op1val:0x0; op2val:0x7bff;
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 128;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f22, f21, f20, dyn, 128, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f20, rs2==f22, rd==f21,
/* opcode: fmul.h ; op1:f20; op2:f22; dest:f21; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f21, f20, f22, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f22, rs2==f21, rd==f20,
/* opcode: fmul.h ; op1:f22; op2:f21; dest:f20; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f20, f22, f21, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f18, rs2==f17, rd==f19,
/* opcode: fmul.h ; op1:f18; op2:f17; dest:f19; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f19, f18, f17, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f17, rs2==f19, rd==f18,
/* opcode: fmul.h ; op1:f17; op2:f19; dest:f18; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f18, f17, f19, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f19, rs2==f18, rd==f17,
/* opcode: fmul.h ; op1:f19; op2:f18; dest:f17; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f17, f19, f18, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f15, rs2==f14, rd==f16,
/* opcode: fmul.h ; op1:f15; op2:f14; dest:f16; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f16, f15, f14, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f14, rs2==f16, rd==f15,
/* opcode: fmul.h ; op1:f14; op2:f16; dest:f15; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f15, f14, f16, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f16, rs2==f15, rd==f14,
/* opcode: fmul.h ; op1:f16; op2:f15; dest:f14; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f14, f16, f15, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rs2==f11, rd==f13,
/* opcode: fmul.h ; op1:f12; op2:f11; dest:f13; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f13, f12, f11, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f11, rs2==f13, rd==f12,
/* opcode: fmul.h ; op1:f11; op2:f13; dest:f12; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f12, f11, f13, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f13, rs2==f12, rd==f11,
/* opcode: fmul.h ; op1:f13; op2:f12; dest:f11; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f11, f13, f12, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f9, rs2==f8, rd==f10,
/* opcode: fmul.h ; op1:f9; op2:f8; dest:f10; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f10, f9, f8, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f8, rs2==f10, rd==f9,
/* opcode: fmul.h ; op1:f8; op2:f10; dest:f9; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f9, f8, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f10, rs2==f9, rd==f8,
/* opcode: fmul.h ; op1:f10; op2:f9; dest:f8; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f8, f10, f9, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f6, rs2==f5, rd==f7,
/* opcode: fmul.h ; op1:f6; op2:f5; dest:f7; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f7, f6, f5, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f5, rs2==f7, rd==f6,
/* opcode: fmul.h ; op1:f5; op2:f7; dest:f6; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f6, f5, f7, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f7, rs2==f6, rd==f5,
/* opcode: fmul.h ; op1:f7; op2:f6; dest:f5; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f5, f7, f6, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f3, rs2==f2, rd==f4,
/* opcode: fmul.h ; op1:f3; op2:f2; dest:f4; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f4, f3, f2, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f2, rs2==f4, rd==f3,
/* opcode: fmul.h ; op1:f2; op2:f4; dest:f3; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f3, f2, f4, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f4, rs2==f3, rd==f2,
/* opcode: fmul.h ; op1:f4; op2:f3; dest:f2; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f2, f4, f3, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f1,
/* opcode: fmul.h ; op1:f1; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f1, f30, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f0,
/* opcode: fmul.h ; op1:f0; op2:f30; dest:f31; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f0, f30, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:
// rs2==f1,
/* opcode: fmul.h ; op1:f30; op2:f1; dest:f31; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f1, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
inst_33:
// rs2==f0,
/* opcode: fmul.h ; op1:f30; op2:f0; dest:f31; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f0, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_34:
// rd==f1,
/* opcode: fmul.h ; op1:f31; op2:f30; dest:f1; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f1, f31, f30, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
inst_35:
// rd==f0,
/* opcode: fmul.h ; op1:f31; op2:f30; dest:f0; op1val:0x0; op2val:0x0;
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f0, f31, f30, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x40 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xfbff;
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 64;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 64, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fs2 == 1 and fe2 == 0x1e and fm2 == 0x3ff and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x0; op2val:0xfbff;
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 74*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31743,16,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(64511,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 76*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

669
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmul_b7-01.S
View file

@ -1,669 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Sat May 6 11:14:00 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmul.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmul.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmul_b7 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmul_b7)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f30, rs2==f29, rd==f31,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7ba5; op2val:0x0;
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs2 == rd != rs1, rs1==f31, rs2==f30, rd==f30,fs1 == 0 and fe1 == 0x1a and fm1 == 0x33c and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f31; op2:f30; dest:f30; op1val:0x6b3c; op2val:0x0;
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f30, f31, f30, dyn, 96, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:
// rs1 == rs2 == rd, rs1==f28, rs2==f28, rd==f28,fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f28; op2:f28; dest:f28; op1val:0x7aae; op2val:0x7aae;
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f28, f28, f28, dyn, 96, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:
// rs1 == rs2 != rd, rs1==f27, rs2==f27, rd==f29,fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f27; op2:f27; dest:f29; op1val:0x795a; op2val:0x795a;
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f29, f27, f27, dyn, 96, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:
// rs1 == rd != rs2, rs1==f26, rs2==f31, rd==f26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0d8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f26; op2:f31; dest:f26; op1val:0x78d8; op2val:0x0;
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f26, f26, f31, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f29, rs2==f26, rd==f27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x0a5 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f29; op2:f26; dest:f27; op1val:0x78a5; op2val:0x0;
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f27, f29, f26, dyn, 96, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f24, rs2==f23, rd==f25,fs1 == 0 and fe1 == 0x1d and fm1 == 0x2e3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f24; op2:f23; dest:f25; op1val:0x76e3; op2val:0x0;
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f25, f24, f23, dyn, 96, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f23, rs2==f25, rd==f24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f23; op2:f25; dest:f24; op1val:0x79c8; op2val:0x0;
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f24, f23, f25, dyn, 96, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f25, rs2==f24, rd==f23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x397 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f25; op2:f24; dest:f23; op1val:0x7b97; op2val:0x0;
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f23, f25, f24, dyn, 96, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f21, rs2==f20, rd==f22,fs1 == 0 and fe1 == 0x1d and fm1 == 0x31d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f21; op2:f20; dest:f22; op1val:0x771d; op2val:0x0;
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f22, f21, f20, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f20, rs2==f22, rd==f21,fs1 == 0 and fe1 == 0x1a and fm1 == 0x099 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f20; op2:f22; dest:f21; op1val:0x6899; op2val:0x0;
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f21, f20, f22, dyn, 96, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f22, rs2==f21, rd==f20,fs1 == 0 and fe1 == 0x1d and fm1 == 0x36f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f22; op2:f21; dest:f20; op1val:0x776f; op2val:0x0;
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f20, f22, f21, dyn, 96, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f18, rs2==f17, rd==f19,fs1 == 0 and fe1 == 0x1d and fm1 == 0x213 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f18; op2:f17; dest:f19; op1val:0x7613; op2val:0x0;
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f19, f18, f17, dyn, 96, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f17, rs2==f19, rd==f18,fs1 == 0 and fe1 == 0x1e and fm1 == 0x034 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f17; op2:f19; dest:f18; op1val:0x7834; op2val:0x0;
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f18, f17, f19, dyn, 96, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f19, rs2==f18, rd==f17,fs1 == 0 and fe1 == 0x1c and fm1 == 0x38d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f19; op2:f18; dest:f17; op1val:0x738d; op2val:0x0;
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f17, f19, f18, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f15, rs2==f14, rd==f16,fs1 == 0 and fe1 == 0x1d and fm1 == 0x133 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f15; op2:f14; dest:f16; op1val:0x7533; op2val:0x0;
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f16, f15, f14, dyn, 96, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f14, rs2==f16, rd==f15,fs1 == 0 and fe1 == 0x1e and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f14; op2:f16; dest:f15; op1val:0x7814; op2val:0x0;
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f15, f14, f16, dyn, 96, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f16, rs2==f15, rd==f14,fs1 == 0 and fe1 == 0x1e and fm1 == 0x164 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f16; op2:f15; dest:f14; op1val:0x7964; op2val:0x0;
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f14, f16, f15, dyn, 96, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rs2==f11, rd==f13,fs1 == 0 and fe1 == 0x1e and fm1 == 0x325 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f12; op2:f11; dest:f13; op1val:0x7b25; op2val:0x0;
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f13, f12, f11, dyn, 96, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f11, rs2==f13, rd==f12,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1df and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f11; op2:f13; dest:f12; op1val:0x79df; op2val:0x0;
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f12, f11, f13, dyn, 96, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f13, rs2==f12, rd==f11,fs1 == 0 and fe1 == 0x1e and fm1 == 0x219 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f13; op2:f12; dest:f11; op1val:0x7a19; op2val:0x0;
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f11, f13, f12, dyn, 96, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f9, rs2==f8, rd==f10,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a8 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f9; op2:f8; dest:f10; op1val:0x75a8; op2val:0x0;
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f10, f9, f8, dyn, 96, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f8, rs2==f10, rd==f9,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3b1 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f8; op2:f10; dest:f9; op1val:0x7bb1; op2val:0x0;
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f9, f8, f10, dyn, 96, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f10, rs2==f9, rd==f8,fs1 == 0 and fe1 == 0x1e and fm1 == 0x207 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f10; op2:f9; dest:f8; op1val:0x7a07; op2val:0x0;
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f8, f10, f9, dyn, 96, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f6, rs2==f5, rd==f7,fs1 == 0 and fe1 == 0x1d and fm1 == 0x361 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f6; op2:f5; dest:f7; op1val:0x7761; op2val:0x0;
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f7, f6, f5, dyn, 96, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f5, rs2==f7, rd==f6,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3d6 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f5; op2:f7; dest:f6; op1val:0x77d6; op2val:0x0;
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f6, f5, f7, dyn, 96, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f7, rs2==f6, rd==f5,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f7; op2:f6; dest:f5; op1val:0x7801; op2val:0x0;
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f5, f7, f6, dyn, 96, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f3, rs2==f2, rd==f4,fs1 == 0 and fe1 == 0x1d and fm1 == 0x1a9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f3; op2:f2; dest:f4; op1val:0x75a9; op2val:0x0;
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f4, f3, f2, dyn, 96, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f2, rs2==f4, rd==f3,fs1 == 0 and fe1 == 0x1e and fm1 == 0x331 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f2; op2:f4; dest:f3; op1val:0x7b31; op2val:0x0;
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f3, f2, f4, dyn, 96, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f4, rs2==f3, rd==f2,fs1 == 0 and fe1 == 0x1e and fm1 == 0x08a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f4; op2:f3; dest:f2; op1val:0x788a; op2val:0x0;
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f2, f4, f3, dyn, 96, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x1c9 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f1; op2:f30; dest:f31; op1val:0x79c9; op2val:0x0;
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f1, f30, dyn, 96, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f0,fs1 == 0 and fe1 == 0x1c and fm1 == 0x318 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f0; op2:f30; dest:f31; op1val:0x7318; op2val:0x0;
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f0, f30, dyn, 96, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:
// rs2==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x198 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f1; dest:f31; op1val:0x7998; op2val:0x0;
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f1, dyn, 96, 0, x3, 64*FLEN/8, x4, x1, x2)
inst_33:
// rs2==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x342 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f0; dest:f31; op1val:0x7b42; op2val:0x0;
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f0, dyn, 96, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_34:
// rd==f1,fs1 == 0 and fe1 == 0x1e and fm1 == 0x349 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f31; op2:f30; dest:f1; op1val:0x7b49; op2val:0x0;
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f1, f31, f30, dyn, 96, 0, x3, 68*FLEN/8, x4, x1, x2)
inst_35:
// rd==f0,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3a7 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f31; op2:f30; dest:f0; op1val:0x7ba7; op2val:0x0;
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f0, f31, f30, dyn, 96, 0, x3, 70*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x008 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7808; op2val:0x0;
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x135 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7935; op2val:0x0;
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 74*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x0fc and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x74fc; op2val:0x0;
valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 76*FLEN/8, x4, x1, x2)
inst_39:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x017 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7817; op2val:0x0;
valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_40:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x0fb and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x78fb; op2val:0x0;
valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 80*FLEN/8, x4, x1, x2)
inst_41:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x28f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a8f; op2val:0x0;
valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 82*FLEN/8, x4, x1, x2)
inst_42:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x341 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x068 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7b41; op2val:0x1468;
valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 84*FLEN/8, x4, x1, x2)
inst_43:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x1f4 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x15f and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x79f4; op2val:0x155f;
valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 86*FLEN/8, x4, x1, x2)
inst_44:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x138 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x221 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7938; op2val:0x1621;
valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 88*FLEN/8, x4, x1, x2)
inst_45:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x33f and fs2 == 0 and fe2 == 0x07 and fm2 == 0x06a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x733f; op2val:0x1c6a;
valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 90*FLEN/8, x4, x1, x2)
inst_46:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x2cc and fs2 == 0 and fe2 == 0x08 and fm2 == 0x0b4 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x6ecc; op2val:0x20b4;
valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 92*FLEN/8, x4, x1, x2)
inst_47:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2d4 and fs2 == 0 and fe2 == 0x05 and fm2 == 0x0af and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7ad4; op2val:0x14af;
valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 94*FLEN/8, x4, x1, x2)
inst_48:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x2bb and fs2 == 0 and fe2 == 0x07 and fm2 == 0x0c0 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x72bb; op2val:0x1cc0;
valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 96*FLEN/8, x4, x1, x2)
inst_49:
// fs1 == 0 and fe1 == 0x1d and fm1 == 0x2c3 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x012 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x76c3; op2val:0x12;
valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 98*FLEN/8, x4, x1, x2)
inst_50:
// fs1 == 0 and fe1 == 0x1a and fm1 == 0x014 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x0fb and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x6814; op2val:0xfb;
valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 100*FLEN/8, x4, x1, x2)
inst_51:
// fs1 == 0 and fe1 == 0x1c and fm1 == 0x17f and fs2 == 0 and fe2 == 0x00 and fm2 == 0x02e and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x717f; op2val:0x2e;
valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 102*FLEN/8, x4, x1, x2)
inst_52:
// fs1 == 0 and fe1 == 0x1b and fm1 == 0x14d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x060 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x6d4d; op2val:0x60;
valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 104*FLEN/8, x4, x1, x2)
inst_53:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x27d and fs2 == 0 and fe2 == 0x00 and fm2 == 0x13b and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x667d; op2val:0x13b;
valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 106*FLEN/8, x4, x1, x2)
inst_54:
// fs1 == 0 and fe1 == 0x19 and fm1 == 0x16a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x17a and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x656a; op2val:0x17a;
valaddr_reg:x3; val_offset:108*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 108*FLEN/8, x4, x1, x2)
inst_55:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x280 and fs2 == 0 and fe2 == 0x00 and fm2 == 0x009 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7a80; op2val:0x9;
valaddr_reg:x3; val_offset:110*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 110*FLEN/8, x4, x1, x2)
inst_56:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x2ae and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x7aae; op2val:0x0;
valaddr_reg:x3; val_offset:112*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 112*FLEN/8, x4, x1, x2)
inst_57:
// fs1 == 0 and fe1 == 0x1e and fm1 == 0x15a and fs2 == 0 and fe2 == 0x00 and fm2 == 0x000 and fcsr == 0x60 and rm_val == 7 and rs1_nan_prefix == 0xffff and rs2_nan_prefix == 0xffff
/* opcode: fmul.h ; op1:f30; op2:f29; dest:f31; op1val:0x795a; op2val:0x0;
valaddr_reg:x3; val_offset:114*FLEN/8; rmval:dyn; fcsr: 96;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fmul.h, f31, f30, f29, dyn, 96, 0, x3, 114*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(31653,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(27452,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(31066,16,FLEN)
NAN_BOXED(31066,16,FLEN)
NAN_BOXED(30936,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30885,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30435,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31176,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31639,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30493,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(26777,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30575,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30227,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30772,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29581,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30003,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30740,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31076,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31525,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31199,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31257,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30120,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31665,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31239,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30561,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30678,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30721,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30121,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31537,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30858,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31177,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29464,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31128,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31554,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31561,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31655,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30728,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31029,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(29948,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30743,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(30971,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31375,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31553,16,FLEN)
NAN_BOXED(5224,16,FLEN)
NAN_BOXED(31220,16,FLEN)
NAN_BOXED(5471,16,FLEN)
NAN_BOXED(31032,16,FLEN)
NAN_BOXED(5665,16,FLEN)
NAN_BOXED(29503,16,FLEN)
NAN_BOXED(7274,16,FLEN)
NAN_BOXED(28364,16,FLEN)
NAN_BOXED(8372,16,FLEN)
NAN_BOXED(31444,16,FLEN)
NAN_BOXED(5295,16,FLEN)
NAN_BOXED(29371,16,FLEN)
NAN_BOXED(7360,16,FLEN)
NAN_BOXED(30403,16,FLEN)
NAN_BOXED(18,16,FLEN)
NAN_BOXED(26644,16,FLEN)
NAN_BOXED(251,16,FLEN)
NAN_BOXED(29055,16,FLEN)
NAN_BOXED(46,16,FLEN)
NAN_BOXED(27981,16,FLEN)
NAN_BOXED(96,16,FLEN)
NAN_BOXED(26237,16,FLEN)
NAN_BOXED(315,16,FLEN)
NAN_BOXED(25962,16,FLEN)
NAN_BOXED(378,16,FLEN)
NAN_BOXED(31360,16,FLEN)
NAN_BOXED(9,16,FLEN)
NAN_BOXED(31406,16,FLEN)
NAN_BOXED(0,16,FLEN)
NAN_BOXED(31066,16,FLEN)
NAN_BOXED(0,16,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 116*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

16824
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmul_b8-01.S
View file

File diff suppressed because it is too large Load diff

1454
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmul_b9-01.S
View file

File diff suppressed because it is too large Load diff

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmv.h.x_b25-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:38:56 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.h.x.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmv.h.x instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmv.h.x_b25 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmv.h.x_b25)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0
/* opcode: fmv.h.x ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:0*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f31, x31, 0, 0, x3, 0*4, x4, x1, x2,lw)
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0
/* opcode: fmv.h.x ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
val_offset:1*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f30, x30, 0, 0, x3, 1*4, x4, x1, x2,lw)
inst_2:// rs1==x29, rd==f29,rs1_val == -1 and fcsr == 0
/* opcode: fmv.h.x ; op1:x29; dest:f29; op1val:-0x1; valaddr_reg:x3;
val_offset:2*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f29, x29, 0, 0, x3, 2*4, x4, x1, x2,lw)
inst_3:// rs1==x28, rd==f28,rs1_val == 2147483647 and fcsr == 0
/* opcode: fmv.h.x ; op1:x28; dest:f28; op1val:0x7fffffff; valaddr_reg:x3;
val_offset:3*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f28, x28, 0, 0, x3, 3*4, x4, x1, x2,lw)
inst_4:// rs1==x27, rd==f27,rs1_val == -2147483647 and fcsr == 0
/* opcode: fmv.h.x ; op1:x27; dest:f27; op1val:-0x7fffffff; valaddr_reg:x3;
val_offset:4*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f27, x27, 0, 0, x3, 4*4, x4, x1, x2,lw)
inst_5:// rs1==x26, rd==f26,rs1_val == 1227077728 and fcsr == 0
/* opcode: fmv.h.x ; op1:x26; dest:f26; op1val:0x4923b860; valaddr_reg:x3;
val_offset:5*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f26, x26, 0, 0, x3, 5*4, x4, x1, x2,lw)
inst_6:// rs1==x25, rd==f25,rs1_val == -1227077728 and fcsr == 0
/* opcode: fmv.h.x ; op1:x25; dest:f25; op1val:-0x4923b860; valaddr_reg:x3;
val_offset:6*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f25, x25, 0, 0, x3, 6*4, x4, x1, x2,lw)
inst_7:// rs1==x24, rd==f24,
/* opcode: fmv.h.x ; op1:x24; dest:f24; op1val:0x0; valaddr_reg:x3;
val_offset:7*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f24, x24, 0, 0, x3, 7*4, x4, x1, x2,lw)
inst_8:// rs1==x23, rd==f23,
/* opcode: fmv.h.x ; op1:x23; dest:f23; op1val:0x0; valaddr_reg:x3;
val_offset:8*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f23, x23, 0, 0, x3, 8*4, x4, x1, x2,lw)
inst_9:// rs1==x22, rd==f22,
/* opcode: fmv.h.x ; op1:x22; dest:f22; op1val:0x0; valaddr_reg:x3;
val_offset:9*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f22, x22, 0, 0, x3, 9*4, x4, x1, x2,lw)
inst_10:// rs1==x21, rd==f21,
/* opcode: fmv.h.x ; op1:x21; dest:f21; op1val:0x0; valaddr_reg:x3;
val_offset:10*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f21, x21, 0, 0, x3, 10*4, x4, x1, x2,lw)
inst_11:// rs1==x20, rd==f20,
/* opcode: fmv.h.x ; op1:x20; dest:f20; op1val:0x0; valaddr_reg:x3;
val_offset:11*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f20, x20, 0, 0, x3, 11*4, x4, x1, x2,lw)
inst_12:// rs1==x19, rd==f19,
/* opcode: fmv.h.x ; op1:x19; dest:f19; op1val:0x0; valaddr_reg:x3;
val_offset:12*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f19, x19, 0, 0, x3, 12*4, x4, x1, x2,lw)
inst_13:// rs1==x18, rd==f18,
/* opcode: fmv.h.x ; op1:x18; dest:f18; op1val:0x0; valaddr_reg:x3;
val_offset:13*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f18, x18, 0, 0, x3, 13*4, x4, x1, x2,lw)
inst_14:// rs1==x17, rd==f17,
/* opcode: fmv.h.x ; op1:x17; dest:f17; op1val:0x0; valaddr_reg:x3;
val_offset:14*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f17, x17, 0, 0, x3, 14*4, x4, x1, x2,lw)
inst_15:// rs1==x16, rd==f16,
/* opcode: fmv.h.x ; op1:x16; dest:f16; op1val:0x0; valaddr_reg:x3;
val_offset:15*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f16, x16, 0, 0, x3, 15*4, x4, x1, x2,lw)
inst_16:// rs1==x15, rd==f15,
/* opcode: fmv.h.x ; op1:x15; dest:f15; op1val:0x0; valaddr_reg:x3;
val_offset:16*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f15, x15, 0, 0, x3, 16*4, x4, x1, x2,lw)
inst_17:// rs1==x14, rd==f14,
/* opcode: fmv.h.x ; op1:x14; dest:f14; op1val:0x0; valaddr_reg:x3;
val_offset:17*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f14, x14, 0, 0, x3, 17*4, x4, x1, x2,lw)
inst_18:// rs1==x13, rd==f13,
/* opcode: fmv.h.x ; op1:x13; dest:f13; op1val:0x0; valaddr_reg:x3;
val_offset:18*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f13, x13, 0, 0, x3, 18*4, x4, x1, x2,lw)
inst_19:// rs1==x12, rd==f12,
/* opcode: fmv.h.x ; op1:x12; dest:f12; op1val:0x0; valaddr_reg:x3;
val_offset:19*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f12, x12, 0, 0, x3, 19*4, x4, x1, x2,lw)
inst_20:// rs1==x11, rd==f11,
/* opcode: fmv.h.x ; op1:x11; dest:f11; op1val:0x0; valaddr_reg:x3;
val_offset:20*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f11, x11, 0, 0, x3, 20*4, x4, x1, x2,lw)
inst_21:// rs1==x10, rd==f10,
/* opcode: fmv.h.x ; op1:x10; dest:f10; op1val:0x0; valaddr_reg:x3;
val_offset:21*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f10, x10, 0, 0, x3, 21*4, x4, x1, x2,lw)
inst_22:// rs1==x9, rd==f9,
/* opcode: fmv.h.x ; op1:x9; dest:f9; op1val:0x0; valaddr_reg:x3;
val_offset:22*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f9, x9, 0, 0, x3, 22*4, x4, x1, x2,lw)
inst_23:// rs1==x8, rd==f8,
/* opcode: fmv.h.x ; op1:x8; dest:f8; op1val:0x0; valaddr_reg:x3;
val_offset:23*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f8, x8, 0, 0, x3, 23*4, x4, x1, x2,lw)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==x7, rd==f7,
/* opcode: fmv.h.x ; op1:x7; dest:f7; op1val:0x0; valaddr_reg:x8;
val_offset:0*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f7, x7, 0, 0, x8, 0*4, x9, x1, x2,lw)
inst_25:// rs1==x6, rd==f6,
/* opcode: fmv.h.x ; op1:x6; dest:f6; op1val:0x0; valaddr_reg:x8;
val_offset:1*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f6, x6, 0, 0, x8, 1*4, x9, x1, x2,lw)
inst_26:// rs1==x5, rd==f5,
/* opcode: fmv.h.x ; op1:x5; dest:f5; op1val:0x0; valaddr_reg:x8;
val_offset:2*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f5, x5, 0, 0, x8, 2*4, x9, x1, x6,lw)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==x4, rd==f4,
/* opcode: fmv.h.x ; op1:x4; dest:f4; op1val:0x0; valaddr_reg:x8;
val_offset:3*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f4, x4, 0, 0, x8, 3*4, x9, x5, x6,lw)
inst_28:// rs1==x3, rd==f3,
/* opcode: fmv.h.x ; op1:x3; dest:f3; op1val:0x0; valaddr_reg:x8;
val_offset:4*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f3, x3, 0, 0, x8, 4*4, x9, x5, x6,lw)
inst_29:// rs1==x2, rd==f2,
/* opcode: fmv.h.x ; op1:x2; dest:f2; op1val:0x0; valaddr_reg:x8;
val_offset:5*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f2, x2, 0, 0, x8, 5*4, x9, x5, x6,lw)
inst_30:// rs1==x1, rd==f1,
/* opcode: fmv.h.x ; op1:x1; dest:f1; op1val:0x0; valaddr_reg:x8;
val_offset:6*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f1, x1, 0, 0, x8, 6*4, x9, x5, x6,lw)
inst_31:// rs1==x0, rd==f0,
/* opcode: fmv.h.x ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
val_offset:7*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f0, x0, 0, 0, x8, 7*4, x9, x5, x6,lw)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.word 0;
.word 1;
.word -1;
.word 2147483647;
.word -2147483647;
.word 1227077728;
.word -1227077728;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
test_dataset_1:
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

327
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmv.h.x_b26-01.S
View file

@ -1,327 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:38:56 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.h.x.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmv.h.x instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmv.h.x_b26 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmv.h.x_b26)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==x31, rd==f31,rs1_val == 0 and fcsr == 0
/* opcode: fmv.h.x ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:0*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f31, x31, 0, 0, x3, 0*4, x4, x1, x2,lw)
inst_1:// rs1==x30, rd==f30,rs1_val == 1 and fcsr == 0
/* opcode: fmv.h.x ; op1:x30; dest:f30; op1val:0x1; valaddr_reg:x3;
val_offset:1*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f30, x30, 0, 0, x3, 1*4, x4, x1, x2,lw)
inst_2:// rs1==x29, rd==f29,rs1_val == 2 and fcsr == 0
/* opcode: fmv.h.x ; op1:x29; dest:f29; op1val:0x2; valaddr_reg:x3;
val_offset:2*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f29, x29, 0, 0, x3, 2*4, x4, x1, x2,lw)
inst_3:// rs1==x28, rd==f28,rs1_val == 7 and fcsr == 0
/* opcode: fmv.h.x ; op1:x28; dest:f28; op1val:0x7; valaddr_reg:x3;
val_offset:3*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f28, x28, 0, 0, x3, 3*4, x4, x1, x2,lw)
inst_4:// rs1==x27, rd==f27,rs1_val == 15 and fcsr == 0
/* opcode: fmv.h.x ; op1:x27; dest:f27; op1val:0xf; valaddr_reg:x3;
val_offset:4*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f27, x27, 0, 0, x3, 4*4, x4, x1, x2,lw)
inst_5:// rs1==x26, rd==f26,rs1_val == 16 and fcsr == 0
/* opcode: fmv.h.x ; op1:x26; dest:f26; op1val:0x10; valaddr_reg:x3;
val_offset:5*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f26, x26, 0, 0, x3, 5*4, x4, x1, x2,lw)
inst_6:// rs1==x25, rd==f25,rs1_val == 45 and fcsr == 0
/* opcode: fmv.h.x ; op1:x25; dest:f25; op1val:0x2d; valaddr_reg:x3;
val_offset:6*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f25, x25, 0, 0, x3, 6*4, x4, x1, x2,lw)
inst_7:// rs1==x24, rd==f24,rs1_val == 123 and fcsr == 0
/* opcode: fmv.h.x ; op1:x24; dest:f24; op1val:0x7b; valaddr_reg:x3;
val_offset:7*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f24, x24, 0, 0, x3, 7*4, x4, x1, x2,lw)
inst_8:// rs1==x23, rd==f23,rs1_val == 253 and fcsr == 0
/* opcode: fmv.h.x ; op1:x23; dest:f23; op1val:0xfd; valaddr_reg:x3;
val_offset:8*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f23, x23, 0, 0, x3, 8*4, x4, x1, x2,lw)
inst_9:// rs1==x22, rd==f22,rs1_val == 398 and fcsr == 0
/* opcode: fmv.h.x ; op1:x22; dest:f22; op1val:0x18e; valaddr_reg:x3;
val_offset:9*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f22, x22, 0, 0, x3, 9*4, x4, x1, x2,lw)
inst_10:// rs1==x21, rd==f21,rs1_val == 676 and fcsr == 0
/* opcode: fmv.h.x ; op1:x21; dest:f21; op1val:0x2a4; valaddr_reg:x3;
val_offset:10*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f21, x21, 0, 0, x3, 10*4, x4, x1, x2,lw)
inst_11:// rs1==x20, rd==f20,rs1_val == 1094 and fcsr == 0
/* opcode: fmv.h.x ; op1:x20; dest:f20; op1val:0x446; valaddr_reg:x3;
val_offset:11*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f20, x20, 0, 0, x3, 11*4, x4, x1, x2,lw)
inst_12:// rs1==x19, rd==f19,rs1_val == 4055 and fcsr == 0
/* opcode: fmv.h.x ; op1:x19; dest:f19; op1val:0xfd7; valaddr_reg:x3;
val_offset:12*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f19, x19, 0, 0, x3, 12*4, x4, x1, x2,lw)
inst_13:// rs1==x18, rd==f18,rs1_val == 6781 and fcsr == 0
/* opcode: fmv.h.x ; op1:x18; dest:f18; op1val:0x1a7d; valaddr_reg:x3;
val_offset:13*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f18, x18, 0, 0, x3, 13*4, x4, x1, x2,lw)
inst_14:// rs1==x17, rd==f17,rs1_val == 9438 and fcsr == 0
/* opcode: fmv.h.x ; op1:x17; dest:f17; op1val:0x24de; valaddr_reg:x3;
val_offset:14*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f17, x17, 0, 0, x3, 14*4, x4, x1, x2,lw)
inst_15:// rs1==x16, rd==f16,rs1_val == 24575 and fcsr == 0
/* opcode: fmv.h.x ; op1:x16; dest:f16; op1val:0x5fff; valaddr_reg:x3;
val_offset:15*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f16, x16, 0, 0, x3, 15*4, x4, x1, x2,lw)
inst_16:// rs1==x15, rd==f15,rs1_val == 56436 and fcsr == 0
/* opcode: fmv.h.x ; op1:x15; dest:f15; op1val:0xdc74; valaddr_reg:x3;
val_offset:16*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f15, x15, 0, 0, x3, 16*4, x4, x1, x2,lw)
inst_17:// rs1==x14, rd==f14,rs1_val == 71376 and fcsr == 0
/* opcode: fmv.h.x ; op1:x14; dest:f14; op1val:0x116d0; valaddr_reg:x3;
val_offset:17*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f14, x14, 0, 0, x3, 17*4, x4, x1, x2,lw)
inst_18:// rs1==x13, rd==f13,rs1_val == 241276 and fcsr == 0
/* opcode: fmv.h.x ; op1:x13; dest:f13; op1val:0x3ae7c; valaddr_reg:x3;
val_offset:18*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f13, x13, 0, 0, x3, 18*4, x4, x1, x2,lw)
inst_19:// rs1==x12, rd==f12,rs1_val == 334857 and fcsr == 0
/* opcode: fmv.h.x ; op1:x12; dest:f12; op1val:0x51c09; valaddr_reg:x3;
val_offset:19*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f12, x12, 0, 0, x3, 19*4, x4, x1, x2,lw)
inst_20:// rs1==x11, rd==f11,rs1_val == 896618 and fcsr == 0
/* opcode: fmv.h.x ; op1:x11; dest:f11; op1val:0xdae6a; valaddr_reg:x3;
val_offset:20*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f11, x11, 0, 0, x3, 20*4, x4, x1, x2,lw)
inst_21:// rs1==x10, rd==f10,rs1_val == 1848861 and fcsr == 0
/* opcode: fmv.h.x ; op1:x10; dest:f10; op1val:0x1c361d; valaddr_reg:x3;
val_offset:21*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f10, x10, 0, 0, x3, 21*4, x4, x1, x2,lw)
inst_22:// rs1==x9, rd==f9,rs1_val == 3864061 and fcsr == 0
/* opcode: fmv.h.x ; op1:x9; dest:f9; op1val:0x3af5fd; valaddr_reg:x3;
val_offset:22*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f9, x9, 0, 0, x3, 22*4, x4, x1, x2,lw)
inst_23:// rs1==x8, rd==f8,rs1_val == 6573466 and fcsr == 0
/* opcode: fmv.h.x ; op1:x8; dest:f8; op1val:0x644d9a; valaddr_reg:x3;
val_offset:23*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f8, x8, 0, 0, x3, 23*4, x4, x1, x2,lw)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==x7, rd==f7,rs1_val == 12789625 and fcsr == 0
/* opcode: fmv.h.x ; op1:x7; dest:f7; op1val:0xc32779; valaddr_reg:x8;
val_offset:0*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f7, x7, 0, 0, x8, 0*4, x9, x1, x2,lw)
inst_25:// rs1==x6, rd==f6,rs1_val == 32105925 and fcsr == 0
/* opcode: fmv.h.x ; op1:x6; dest:f6; op1val:0x1e9e5c5; valaddr_reg:x8;
val_offset:1*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f6, x6, 0, 0, x8, 1*4, x9, x1, x2,lw)
inst_26:// rs1==x5, rd==f5,rs1_val == 45276376 and fcsr == 0
/* opcode: fmv.h.x ; op1:x5; dest:f5; op1val:0x2b2dcd8; valaddr_reg:x8;
val_offset:2*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f5, x5, 0, 0, x8, 2*4, x9, x1, x6,lw)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==x4, rd==f4,rs1_val == 107790943 and fcsr == 0
/* opcode: fmv.h.x ; op1:x4; dest:f4; op1val:0x66cc25f; valaddr_reg:x8;
val_offset:3*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f4, x4, 0, 0, x8, 3*4, x9, x5, x6,lw)
inst_28:// rs1==x3, rd==f3,rs1_val == 231549045 and fcsr == 0
/* opcode: fmv.h.x ; op1:x3; dest:f3; op1val:0xdcd2875; valaddr_reg:x8;
val_offset:4*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f3, x3, 0, 0, x8, 4*4, x9, x5, x6,lw)
inst_29:// rs1==x2, rd==f2,rs1_val == 339827553 and fcsr == 0
/* opcode: fmv.h.x ; op1:x2; dest:f2; op1val:0x14415b61; valaddr_reg:x8;
val_offset:5*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f2, x2, 0, 0, x8, 5*4, x9, x5, x6,lw)
inst_30:// rs1==x1, rd==f1,rs1_val == 1027494066 and fcsr == 0
/* opcode: fmv.h.x ; op1:x1; dest:f1; op1val:0x3d3e50b2; valaddr_reg:x8;
val_offset:6*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f1, x1, 0, 0, x8, 6*4, x9, x5, x6,lw)
inst_31:// rs1==x0, rd==f0,rs1_val == 1587807073 and fcsr == 0
/* opcode: fmv.h.x ; op1:x0; dest:f0; op1val:0x0; valaddr_reg:x8;
val_offset:7*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f0, x0, 0, 0, x8, 7*4, x9, x5, x6,lw)
inst_32:// rs1_val == 1587807073 and fcsr == 0
/* opcode: fmv.h.x ; op1:x31; dest:f31; op1val:0x5ea40361; valaddr_reg:x8;
val_offset:8*4; correctval:??; testreg:x6;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fmv.h.x, f31, x31, 0, 0, x8, 8*4, x9, x5, x6,lw)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.word 0;
.word 1;
.word 2;
.word 7;
.word 15;
.word 16;
.word 45;
.word 123;
.word 253;
.word 398;
.word 676;
.word 1094;
.word 4055;
.word 6781;
.word 9438;
.word 24575;
.word 56436;
.word 71376;
.word 241276;
.word 334857;
.word 896618;
.word 1848861;
.word 3864061;
.word 6573466;
test_dataset_1:
.word 12789625;
.word 32105925;
.word 45276376;
.word 107790943;
.word 231549045;
.word 339827553;
.word 1027494066;
.word 0;
.word 1587807073;
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 12*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmv.x.h_b1-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:39:22 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.x.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmv.x.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmv.x.h_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmv.x.h_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0
/* opcode: fmv.x.h ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000 and fcsr == 0
/* opcode: fmv.x.h ; op1:f30; dest:x30; op1val:0x8000; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0
/* opcode: fmv.x.h ; op1:f29; dest:x29; op1val:0x1; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x00 and fm1 == 0x001 and fcsr == 0
/* opcode: fmv.x.h ; op1:f28; dest:x28; op1val:0x8001; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x002 and fcsr == 0
/* opcode: fmv.x.h ; op1:f27; dest:x27; op1val:0x2; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3fe and fcsr == 0
/* opcode: fmv.x.h ; op1:f26; dest:x26; op1val:0x83fe; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0
/* opcode: fmv.x.h ; op1:f25; dest:x25; op1val:0x3ff; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x00 and fm1 == 0x3ff and fcsr == 0
/* opcode: fmv.x.h ; op1:f24; dest:x24; op1val:0x83ff; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0
/* opcode: fmv.x.h ; op1:f23; dest:x23; op1val:0x400; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:// rs1==f22, rd==x22,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000 and fcsr == 0
/* opcode: fmv.x.h ; op1:f22; dest:x22; op1val:0x8400; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:// rs1==f21, rd==x21,fs1 == 0 and fe1 == 0x01 and fm1 == 0x001 and fcsr == 0
/* opcode: fmv.x.h ; op1:f21; dest:x21; op1val:0x401; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:// rs1==f20, rd==x20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055 and fcsr == 0
/* opcode: fmv.x.h ; op1:f20; dest:x20; op1val:0x8455; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0
/* opcode: fmv.x.h ; op1:f19; dest:x19; op1val:0x7bff; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:// rs1==f18, rd==x18,fs1 == 1 and fe1 == 0x1e and fm1 == 0x3ff and fcsr == 0
/* opcode: fmv.x.h ; op1:f18; dest:x18; op1val:0xfbff; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0
/* opcode: fmv.x.h ; op1:f17; dest:x17; op1val:0x7c00; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x1f and fm1 == 0x000 and fcsr == 0
/* opcode: fmv.x.h ; op1:f16; dest:x16; op1val:0xfc00; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:// rs1==f15, rd==x15,fs1 == 0 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0
/* opcode: fmv.x.h ; op1:f15; dest:x15; op1val:0x7e00; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:// rs1==f14, rd==x14,fs1 == 1 and fe1 == 0x1f and fm1 == 0x200 and fcsr == 0
/* opcode: fmv.x.h ; op1:f14; dest:x14; op1val:0xfe00; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0
/* opcode: fmv.x.h ; op1:f13; dest:x13; op1val:0x7e01; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0
/* opcode: fmv.x.h ; op1:f12; dest:x12; op1val:0xfe55; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:// rs1==f11, rd==x11,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0
/* opcode: fmv.x.h ; op1:f11; dest:x11; op1val:0x7c01; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:// rs1==f10, rd==x10,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0
/* opcode: fmv.x.h ; op1:f10; dest:x10; op1val:0xfd55; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0
/* opcode: fmv.x.h ; op1:f9; dest:x9; op1val:0x3c00; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:// rs1==f8, rd==x8,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0
/* opcode: fmv.x.h ; op1:f8; dest:x8; op1val:0xbc00; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,
/* opcode: fmv.x.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
inst_25:// rs1==f6, rd==x6,
/* opcode: fmv.x.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
inst_26:// rs1==f5, rd==x5,
/* opcode: fmv.x.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
val_offset:2*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,
/* opcode: fmv.x.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
val_offset:3*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
inst_28:// rs1==f3, rd==x3,
/* opcode: fmv.x.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
inst_29:// rs1==f2, rd==x2,
/* opcode: fmv.x.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
inst_30:// rs1==f1, rd==x1,
/* opcode: fmv.x.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
inst_31:// rs1==f0, rd==x0,
/* opcode: fmv.x.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(18446744073709486080,32,FLEN)
NAN_BOXED(18446744073709518848,32,FLEN)
NAN_BOXED(18446744073709486081,32,FLEN)
NAN_BOXED(18446744073709518849,32,FLEN)
NAN_BOXED(18446744073709486082,32,FLEN)
NAN_BOXED(18446744073709519870,32,FLEN)
NAN_BOXED(18446744073709487103,32,FLEN)
NAN_BOXED(18446744073709519871,32,FLEN)
NAN_BOXED(18446744073709487104,32,FLEN)
NAN_BOXED(18446744073709519872,32,FLEN)
NAN_BOXED(18446744073709487105,32,FLEN)
NAN_BOXED(18446744073709519957,32,FLEN)
NAN_BOXED(18446744073709517823,32,FLEN)
NAN_BOXED(18446744073709550591,32,FLEN)
NAN_BOXED(18446744073709517824,32,FLEN)
NAN_BOXED(18446744073709550592,32,FLEN)
NAN_BOXED(18446744073709518336,32,FLEN)
NAN_BOXED(18446744073709551104,32,FLEN)
NAN_BOXED(18446744073709518337,32,FLEN)
NAN_BOXED(18446744073709551189,32,FLEN)
NAN_BOXED(18446744073709517825,32,FLEN)
NAN_BOXED(18446744073709550933,32,FLEN)
NAN_BOXED(18446744073709501440,32,FLEN)
NAN_BOXED(18446744073709534208,32,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmv.x.h_b22-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:39:22 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.x.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmv.x.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmv.x.h_b22 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmv.x.h_b22)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x0c and fm1 == 0x249 and fcsr == 0
/* opcode: fmv.x.h ; op1:f31; dest:x31; op1val:0x3249; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x0d and fm1 == 0x1b7 and fcsr == 0
/* opcode: fmv.x.h ; op1:f30; dest:x30; op1val:0x35b7; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0e and fm1 == 0x24f and fcsr == 0
/* opcode: fmv.x.h ; op1:f29; dest:x29; op1val:0x3a4f; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0f and fm1 == 0x0d3 and fcsr == 0
/* opcode: fmv.x.h ; op1:f28; dest:x28; op1val:0x3cd3; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x10 and fm1 == 0x340 and fcsr == 0
/* opcode: fmv.x.h ; op1:f27; dest:x27; op1val:0x4340; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x11 and fm1 == 0x34b and fcsr == 0
/* opcode: fmv.x.h ; op1:f26; dest:x26; op1val:0x474b; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x07 and fm1 == 0x29d and fcsr == 0
/* opcode: fmv.x.h ; op1:f25; dest:x25; op1val:0x9e9d; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x04 and fm1 == 0x023 and fcsr == 0
/* opcode: fmv.x.h ; op1:f24; dest:x24; op1val:0x1023; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:// rs1==f23, rd==x23,
/* opcode: fmv.x.h ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:// rs1==f22, rd==x22,
/* opcode: fmv.x.h ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:// rs1==f21, rd==x21,
/* opcode: fmv.x.h ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:// rs1==f20, rd==x20,
/* opcode: fmv.x.h ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:// rs1==f19, rd==x19,
/* opcode: fmv.x.h ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:// rs1==f18, rd==x18,
/* opcode: fmv.x.h ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:// rs1==f17, rd==x17,
/* opcode: fmv.x.h ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:// rs1==f16, rd==x16,
/* opcode: fmv.x.h ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:// rs1==f15, rd==x15,
/* opcode: fmv.x.h ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:// rs1==f14, rd==x14,
/* opcode: fmv.x.h ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:// rs1==f13, rd==x13,
/* opcode: fmv.x.h ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:// rs1==f12, rd==x12,
/* opcode: fmv.x.h ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:// rs1==f11, rd==x11,
/* opcode: fmv.x.h ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:// rs1==f10, rd==x10,
/* opcode: fmv.x.h ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:// rs1==f9, rd==x9,
/* opcode: fmv.x.h ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:// rs1==f8, rd==x8,
/* opcode: fmv.x.h ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,
/* opcode: fmv.x.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
inst_25:// rs1==f6, rd==x6,
/* opcode: fmv.x.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
inst_26:// rs1==f5, rd==x5,
/* opcode: fmv.x.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
val_offset:2*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,
/* opcode: fmv.x.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
val_offset:3*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
inst_28:// rs1==f3, rd==x3,
/* opcode: fmv.x.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
inst_29:// rs1==f2, rd==x2,
/* opcode: fmv.x.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
inst_30:// rs1==f1, rd==x1,
/* opcode: fmv.x.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
inst_31:// rs1==f0, rd==x0,
/* opcode: fmv.x.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(18446744073709498953,32,FLEN)
NAN_BOXED(18446744073709499831,32,FLEN)
NAN_BOXED(18446744073709501007,32,FLEN)
NAN_BOXED(18446744073709501651,32,FLEN)
NAN_BOXED(18446744073709503296,32,FLEN)
NAN_BOXED(18446744073709504331,32,FLEN)
NAN_BOXED(18446744073709526685,32,FLEN)
NAN_BOXED(18446744073709490211,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmv.x.h_b23-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:39:22 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.x.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmv.x.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmv.x.h_b23 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmv.x.h_b23)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fc and fcsr == 0
/* opcode: fmv.x.h ; op1:f31; dest:x31; op1val:0x77fc; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:// rs1==f30, rd==x30,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fd and fcsr == 0
/* opcode: fmv.x.h ; op1:f30; dest:x30; op1val:0x77fd; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3fe and fcsr == 0
/* opcode: fmv.x.h ; op1:f29; dest:x29; op1val:0x77fe; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x1d and fm1 == 0x3ff and fcsr == 0
/* opcode: fmv.x.h ; op1:f28; dest:x28; op1val:0x77ff; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1e and fm1 == 0x000 and fcsr == 0
/* opcode: fmv.x.h ; op1:f27; dest:x27; op1val:0x7800; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:// rs1==f26, rd==x26,fs1 == 0 and fe1 == 0x1e and fm1 == 0x001 and fcsr == 0
/* opcode: fmv.x.h ; op1:f26; dest:x26; op1val:0x7801; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1e and fm1 == 0x002 and fcsr == 0
/* opcode: fmv.x.h ; op1:f25; dest:x25; op1val:0x7802; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x1e and fm1 == 0x003 and fcsr == 0
/* opcode: fmv.x.h ; op1:f24; dest:x24; op1val:0x7803; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x1e and fm1 == 0x004 and fcsr == 0
/* opcode: fmv.x.h ; op1:f23; dest:x23; op1val:0x7804; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:// rs1==f22, rd==x22,
/* opcode: fmv.x.h ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:// rs1==f21, rd==x21,
/* opcode: fmv.x.h ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:// rs1==f20, rd==x20,
/* opcode: fmv.x.h ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:// rs1==f19, rd==x19,
/* opcode: fmv.x.h ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:// rs1==f18, rd==x18,
/* opcode: fmv.x.h ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:// rs1==f17, rd==x17,
/* opcode: fmv.x.h ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:// rs1==f16, rd==x16,
/* opcode: fmv.x.h ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:// rs1==f15, rd==x15,
/* opcode: fmv.x.h ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:// rs1==f14, rd==x14,
/* opcode: fmv.x.h ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:// rs1==f13, rd==x13,
/* opcode: fmv.x.h ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:// rs1==f12, rd==x12,
/* opcode: fmv.x.h ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:// rs1==f11, rd==x11,
/* opcode: fmv.x.h ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:// rs1==f10, rd==x10,
/* opcode: fmv.x.h ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:// rs1==f9, rd==x9,
/* opcode: fmv.x.h ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:// rs1==f8, rd==x8,
/* opcode: fmv.x.h ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,
/* opcode: fmv.x.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
inst_25:// rs1==f6, rd==x6,
/* opcode: fmv.x.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
inst_26:// rs1==f5, rd==x5,
/* opcode: fmv.x.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
val_offset:2*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,
/* opcode: fmv.x.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
val_offset:3*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
inst_28:// rs1==f3, rd==x3,
/* opcode: fmv.x.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
inst_29:// rs1==f2, rd==x2,
/* opcode: fmv.x.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
inst_30:// rs1==f1, rd==x1,
/* opcode: fmv.x.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
inst_31:// rs1==f0, rd==x0,
/* opcode: fmv.x.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(18446744073709516796,32,FLEN)
NAN_BOXED(18446744073709516797,32,FLEN)
NAN_BOXED(18446744073709516798,32,FLEN)
NAN_BOXED(18446744073709516799,32,FLEN)
NAN_BOXED(18446744073709516800,32,FLEN)
NAN_BOXED(18446744073709516801,32,FLEN)
NAN_BOXED(18446744073709516802,32,FLEN)
NAN_BOXED(18446744073709516803,32,FLEN)
NAN_BOXED(18446744073709516804,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmv.x.h_b24-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:39:22 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.x.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmv.x.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmv.x.h_b24 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmv.x.h_b24)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0
/* opcode: fmv.x.h ; op1:f31; dest:x31; op1val:0x211e; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0
/* opcode: fmv.x.h ; op1:f30; dest:x30; op1val:0xbc00; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0
/* opcode: fmv.x.h ; op1:f29; dest:x29; op1val:0x3c0a; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:// rs1==f28, rd==x28,fs1 == 0 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0
/* opcode: fmv.x.h ; op1:f28; dest:x28; op1val:0x3b1e; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0
/* opcode: fmv.x.h ; op1:f27; dest:x27; op1val:0x3beb; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0
/* opcode: fmv.x.h ; op1:f26; dest:x26; op1val:0xbb33; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0
/* opcode: fmv.x.h ; op1:f25; dest:x25; op1val:0xaf0a; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:// rs1==f24, rd==x24,fs1 == 0 and fe1 == 0x0e and fm1 == 0x333 and fcsr == 0
/* opcode: fmv.x.h ; op1:f24; dest:x24; op1val:0x3b33; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:// rs1==f23, rd==x23,fs1 == 0 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0
/* opcode: fmv.x.h ; op1:f23; dest:x23; op1val:0x3c70; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:// rs1==f22, rd==x22,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0f0 and fcsr == 0
/* opcode: fmv.x.h ; op1:f22; dest:x22; op1val:0xf0; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:// rs1==f21, rd==x21,fs1 == 1 and fe1 == 0x0f and fm1 == 0x00a and fcsr == 0
/* opcode: fmv.x.h ; op1:f21; dest:x21; op1val:0xbc0a; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:// rs1==f20, rd==x20,fs1 == 0 and fe1 == 0x0f and fm1 == 0x000 and fcsr == 0
/* opcode: fmv.x.h ; op1:f20; dest:x20; op1val:0x3c00; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:// rs1==f19, rd==x19,fs1 == 0 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0
/* opcode: fmv.x.h ; op1:f19; dest:x19; op1val:0x2e66; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:// rs1==f18, rd==x18,fs1 == 0 and fe1 == 0x0b and fm1 == 0x30a and fcsr == 0
/* opcode: fmv.x.h ; op1:f18; dest:x18; op1val:0x2f0a; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:// rs1==f17, rd==x17,fs1 == 1 and fe1 == 0x08 and fm1 == 0x11e and fcsr == 0
/* opcode: fmv.x.h ; op1:f17; dest:x17; op1val:0xa11e; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:// rs1==f16, rd==x16,fs1 == 1 and fe1 == 0x0f and fm1 == 0x070 and fcsr == 0
/* opcode: fmv.x.h ; op1:f16; dest:x16; op1val:0xbc70; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:// rs1==f15, rd==x15,fs1 == 1 and fe1 == 0x0b and fm1 == 0x266 and fcsr == 0
/* opcode: fmv.x.h ; op1:f15; dest:x15; op1val:0xae66; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:// rs1==f14, rd==x14,fs1 == 0 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0
/* opcode: fmv.x.h ; op1:f14; dest:x14; op1val:0x3c66; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:// rs1==f13, rd==x13,fs1 == 1 and fe1 == 0x0e and fm1 == 0x31e and fcsr == 0
/* opcode: fmv.x.h ; op1:f13; dest:x13; op1val:0xbb1e; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:// rs1==f12, rd==x12,fs1 == 1 and fe1 == 0x0f and fm1 == 0x066 and fcsr == 0
/* opcode: fmv.x.h ; op1:f12; dest:x12; op1val:0xbc66; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:// rs1==f11, rd==x11,fs1 == 1 and fe1 == 0x0e and fm1 == 0x3eb and fcsr == 0
/* opcode: fmv.x.h ; op1:f11; dest:x11; op1val:0xbbeb; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:// rs1==f10, rd==x10,
/* opcode: fmv.x.h ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:// rs1==f9, rd==x9,
/* opcode: fmv.x.h ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:// rs1==f8, rd==x8,
/* opcode: fmv.x.h ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,
/* opcode: fmv.x.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
inst_25:// rs1==f6, rd==x6,
/* opcode: fmv.x.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
inst_26:// rs1==f5, rd==x5,
/* opcode: fmv.x.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
val_offset:2*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,
/* opcode: fmv.x.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
val_offset:3*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
inst_28:// rs1==f3, rd==x3,
/* opcode: fmv.x.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
inst_29:// rs1==f2, rd==x2,
/* opcode: fmv.x.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
inst_30:// rs1==f1, rd==x1,
/* opcode: fmv.x.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
inst_31:// rs1==f0, rd==x0,
/* opcode: fmv.x.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(18446744073709494558,32,FLEN)
NAN_BOXED(18446744073709534208,32,FLEN)
NAN_BOXED(18446744073709501450,32,FLEN)
NAN_BOXED(18446744073709501214,32,FLEN)
NAN_BOXED(18446744073709501419,32,FLEN)
NAN_BOXED(18446744073709534003,32,FLEN)
NAN_BOXED(18446744073709530890,32,FLEN)
NAN_BOXED(18446744073709501235,32,FLEN)
NAN_BOXED(18446744073709501552,32,FLEN)
NAN_BOXED(18446744073709486320,32,FLEN)
NAN_BOXED(18446744073709534218,32,FLEN)
NAN_BOXED(18446744073709501440,32,FLEN)
NAN_BOXED(18446744073709497958,32,FLEN)
NAN_BOXED(18446744073709498122,32,FLEN)
NAN_BOXED(18446744073709527326,32,FLEN)
NAN_BOXED(18446744073709534320,32,FLEN)
NAN_BOXED(18446744073709530726,32,FLEN)
NAN_BOXED(18446744073709501542,32,FLEN)
NAN_BOXED(18446744073709533982,32,FLEN)
NAN_BOXED(18446744073709534310,32,FLEN)
NAN_BOXED(18446744073709534187,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

320
tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/Zfh/src/fmv.x.h_b27-01.S
View file

@ -1,320 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.11.0
// timestamp : Mon May 8 04:39:22 2023 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32H/rv32h_fmv.x.h.cgf \
\
// -- xlen 32 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fmv.x.h instruction of the RISC-V RV32F_Zicsr_Zfh,RV64F_Zicsr_Zfh extension for the fmv.x.h_b27 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IF_Zicsr_Zfh,RV64IF_Zicsr_Zfh")
.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*F.*Zfh.*);def TEST_CASE_1=True;",fmv.x.h_b27)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0
/* opcode: fmv.x.h ; op1:f31; dest:x31; op1val:0x7c01; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x31, f31, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:// rs1==f30, rd==x30,fs1 == 1 and fe1 == 0x1f and fm1 == 0x001 and fcsr == 0
/* opcode: fmv.x.h ; op1:f30; dest:x30; op1val:0xfc01; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x30, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:// rs1==f29, rd==x29,fs1 == 0 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0
/* opcode: fmv.x.h ; op1:f29; dest:x29; op1val:0x7d55; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x29, f29, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:// rs1==f28, rd==x28,fs1 == 1 and fe1 == 0x1f and fm1 == 0x155 and fcsr == 0
/* opcode: fmv.x.h ; op1:f28; dest:x28; op1val:0xfd55; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x28, f28, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:// rs1==f27, rd==x27,fs1 == 0 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0
/* opcode: fmv.x.h ; op1:f27; dest:x27; op1val:0x7e01; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x27, f27, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:// rs1==f26, rd==x26,fs1 == 1 and fe1 == 0x1f and fm1 == 0x201 and fcsr == 0
/* opcode: fmv.x.h ; op1:f26; dest:x26; op1val:0xfe01; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x26, f26, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:// rs1==f25, rd==x25,fs1 == 0 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0
/* opcode: fmv.x.h ; op1:f25; dest:x25; op1val:0x7e55; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x25, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x1f and fm1 == 0x255 and fcsr == 0
/* opcode: fmv.x.h ; op1:f24; dest:x24; op1val:0xfe55; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x24, f24, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:// rs1==f23, rd==x23,
/* opcode: fmv.x.h ; op1:f23; dest:x23; op1val:0x0; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x23, f23, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:// rs1==f22, rd==x22,
/* opcode: fmv.x.h ; op1:f22; dest:x22; op1val:0x0; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x22, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:// rs1==f21, rd==x21,
/* opcode: fmv.x.h ; op1:f21; dest:x21; op1val:0x0; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x21, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:// rs1==f20, rd==x20,
/* opcode: fmv.x.h ; op1:f20; dest:x20; op1val:0x0; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x20, f20, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:// rs1==f19, rd==x19,
/* opcode: fmv.x.h ; op1:f19; dest:x19; op1val:0x0; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x19, f19, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:// rs1==f18, rd==x18,
/* opcode: fmv.x.h ; op1:f18; dest:x18; op1val:0x0; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x18, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:// rs1==f17, rd==x17,
/* opcode: fmv.x.h ; op1:f17; dest:x17; op1val:0x0; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x17, f17, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:// rs1==f16, rd==x16,
/* opcode: fmv.x.h ; op1:f16; dest:x16; op1val:0x0; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x16, f16, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:// rs1==f15, rd==x15,
/* opcode: fmv.x.h ; op1:f15; dest:x15; op1val:0x0; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x15, f15, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:// rs1==f14, rd==x14,
/* opcode: fmv.x.h ; op1:f14; dest:x14; op1val:0x0; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x14, f14, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:// rs1==f13, rd==x13,
/* opcode: fmv.x.h ; op1:f13; dest:x13; op1val:0x0; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x13, f13, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:// rs1==f12, rd==x12,
/* opcode: fmv.x.h ; op1:f12; dest:x12; op1val:0x0; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x12, f12, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:// rs1==f11, rd==x11,
/* opcode: fmv.x.h ; op1:f11; dest:x11; op1val:0x0; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x11, f11, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:// rs1==f10, rd==x10,
/* opcode: fmv.x.h ; op1:f10; dest:x10; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x10, f10, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:// rs1==f9, rd==x9,
/* opcode: fmv.x.h ; op1:f9; dest:x9; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x9, f9, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:// rs1==f8, rd==x8,
/* opcode: fmv.x.h ; op1:f8; dest:x8; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x8, f8, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
RVTEST_VALBASEUPD(x8,test_dataset_1)
inst_24:// rs1==f7, rd==x7,
/* opcode: fmv.x.h ; op1:f7; dest:x7; op1val:0x0; valaddr_reg:x8;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x7, f7, 0, 0, x8, 0*FLEN/8, x9, x1, x2)
inst_25:// rs1==f6, rd==x6,
/* opcode: fmv.x.h ; op1:f6; dest:x6; op1val:0x0; valaddr_reg:x8;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x6, f6, 0, 0, x8, 1*FLEN/8, x9, x1, x2)
inst_26:// rs1==f5, rd==x5,
/* opcode: fmv.x.h ; op1:f5; dest:x5; op1val:0x0; valaddr_reg:x8;
val_offset:2*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x5, f5, 0, 0, x8, 2*FLEN/8, x9, x1, x6)
RVTEST_SIGBASE(x5,signature_x5_0)
inst_27:// rs1==f4, rd==x4,
/* opcode: fmv.x.h ; op1:f4; dest:x4; op1val:0x0; valaddr_reg:x8;
val_offset:3*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x4, f4, 0, 0, x8, 3*FLEN/8, x9, x5, x6)
inst_28:// rs1==f3, rd==x3,
/* opcode: fmv.x.h ; op1:f3; dest:x3; op1val:0x0; valaddr_reg:x8;
val_offset:4*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x3, f3, 0, 0, x8, 4*FLEN/8, x9, x5, x6)
inst_29:// rs1==f2, rd==x2,
/* opcode: fmv.x.h ; op1:f2; dest:x2; op1val:0x0; valaddr_reg:x8;
val_offset:5*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x2, f2, 0, 0, x8, 5*FLEN/8, x9, x5, x6)
inst_30:// rs1==f1, rd==x1,
/* opcode: fmv.x.h ; op1:f1; dest:x1; op1val:0x0; valaddr_reg:x8;
val_offset:6*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x1, f1, 0, 0, x8, 6*FLEN/8, x9, x5, x6)
inst_31:// rs1==f0, rd==x0,
/* opcode: fmv.x.h ; op1:f0; dest:x0; op1val:0x0; valaddr_reg:x8;
val_offset:7*FLEN/8; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP_NRM(fmv.x.h, x0, f0, 0, 0, x8, 7*FLEN/8, x9, x5, x6)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(18446744073709517825,32,FLEN)
NAN_BOXED(18446744073709550593,32,FLEN)
NAN_BOXED(18446744073709518165,32,FLEN)
NAN_BOXED(18446744073709550933,32,FLEN)
NAN_BOXED(18446744073709518337,32,FLEN)
NAN_BOXED(18446744073709551105,32,FLEN)
NAN_BOXED(18446744073709518421,32,FLEN)
NAN_BOXED(18446744073709551189,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
test_dataset_1:
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
NAN_BOXED(0,32,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*XLEN/32,4,0xdeadbeef
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

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