mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-04-24 13:57:07 -04:00
Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing.
This commit is contained in:
Ross Thompson
parent
b8572d6a2a
commit
4af7a27d87
7 changed files with 150 additions and 175 deletions
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@ -90,23 +90,6 @@ module clkdivider #(parameter integer g_COUNT_WIDTH)
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generate
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if(`FPGA) begin
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/* -----\/----- EXCLUDED -----\/-----
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logic CLKDiv8, CLKDiv64;
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BUFGCE_DIV #("8") clkDivider1(.I(i_CLK),
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.CLR(i_RST),
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.CE(1'b1),
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.O(CLKDiv8));
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BUFGCE_DIV #("8") clkDivider2(.I(CLKDiv8),
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.CLR(i_RST),
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.CE(1'b1),
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.O(CLKDiv64));
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BUFGMUX clkMux(.I1(CLKDiv64),
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.I0(i_CLK),
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.S(i_EN),
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.O(o_CLK));
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-----/\----- EXCLUDED -----/\----- */
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BUFGMUX
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clkMux(.I1(r_fd_Q),
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.I0(i_CLK),
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@ -33,76 +33,77 @@ module sd_cmd_fsm
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input logic i_RST, // reset FSM,
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// MUST COME OUT OF RESET
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// SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
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(* mark_debug = "true" *) output logic o_TIMER_LOAD, o_TIMER_EN, // Timer
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(* mark_debug = "true" *) output logic [18:0] o_TIMER_IN,
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(* mark_debug = "true" *) input logic [18:0] i_TIMER_OUT,
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(* mark_debug = "true" *) output logic o_COUNTER_LOAD, o_COUNTER_EN, // Counter
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(* mark_debug = "true" *) output logic [7:0] o_COUNTER_IN,
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(* mark_debug = "true" *) input logic [7:0] i_COUNTER_OUT,
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(* mark_debug = "true" *) output logic o_SD_CLK_EN, // Clock Gaters
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(* mark_debug = "true" *) input logic i_CLOCK_CHANGE_DONE, // Communication with CLK_FSM
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(* mark_debug = "true" *) output logic o_START_CLOCK_CHANGE, // Communication with CLK_FSM
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(* mark_debug = "true" *) output logic o_IC_RST, o_IC_EN, o_IC_UP_DOWN, // Instruction counter
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(* mark_debug = "true" *) input logic [3:0] i_IC_OUT, // stop when you get to 10 because that is CMD17
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(* mark_debug = "true" *) input logic [1:0] i_USES_DAT,
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(* mark_debug = "true" *) input logic [6:0] i_OPCODE,
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(* mark_debug = "true" *) input logic [2:0] i_R_TYPE,
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output logic o_TIMER_LOAD, o_TIMER_EN, // Timer
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output logic [18:0] o_TIMER_IN,
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input logic [18:0] i_TIMER_OUT,
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output logic o_COUNTER_LOAD, o_COUNTER_EN, // Counter
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output logic [7:0] o_COUNTER_IN,
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input logic [7:0] i_COUNTER_OUT,
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output logic o_SD_CLK_EN, // Clock Gaters
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input logic i_CLOCK_CHANGE_DONE, // Communication with CLK_FSM
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output logic o_START_CLOCK_CHANGE, // Communication with CLK_FSM
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output logic o_IC_RST, o_IC_EN, o_IC_UP_DOWN, // Instruction counter
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input logic [3:0] i_IC_OUT, // stop when you get to 10 because that is CMD17
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input logic [1:0] i_USES_DAT,
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input logic [6:0] i_OPCODE,
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input logic [2:0] i_R_TYPE,
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// bit masks
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(* mark_debug = "true" *) input logic [31:0] i_NO_REDO_MASK,
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(* mark_debug = "true" *) input logic [31:0] i_NO_REDO_ANS,
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(* mark_debug = "true" *) input logic [31:0] i_NO_ERROR_MASK,
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(* mark_debug = "true" *) input logic [31:0] i_NO_ERROR_ANS,
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input logic [31:0] i_NO_REDO_MASK,
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input logic [31:0] i_NO_REDO_ANS,
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input logic [31:0] i_NO_ERROR_MASK,
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input logic [31:0] i_NO_ERROR_ANS,
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(* mark_debug = "true" *) output logic o_SD_CMD_OE, // Enable ouptut on tri-state SD_CMD line
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// TX Components
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(* mark_debug = "true" *) output logic o_TX_PISO40_LOAD, o_TX_PISO40_EN, // Shift register for TX command head
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(* mark_debug = "true" *) output logic o_TX_PISO8_LOAD, o_TX_PISO8_EN, // Shift register for TX command tail
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(* mark_debug = "true" *) output logic o_TX_CRC7_PIPO_RST, o_TX_CRC7_PIPO_EN, // Parallel-to-Parallel CRC7 Generator
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(* mark_debug = "true" *) output logic [1:0] o_TX_SOURCE_SELECT, // What gets sent to CMD_TX
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output logic o_TX_PISO40_LOAD, o_TX_PISO40_EN, // Shift register for TX command head
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output logic o_TX_PISO8_LOAD, o_TX_PISO8_EN, // Shift register for TX command tail
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output logic o_TX_CRC7_PIPO_RST, o_TX_CRC7_PIPO_EN, // Parallel-to-Parallel CRC7 Generator
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output logic [1:0] o_TX_SOURCE_SELECT, // What gets sent to CMD_TX
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// TX Memory
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(* mark_debug = "true" *) output logic o_CMD_TX_IS_CMD55_RST,
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(* mark_debug = "true" *) output logic o_CMD_TX_IS_CMD55_EN, // '1' means that the command that was just sent has index
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output logic o_CMD_TX_IS_CMD55_RST,
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output logic o_CMD_TX_IS_CMD55_EN, // '1' means that the command that was just sent has index
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// 55, so the subsequent command is to be
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// viewed as ACMD by the SD card.
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// RX Components
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(* mark_debug = "true" *) input logic i_SD_CMD_RX, // serial response input on SD_CMD
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(* mark_debug = "true" *) output logic o_RX_SIPO48_RST, o_RX_SIPO48_EN, // Shift Register for all 48 bits of Response
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input logic i_SD_CMD_RX, // serial response input on SD_CMD
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output logic o_RX_SIPO48_RST, o_RX_SIPO48_EN, // Shift Register for all 48 bits of Response
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(* mark_debug = "true" *) input logic [39:8] i_RESPONSE_CONTENT, // last 32 bits of RX_SIPO_40_OUT
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(* mark_debug = "true" *) input logic [45:40] i_RESPONSE_INDEX, // 6 bits from RX_SIPO_40_OUT
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(* mark_debug = "true" *) output logic o_RX_CRC7_SIPO_RST, o_RX_CRC7_SIPO_EN, // Serial-to-parallel CRC7 Generator
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(* mark_debug = "true" *) input logic [6:0] i_RX_CRC7,
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input logic [39:8] i_RESPONSE_CONTENT, // last 32 bits of RX_SIPO_40_OUT
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input logic [45:40] i_RESPONSE_INDEX, // 6 bits from RX_SIPO_40_OUT
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output logic o_RX_CRC7_SIPO_RST, o_RX_CRC7_SIPO_EN, // Serial-to-parallel CRC7 Generator
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input logic [6:0] i_RX_CRC7,
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// RX Memory
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(* mark_debug = "true" *) output logic o_RCA_REGISTER_RST, o_RCA_REGISTER_EN, // Relative Card Address
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output logic o_RCA_REGISTER_RST, o_RCA_REGISTER_EN, // Relative Card Address
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// Communication to sd_dat_fsm
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(* mark_debug = "true" *) output logic o_CMD_TX_DONE, // begin waiting for DAT_RX to complete
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(* mark_debug = "true" *) input logic i_DAT_RX_DONE, // now go to next state since data block rx was completed
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output logic o_CMD_TX_DONE, // begin waiting for DAT_RX to complete
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input logic i_DAT_RX_DONE, // now go to next state since data block rx was completed
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(* mark_debug = "true" *) input logic i_ERROR_CRC16, // repeat last command
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(* mark_debug = "true" *) input logic i_ERROR_DAT_TIMES_OUT,
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// Commnuication to core
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(* mark_debug = "true" *) output logic o_READY_FOR_READ, // tell core that I have completed initialization
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(* mark_debug = "true" *) output logic o_SD_RESTARTING, // inform core the need to restart
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(* mark_debug = "true" *) input logic i_READ_REQUEST, // core tells me to execute CMD17
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output logic o_READY_FOR_READ, // tell core that I have completed initialization
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output logic o_SD_RESTARTING, // inform core the need to restart
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input logic i_READ_REQUEST, // core tells me to execute CMD17
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// Communication to Host
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(* mark_debug = "true" *) output logic o_DAT_ERROR_FD_RST,
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(* mark_debug = "true" *) output logic [2:0] o_ERROR_CODE_Q, // Indicates what caused the fatal error
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(* mark_debug = "true" *) output logic o_FATAL_ERROR, // SD Card is damaged beyond recovery, restart entire initialization procedure of card
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(* mark_debug = "true" *) input logic LIMIT_SD_TIMERS
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output logic o_DAT_ERROR_FD_RST,
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output logic [2:0] o_ERROR_CODE_Q, // Indicates what caused the fatal error
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output logic o_FATAL_ERROR, // SD Card is damaged beyond recovery, restart entire initialization procedure of card
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input logic LIMIT_SD_TIMERS
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);
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(* mark_debug = "true" *) logic [4:0] w_next_state, r_curr_state;
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(* mark_debug = "true" *) logic w_resend_last_command, w_rx_crc7_check, w_rx_index_check, w_rx_bad_crc7, w_rx_bad_index, w_rx_bad_reply, w_bad_card;
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logic [4:0] w_next_state;
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(* mark_debug = "true" *) logic [4:0] r_curr_state;
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logic w_resend_last_command, w_rx_crc7_check, w_rx_index_check, w_rx_bad_crc7, w_rx_bad_index, w_rx_bad_reply, w_bad_card;
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(* mark_debug = "true" *) logic [31:0] w_redo_result, w_error_result;
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(* mark_debug = "true" *) logic w_ACMD41_init_done;
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(* mark_debug = "true" *) logic w_fail_cnt_en, w_fail_count_rst;
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(* mark_debug = "true" *) logic [10:0] r_fail_count_out;
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logic [31:0] w_redo_result, w_error_result;
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logic w_ACMD41_init_done;
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logic w_fail_cnt_en, w_fail_count_rst;
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logic [10:0] r_fail_count_out;
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(* mark_debug = "true" *) logic w_ACMD41_busy_timer_START, w_ACMD41_times_out_FLAG, w_ACMD41_busy_timer_RST; //give up after 1000 ms of ACMD41
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(* mark_debug = "true" *) logic [2:0] w_ERROR_CODE_D, r_ERROR_CODE_Q ; // Error Codes for fatal error on SD CMD FSM
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(* mark_debug = "true" *) logic w_ERROR_CODE_RST, w_ERROR_CODE_EN;
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(* mark_debug = "true" *) logic [18:0] Timer_In;
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logic w_ACMD41_busy_timer_START, w_ACMD41_times_out_FLAG, w_ACMD41_busy_timer_RST; //give up after 1000 ms of ACMD41
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logic [2:0] w_ERROR_CODE_D, r_ERROR_CODE_Q ; // Error Codes for fatal error on SD CMD FSM
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logic w_ERROR_CODE_RST, w_ERROR_CODE_EN;
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logic [18:0] Timer_In;
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localparam s_reset_clear_error_reg = 5'b00000;
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@ -29,45 +29,46 @@
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module sd_dat_fsm
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(
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input logic CLK, // HS Clock (48 MHz)
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input logic i_RST,
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input logic CLK, // HS Clock (48 MHz)
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input logic i_RST,
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// Timer module control
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input logic i_SD_CLK_SELECTED, // Which frequency I'm in determines what count in to load for a 100ms timer
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(* mark_debug = "true" *)output logic o_TIMER_LOAD, o_TIMER_EN, // Timer Control signals
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(* mark_debug = "true" *)output logic [22:0] o_TIMER_IN, // Need Enough bits for 100 milliseconds at 48MHz
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(* mark_debug = "true" *)input logic [22:0] i_TIMER_OUT, // (ceiling(log((clk freq)(delay desired)-1)/log(2))-1) downto 0
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input logic i_SD_CLK_SELECTED, // Which frequency I'm in determines what count in to load for a 100ms timer
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output logic o_TIMER_LOAD, o_TIMER_EN, // Timer Control signals
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output logic [22:0] o_TIMER_IN, // Need Enough bits for 100 milliseconds at 48MHz
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input logic [22:0] i_TIMER_OUT, // (ceiling(log((clk freq)(delay desired)-1)/log(2))-1) downto 0
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// Nibble counter module control
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(* mark_debug = "true" *)output logic o_COUNTER_RST, o_COUNTER_EN, // nibble counter
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(* mark_debug = "true" *)input logic [10:0] i_COUNTER_OUT, // max nibbles is 1024 + crc16 bits = 1040 bits
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output logic o_COUNTER_RST, o_COUNTER_EN, // nibble counter
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input logic [10:0] i_COUNTER_OUT, // max nibbles is 1024 + crc16 bits = 1040 bits
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// CRC16 Generation control
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(* mark_debug = "true" *)output logic o_CRC16_EN, o_CRC16_RST, // shared signals for all 4 CRC16_SIPO (one for each of 4 DAT lines)
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(* mark_debug = "true" *)input logic i_DATA_CRC16_GOOD, // indicates that no errors in transmission when CRC16 are all zero
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(* mark_debug = "true" *)output logic o_CRC16_EN, o_CRC16_RST, // shared signals for all 4 CRC16_SIPO (one for each of 4 DAT lines)
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(* mark_debug = "true" *)input logic i_DATA_CRC16_GOOD, // indicates that no errors in transmission when CRC16 are all zero
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// For R1b
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(* mark_debug = "true" *)output logic o_BUSY_RST, o_BUSY_EN, // busy signal for R1b
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output logic o_BUSY_RST, o_BUSY_EN, // busy signal for R1b
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(* mark_debug = "true" *)input logic i_DAT0_Q,
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// Storage Buffers for DAT bits read
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(* mark_debug = "true" *)output logic o_NIBO_EN, // 512 bytes block data (Nibble In Block Out)
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output logic o_NIBO_EN, // 512 bytes block data (Nibble In Block Out)
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// From LUT
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(* mark_debug = "true" *)input logic [1:0] i_USES_DAT, // current command needs use of DAT bus
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(* mark_debug = "true" *)input logic [1:0] i_USES_DAT, // current command needs use of DAT bus
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// For communicating with core
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(* mark_debug = "true" *)output logic o_DATA_VALID, // indicates that DATA being send over o_DATA to core is valid
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(* mark_debug = "true" *)output logic o_LAST_NIBBLE, // indicates that the last nibble has been sent
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output logic o_DATA_VALID, // indicates that DATA being send over o_DATA to core is valid
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output logic o_LAST_NIBBLE, // indicates that the last nibble has been sent
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// For communication with sd_cmd_fsm
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(* mark_debug = "true" *)input logic i_CMD_TX_DONE, // command transmission completed, begin waiting for DATA
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(* mark_debug = "true" *)output logic o_DAT_RX_DONE, // tell SD_CMD_FSM that DAT communication is completed, send next instruction to sd card
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(* mark_debug = "true" *)output logic o_ERROR_DAT_TIMES_OUT, // error flag for when DAT times out (so don't fetch more instructions)
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(* mark_debug = "true" *)input logic i_CMD_TX_DONE, // command transmission completed, begin waiting for DATA
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(* mark_debug = "true" *)output logic o_DAT_RX_DONE, // tell SD_CMD_FSM that DAT communication is completed, send next instruction to sd card
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(* mark_debug = "true" *)output logic o_ERROR_DAT_TIMES_OUT, // error flag for when DAT times out (so don't fetch more instructions)
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(* mark_debug = "true" *)output logic o_DAT_ERROR_FD_RST,
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(* mark_debug = "true" *)output logic o_DAT_ERROR_FD_EN, // tell SD_CMD_FSM to resend command due to error in transmission
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input logic LIMIT_SD_TIMERS
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(* mark_debug = "true" *)output logic o_DAT_ERROR_FD_EN, // tell SD_CMD_FSM to resend command due to error in transmission
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input logic LIMIT_SD_TIMERS
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);
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(* mark_debug = "true" *) logic [3:0] w_next_state, r_curr_state;
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(* mark_debug = "true" *) logic [3:0] r_curr_state;
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logic [3:0] w_next_state;
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(* mark_debug = "true" *) logic w_error_crc16_fd_en, w_error_crc16_fd_rst, w_error_crc16_fd_d; // Save ERROR_CRC16 so CMD FSM sees it in IDLE_NRC (not just in IDLE_DAT)
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logic r_error_crc16_fd_Q;
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(* mark_debug = "true" *) logic [22:0] Identify_Timer_In;
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(* mark_debug = "true" *) logic [22:0] Data_TX_Timer_In;
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logic [22:0] Identify_Timer_In;
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logic [22:0] Data_TX_Timer_In;
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localparam logic [3:0] s_reset = 4'b0000;
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localparam logic [3:0] s_idle = 4'b0001;
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@ -28,7 +28,7 @@
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module sd_top #(parameter g_COUNT_WIDTH = 8)
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(
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input logic CLK, // 1.2 GHz (1.0 GHz typical)
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(* mark_debug = "true" *)input logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
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input logic a_RST, // Reset signal (Must be held for minimum of 24 clock cycles)
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// a_RST MUST COME OUT OF RESET SYNCHRONIZED TO THE 1.2 GHZ CLOCK!
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// io_SD_CMD_z : inout std_logic; // SD CMD Bus
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(* mark_debug = "true" *)input logic i_SD_CMD, // CMD Response from card
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@ -156,41 +156,33 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
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localparam logic [127:96] c_ACMD55_ans_error_free = 32'h00000000;
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// SD_CMD_FSM Connections
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(* mark_debug = "true" *)logic w_TIMER_LOAD, w_TIMER_EN;
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(* mark_debug = "true" *)logic [18:0] w_TIMER_IN;
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(* mark_debug = "true" *)logic [18:0] r_TIMER_OUT;
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(* mark_debug = "true" *)logic w_COUNTER_LOAD, w_COUNTER_EN;
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(* mark_debug = "true" *)logic [7:0] w_COUNTER_IN;
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(* mark_debug = "true" *)logic [7:0] r_COUNTER_OUT;
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(* mark_debug = "true" *)logic w_SD_CLK_EN;
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(* mark_debug = "true" *)logic w_CLOCK_CHANGE_DONE, w_START_CLOCK_CHANGE; // to clk fsm
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(* mark_debug = "true" *)logic w_HS_TO_INIT_CLK_DIVIDER_RST;
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logic w_TIMER_LOAD, w_TIMER_EN;
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logic [18:0] w_TIMER_IN;
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logic [18:0] r_TIMER_OUT;
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logic w_COUNTER_LOAD, w_COUNTER_EN;
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logic [7:0] w_COUNTER_IN;
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logic [7:0] r_COUNTER_OUT;
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logic w_SD_CLK_EN;
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logic w_CLOCK_CHANGE_DONE, w_START_CLOCK_CHANGE; // to clk fsm
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logic w_HS_TO_INIT_CLK_DIVIDER_RST;
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(* mark_debug = "true" *)logic w_IC_RST, w_IC_EN, w_IC_UP_DOWN;
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//logic w_USES_DAT : std_logic_vector(1 downto 0);
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//logic w_OPCODE_Q : std_logic_vector(6 downto 0);
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//logic w_R_TYPE : std_logic_vector(2 downto 0);
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//logic w_NO_REDO_MASK : std_logic_vector(31 downto 0);
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//logic w_NO_REDO_ANS : std_logic_vector(31 downto 0);
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//logic w_NO_ERROR_MASK : std_logic_vector(31 downto 0);
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//logic w_NO_ERROR_ANS : std_logic_vector(31 downto 0);
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(* mark_debug = "true" *)logic w_SD_CMD_OE;
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//logic w_SD_CMD_IE : std_logic; // tri-state buffer - input enable (for simulation only)
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(* mark_debug = "true" *)logic w_TX_PISO40_LOAD, w_TX_PISO40_EN;
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(* mark_debug = "true" *)logic w_TX_PISO8_LOAD, w_TX_PISO8_EN;
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(* mark_debug = "true" *)logic w_TX_CRC7_PIPO_RST, w_TX_CRC7_PIPO_EN;
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(* mark_debug = "true" *)logic [1:0] w_TX_SOURCE_SELECT;
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(* mark_debug = "true" *)logic w_CMD_TX_IS_CMD55_RST;
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(* mark_debug = "true" *)logic w_CMD_TX_IS_CMD55_EN;
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logic w_TX_PISO40_LOAD, w_TX_PISO40_EN;
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logic w_TX_PISO8_LOAD, w_TX_PISO8_EN;
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logic w_TX_CRC7_PIPO_RST, w_TX_CRC7_PIPO_EN;
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logic [1:0] w_TX_SOURCE_SELECT;
|
||||
logic w_CMD_TX_IS_CMD55_RST;
|
||||
logic w_CMD_TX_IS_CMD55_EN;
|
||||
//logic w_CMD_RX;
|
||||
(* mark_debug = "true" *)logic w_RX_SIPO48_RST, w_RX_SIPO48_EN;
|
||||
logic w_RX_SIPO48_RST, w_RX_SIPO48_EN;
|
||||
(* mark_debug = "true" *)logic [39:8] r_RESPONSE_CONTENT;
|
||||
(* mark_debug = "true" *)logic [45:40] r_RESPONSE_INDEX;
|
||||
(* mark_debug = "true" *)logic w_RX_CRC7_SIPO_RST, w_RX_CRC7_SIPO_EN;
|
||||
(* mark_debug = "true" *)logic [6:0] r_RX_CRC7_Q;
|
||||
(* mark_debug = "true" *)logic w_RCA_REGISTER_RST, w_RCA_REGISTER_EN;
|
||||
(* mark_debug = "true" *)logic w_CMD_TX_DONE;
|
||||
(* mark_debug = "true" *)logic w_DAT_RX_DONE;
|
||||
(* mark_debug = "true" *)logic w_DAT_ERROR_FD_RST_DAT, w_DAT_ERROR_FD_RST_CMD, w_DAT_ERROR_FD_RST, w_DAT_ERROR_FD_EN;
|
||||
logic w_RX_CRC7_SIPO_RST, w_RX_CRC7_SIPO_EN;
|
||||
logic [6:0] r_RX_CRC7_Q;
|
||||
logic w_RCA_REGISTER_RST, w_RCA_REGISTER_EN;
|
||||
logic w_CMD_TX_DONE;
|
||||
logic w_DAT_RX_DONE;
|
||||
logic w_DAT_ERROR_FD_RST_DAT, w_DAT_ERROR_FD_RST_CMD, w_DAT_ERROR_FD_RST, w_DAT_ERROR_FD_EN;
|
||||
(* mark_debug = "true" *)logic r_DAT_ERROR_Q; // CRC16 error or time out
|
||||
(* mark_debug = "true" *)logic w_NOT_DAT_ERROR_Q; // '0'=no error, '1'=tx error on DAT bus
|
||||
(* mark_debug = "true" *)logic w_ERROR_DAT_TIMES_OUT;
|
||||
|
|
@ -205,57 +197,57 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
|
|||
(* mark_debug = "true" *)logic w_LAST_NIBBLE;
|
||||
|
||||
//SD_DAT_FSM Connections
|
||||
(* mark_debug = "true" *)logic w_DAT_TIMER_LOAD, w_DAT_TIMER_EN;
|
||||
(* mark_debug = "true" *)logic w_DAT_COUNTER_RST, w_DAT_COUNTER_EN;
|
||||
(* mark_debug = "true" *)logic w_CRC16_EN, w_CRC16_RST;
|
||||
(* mark_debug = "true" *)logic w_BUSY_RST, w_BUSY_EN;
|
||||
(* mark_debug = "true" *)logic w_NIBO_EN;
|
||||
(* mark_debug = "true" *)logic w_DATA_CRC16_GOOD;
|
||||
(* mark_debug = "true" *)logic w_VALID_BLOCK_D, w_VALID_BLOCK_EN, w_VALID_WIDE_D, w_VALID_WIDE_EN;
|
||||
(* mark_debug = "true" *)logic [22:0] w_DAT_TIMER_IN;
|
||||
(* mark_debug = "true" *)logic [22:0] r_DAT_TIMER_OUT;
|
||||
(* mark_debug = "true" *)logic [10:0] r_DAT_COUNTER_OUT;
|
||||
logic w_DAT_TIMER_LOAD, w_DAT_TIMER_EN;
|
||||
logic w_DAT_COUNTER_RST, w_DAT_COUNTER_EN;
|
||||
logic w_CRC16_EN, w_CRC16_RST;
|
||||
logic w_BUSY_RST, w_BUSY_EN;
|
||||
logic w_NIBO_EN;
|
||||
logic w_DATA_CRC16_GOOD;
|
||||
logic w_VALID_BLOCK_D, w_VALID_BLOCK_EN, w_VALID_WIDE_D, w_VALID_WIDE_EN;
|
||||
logic [22:0] w_DAT_TIMER_IN;
|
||||
logic [22:0] r_DAT_TIMER_OUT;
|
||||
logic [10:0] r_DAT_COUNTER_OUT;
|
||||
(* mark_debug = "true" *)logic [3:0] r_DAT_Q;
|
||||
|
||||
// RCA Register
|
||||
(* mark_debug = "true" *)logic [15:0] w_RCA_D_Q;
|
||||
(* mark_debug = "true" *)logic [15:0] r_RCA_Q2;
|
||||
logic [15:0] w_RCA_D_Q;
|
||||
logic [15:0] r_RCA_Q2;
|
||||
|
||||
// Multiplexer Logics
|
||||
(* mark_debug = "true" *) logic [132:0] w_instruction_control_bits;
|
||||
(* mark_debug = "true" *)logic [132:130] w_R_TYPE ;
|
||||
(* mark_debug = "true" *)logic [129:128] w_USES_DAT ;
|
||||
(* mark_debug = "true" *)logic [127:96] w_NO_REDO_MASK ;
|
||||
(* mark_debug = "true" *)logic [95:64] w_NO_REDO_ANS ;
|
||||
(* mark_debug = "true" *)logic [63:32] w_NO_ERROR_MASK ;
|
||||
(* mark_debug = "true" *)logic [31:0] w_NO_ERROR_ANS ;
|
||||
(* mark_debug = "true" *)logic [45:40] w_command_index ;
|
||||
(* mark_debug = "true" *)logic [39:8] w_command_arguments ;
|
||||
(* mark_debug = "true" *)logic [47:8] w_command_head ;
|
||||
logic [132:0] w_instruction_control_bits;
|
||||
logic [132:130] w_R_TYPE ;
|
||||
logic [129:128] w_USES_DAT ;
|
||||
logic [127:96] w_NO_REDO_MASK ;
|
||||
logic [95:64] w_NO_REDO_ANS ;
|
||||
logic [63:32] w_NO_ERROR_MASK ;
|
||||
logic [31:0] w_NO_ERROR_ANS ;
|
||||
logic [45:40] w_command_index ;
|
||||
logic [39:8] w_command_arguments ;
|
||||
logic [47:8] w_command_head ;
|
||||
(* mark_debug = "true" *)logic [6:0] w_OPCODE_Q ;
|
||||
|
||||
// TOP_LEVEL Connections
|
||||
(* mark_debug = "true" *)logic [40:9] w_BLOCK_ADDR ;
|
||||
logic [40:9] w_BLOCK_ADDR ;
|
||||
(* mark_debug = "true" *)logic [3:0] r_IC_OUT ;
|
||||
(* mark_debug = "true" *)logic [2:0] r_command_index_is_55_history ; // [0] is live index, [1] is currently saved index, [2] is index of previous command
|
||||
(* mark_debug = "true" *)logic r_previous_command_index_was_55_q; // is index of previous command 55, wired to r_command_index_is_55_history[2]
|
||||
(* mark_debug = "true" *)logic r_ACMD_Q; // if the previous command sent to the SD card successfully had index 55, then the SD card thinks the current command is ACMD
|
||||
(* mark_debug = "true" *)logic [4095:0] r_block_data ; // data block from CMD17
|
||||
logic [2:0] r_command_index_is_55_history ; // [0] is live index, [1] is currently saved index, [2] is index of previous command
|
||||
logic r_previous_command_index_was_55_q; // is index of previous command 55, wired to r_command_index_is_55_history[2]
|
||||
logic r_ACMD_Q; // if the previous command sent to the SD card successfully had index 55, then the SD card thinks the current command is ACMD
|
||||
logic [4095:0] r_block_data ; // data block from CMD17
|
||||
|
||||
// TX
|
||||
(* mark_debug = "true" *)logic [45:8] w_command_content; // first 40 bits of command packet
|
||||
(* mark_debug = "true" *)logic w_tx_head_Q; // transmission of first part of command packet
|
||||
(* mark_debug = "true" *)logic w_tx_tail_Q; // transmission of last part of command packet
|
||||
(* mark_debug = "true" *)logic [7:0] r_command_tail; // last 8 bits of command packet
|
||||
(* mark_debug = "true" *)logic [6:0] r_TX_CRC7;
|
||||
logic [45:8] w_command_content; // first 40 bits of command packet
|
||||
logic w_tx_head_Q; // transmission of first part of command packet
|
||||
logic w_tx_tail_Q; // transmission of last part of command packet
|
||||
logic [7:0] r_command_tail; // last 8 bits of command packet
|
||||
logic [6:0] r_TX_CRC7;
|
||||
//logic w_TX_Q:= '0'; // actual transmission when tx is enabled
|
||||
|
||||
// RX
|
||||
(* mark_debug = "true" *)logic [47:0] r_RX_RESPONSE;
|
||||
logic [47:0] r_RX_RESPONSE;
|
||||
|
||||
// Tri state IO Driver BC18MIMS
|
||||
(* mark_debug = "true" *)logic w_SD_CMD_TX_Q; // Write Data
|
||||
(* mark_debug = "true" *) logic w_SD_CMD_RX; // Read Data
|
||||
logic w_SD_CMD_TX_Q; // Write Data
|
||||
logic w_SD_CMD_RX; // Read Data
|
||||
|
||||
|
||||
// CLOCKS
|
||||
|
|
@ -263,19 +255,17 @@ module sd_top #(parameter g_COUNT_WIDTH = 8)
|
|||
//logic r_SD_CLK_ungated := '0'; // Selected clock before it is clock gated
|
||||
|
||||
//logic r_SD_CLK := '0'; // GATED CLOCKS
|
||||
(* mark_debug = "true" *)logic r_TO_SD_CLK; // What is actually sent to the SD card
|
||||
logic r_TO_SD_CLK; // What is actually sent to the SD card
|
||||
|
||||
(* mark_debug = "true" *)logic w_G_CLK_SD_EN;
|
||||
(* mark_debug = "true" *)logic r_CLK_SD, r_G_CLK_SD; // clocks
|
||||
(* mark_debug = "true" *)logic r_G_CLK_SD_n;
|
||||
(* mark_debug = "true" *)logic [15:0] r_CLK_FSM_RST ; // a_rst logic delayed by one 1.2 GHz period
|
||||
(* mark_debug = "true" *)logic w_SD_CLK_SELECTED;
|
||||
logic w_G_CLK_SD_EN;
|
||||
logic r_CLK_SD, r_G_CLK_SD; // clocks
|
||||
logic r_G_CLK_SD_n;
|
||||
logic [15:0] r_CLK_FSM_RST ; // a_rst logic delayed by one 1.2 GHz period
|
||||
logic w_SD_CLK_SELECTED;
|
||||
|
||||
//DAT FSM Connections
|
||||
(* mark_debug = "true" *)logic [15:0] r_DAT3_CRC16, r_DAT2_CRC16, r_DAT1_CRC16;
|
||||
(* mark_debug = "true" *)logic [15:0] r_DAT0_CRC16;
|
||||
|
||||
(* mark_debug = "true" *) logic w_IC_EN_Q;
|
||||
logic [15:0] r_DAT3_CRC16, r_DAT2_CRC16, r_DAT1_CRC16;
|
||||
logic [15:0] r_DAT0_CRC16;
|
||||
|
||||
assign w_BLOCK_ADDR = {8'h00, i_BLOCK_ADDR}; // (40 downto 36 are zero since card is 64 GB)
|
||||
// (35 downto 32 are zero since memeory is only 8GB total)
|
||||
|
|
|
|||
|
|
@ -26,14 +26,14 @@ module sd_top_wrapper #(parameter g_COUNT_WIDTH = 8)
|
|||
wire CLK;
|
||||
wire LIMIT_SD_TIMERS;
|
||||
wire [g_COUNT_WIDTH-1:0] i_COUNT_IN_MAX;
|
||||
(* mark_debug = "true" *) wire [4095:0] ReadData; // full 512 bytes to Bus
|
||||
wire [4095:0] ReadData; // full 512 bytes to Bus
|
||||
wire [32:9] i_BLOCK_ADDR; // see "Addressing" in parts.fods (only 8GB total capacity is used)
|
||||
wire o_SD_CMD; // CMD Command from host
|
||||
wire i_SD_CMD; // CMD Command from host
|
||||
wire o_SD_CMD_OE; // Direction of SD_CMD
|
||||
(* mark_debug = "true" *) wire [2:0] o_ERROR_CODE_Q; // indicates which error occured
|
||||
(* mark_debug = "true" *) wire o_FATAL_ERROR; // indicates that the FATAL ERROR register has updated
|
||||
(* mark_debug = "true" *) wire o_LAST_NIBBLE; // pulse when last nibble is sent
|
||||
wire [2:0] o_ERROR_CODE_Q; // indicates which error occured
|
||||
wire o_FATAL_ERROR; // indicates that the FATAL ERROR register has updated
|
||||
wire o_LAST_NIBBLE; // pulse when last nibble is sent
|
||||
|
||||
assign LIMIT_SD_TIMERS = 1'b0;
|
||||
assign i_COUNT_IN_MAX = -8'd62;
|
||||
|
|
|
|||
|
|
@ -35,9 +35,9 @@ module up_down_counter #(parameter integer WIDTH=32)
|
|||
input logic clk,
|
||||
input logic reset);
|
||||
|
||||
(* mark_debug = "true" *)logic [WIDTH-1:0] NextCount;
|
||||
logic [WIDTH-1:0] NextCount;
|
||||
logic [WIDTH-1:0] count_q;
|
||||
(* mark_debug = "true" *)logic [WIDTH-1:0] CountP1;
|
||||
logic [WIDTH-1:0] CountP1;
|
||||
|
||||
flopenr #(WIDTH) reg1(.clk,
|
||||
.reset,
|
||||
|
|
|
|||
|
|
@ -35,9 +35,9 @@ module uart (
|
|||
input logic [`XLEN-1:0] HWDATA,
|
||||
output logic [`XLEN-1:0] HREADUART,
|
||||
output logic HRESPUART, HREADYUART,
|
||||
input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface
|
||||
output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface
|
||||
output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU
|
||||
(* mark_debug = "true" *) input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface
|
||||
(* mark_debug = "true" *) output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface
|
||||
(* mark_debug = "true" *) output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU
|
||||
|
||||
// UART interface signals
|
||||
logic [2:0] A;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue