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PIPELINE test running
This commit is contained in:
David Harris
parent
c306884e2c
commit
4b57af9cff
9 changed files with 36 additions and 91 deletions
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@ -1,6 +1,6 @@
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#!/usr/bin/python3
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##################################
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# wally-I-PIPELINE.py
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# PIPELINE.py
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#
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# David_Harris@hmc.edu 27 October 2021
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#
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@ -108,7 +108,7 @@ for xlen in xlens:
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storecmd = "sd"
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wordsize = 8
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pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
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fname = pathname + "src/WALLY-PIPELINE.S"
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fname = pathname + "src/PIPELINE.S"
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testnum = 0
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# print custom header part
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@ -126,6 +126,19 @@ for xlen in xlens:
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for line in h:
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f.write(line)
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maxreg = 5
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for i in range(1):
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instr = instrs[randint(0,len(instrs)-1)]
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reg1 = randint(0,maxreg)
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reg2 = randint(0,maxreg)
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reg3 = randint(1,maxreg)
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line = instr + " x" +str(reg3) + ", x" + str(reg1) + ", x" + str(reg2) + "\n"
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f.write(line)
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for i in range(1,maxreg+1):
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line = storecmd + " x" + str(i) + ", " + str(wordsize*(i-1)) + "(x8)\n"
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f.write(line)
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# print directed and random test vectors
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# for a in corners:
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# for b in corners:
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@ -1,3 +1,4 @@
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#endif
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RVTEST_CODE_END
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RVMODEL_HALT
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@ -87,7 +87,7 @@ simulate:
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run -C $(SUITEDIR)
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verify: simulate
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riscv-test-env/verify.sh
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# riscv-test-env/verify.sh # dmh 1 November 2021 removed because these tests don't have expected values
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postverify:
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ifeq ($(wildcard $(TARGETDIR)/$(RISCV_TARGET)/postverify.sh),)
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@ -1,7 +1,7 @@
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///////////////////////////////////////////
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// ../wally-riscv-arch-test/riscv-test-suite/rv32i_m/I/src/WALLY-PIPELINE.S
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// David_Harris@hmc.edu
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// Created 2021-11-01 08:46:04.665699//
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// Created 2021-11-01 11:43:39.219968//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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@ -32,6 +32,13 @@ RVTEST_CODE_BEGIN
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RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
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RVTEST_SIGBASE( x8,signature_x8_1)
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AND x1, x3, x3
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sw x1, 0(x8)
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sw x2, 4(x8)
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sw x3, 8(x8)
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sw x4, 12(x8)
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sw x5, 16(x8)
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#endif
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RVTEST_CODE_END
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RVMODEL_HALT
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@ -29,6 +29,7 @@
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rv64i_sc_tests = \
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add-01 \
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PIPELINE \
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@ -1,82 +0,0 @@
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///////////////////////////////////////////
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// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S
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// David_Harris@hmc.edu
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// Created 2021-11-01 08:46:04.668632//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV64I")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
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RVTEST_SIGBASE( x8,signature_x8_1)
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RVTEST_CODE_END
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RVMODEL_HALT
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RVTEST_DATA_BEGIN
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.align 4
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rvtest_data:
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.word 0xbabecafe
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RVTEST_DATA_END
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RVMODEL_DATA_BEGIN
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signature_x8_0:
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.fill 0*(XLEN/32),4,0xdeadbeef
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signature_x8_1:
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.fill 19*(XLEN/32),4,0xdeadbeef
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signature_x1_0:
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.fill 256*(XLEN/32),4,0xdeadbeef
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signature_x1_1:
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.fill 256*(XLEN/32),4,0xdeadbeef
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signature_x1_2:
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.fill 148*(XLEN/32),4,0xdeadbeef
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#ifdef rvtest_mtrap_routine
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mtrap_sigptr:
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.fill 64*(XLEN/32),4,0xdeadbeef
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#endif
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#ifdef rvtest_gpr_save
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gpr_save:
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.fill 32*(XLEN/32),4,0xdeadbeef
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#endif
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RVMODEL_DATA_END
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// ../wally-riscv-arch-test/riscv-test-suite/rv64i_m/I/src/WALLY-PIPELINE.S
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// David_Harris@hmc.edu
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@ -55,7 +55,7 @@ module fpudivsqrtrecur (
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// Special Cases
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// *** shift to handle denorms in hardware
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assign FDivSqrtResSign = FDivE & (XSgnE ^ YSgnE); // Sign is negative for division if inputs have opposite signs
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assign FDivSqrtResSgn = FDivE & (XSgnE ^ YSgnE); // Sign is negative for division if inputs have opposite signs
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always_comb begin
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if (FSqrtE & XSgnE | FDivE & XZeroE & YZeroE | XNaNE | FDivE & YNaNE) FDivSqrtResM = 0; // ***replace with NAN; // *** which one
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@ -64,7 +64,10 @@ module intdiv #(parameter WIDTH=64)
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logic [WIDTH-1:0] QT, remT;
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logic D_NegOne;
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logic Max_N;
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logic otfzerov;
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logic tcQ;
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logic tcR;
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// Check if negative (two's complement)
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// If so, convert to positive
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@ -182,7 +185,9 @@ module divide4 #(parameter WIDTH=64)
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logic CshiftQ, CshiftQM;
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logic [WIDTH+3:0] rem1, rem2, rem3;
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logic [WIDTH+3:0] SumR, CarryR;
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logic [WIDTH:0] Qt;
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logic [WIDTH:0] Qt;
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logic ulp;
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// Create one's complement values of Divisor (for q*D)
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assign divi1 = {3'h0, op2, 1'b0};
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@ -1071,8 +1071,8 @@ string imperas32f[] = '{
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string wally64i[] = '{
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`WALLYTEST,
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"rv64i_m/I/add-01", "9010"
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// "rv64i_m/I/pipeline-01", "9010"
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"rv64i_m/I/add-01", "9010",
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"rv64i_m/I/PIPELINE", "2010"
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};
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string wally64priv[] = '{
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