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Maybe improvements to fpga synthesis.

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This commit is contained in:
Rose Thompson 2024-08-23 13:00:22 -07:00
parent fc80bf1251
commit 4d56b3ca96
3 changed files with 172 additions and 166 deletions
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2
fpga/generator/Makefile
View file

@ -33,7 +33,7 @@ IP_VCU: $(dst)/sysrst.log \
$(dst)/ahbaxibridge.log
IP_Arty: $(dst)/sysrst.log \
MEM_Arty \
$(dst)/mmcm.log \
$(dst)/xlnx_mmcm.log \
$(dst)/clkconverter.log \
$(dst)/ahbaxibridge.log
#$(dst)/xlnx_axi_crossbar.log \

32
fpga/generator/wally.tcl
View file

@ -5,6 +5,11 @@ set boardName $::env(XILINX_BOARD)
set boardSubName [lindex [split ${boardName} :] 1]
set board $::env(board)
set partNumber xc7a100tcsg324-1
set boardName digilentinc.com:arty-a7-100:part0:1.1
set boardSubName arty-a7-100
set board ArtyA7
set ipName WallyFPGA
create_project $ipName . -force -part $partNumber
@ -23,15 +28,15 @@ if {$board=="ArtyA7"} {
}
# read in ip
read_ip IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci
read_ip IP/ahbaxibridge.srcs/sources_1/ip/ahbaxibridge/ahbaxibridge.xci
read_ip IP/clkconverter.srcs/sources_1/ip/clkconverter/clkconverter.xci
import_ip IP/sysrst.srcs/sources_1/ip/sysrst/sysrst.xci
import_ip IP/ahbaxibridge.srcs/sources_1/ip/ahbaxibridge/ahbaxibridge.xci
import_ip IP/clkconverter.srcs/sources_1/ip/clkconverter/clkconverter.xci
if {$board=="ArtyA7"} {
read_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci
read_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci
import_ip IP/ddr3.srcs/sources_1/ip/ddr3/ddr3.xci
import_ip IP/mmcm.srcs/sources_1/ip/mmcm/mmcm.xci
} else {
read_ip IP/ddr4.srcs/sources_1/ip/ddr4/ddr4.xci
import_ip IP/ddr4.srcs/sources_1/ip/ddr4/ddr4.xci
}
# read in all other rtl
@ -41,13 +46,6 @@ read_verilog [glob -type f ../../addins/ahbsdc/sdc/*.v]
set_property include_dirs {../src/CopiedFiles_do_not_add_to_repo/config ../../config/shared ../../addins/ahbsdc/sdc} [current_fileset]
if {$board=="ArtyA7"} {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
} else {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
}
# define top level
set_property top fpgaTop [current_fileset]
@ -57,6 +55,14 @@ update_compile_order -fileset sources_1
exec mkdir -p reports/
exec rm -rf reports/*
if {$board=="ArtyA7"} {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$board.xdc]
} else {
add_files -fileset constrs_1 -norecurse ../constraints/constraints-$boardSubName.xdc
set_property PROCESSING_ORDER NORMAL [get_files ../constraints/constraints-$boardSubName.xdc]
}
report_compile_order -constraints > reports/compile_order.rpt
# this is elaboration not synthesis.

304
fpga/src/fpgaTopArtyA7.sv
View file

@ -29,183 +29,183 @@
import cvw::*;
module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
(input default_100mhz_clk,
(* mark_debug = "true" *) input resetn,
input south_reset,
(input logic default_100mhz_clk,
input logic resetn,
input logic south_reset,
// GPIO signals
input [3:0] GPI,
output [4:0] GPO,
input logic [3:0] GPI,
output logic [4:0] GPO,
// UART Signals
input UARTSin,
output UARTSout,
input logic UARTSin,
output logic UARTSout,
// SDC Signals connecting to an SPI peripheral
input SDCIn,
output SDCCLK,
output SDCCmd,
output SDCCS,
input SDCCD,
input SDCWP,
input logic SDCIn,
output logic SDCCLK,
output logic SDCCmd,
output logic SDCCS,
input logic SDCCD,
input logic SDCWP,
/*
* Ethernet: 100BASE-T MII
*/
output phy_ref_clk,
input phy_rx_clk,
input [3:0] phy_rxd,
input phy_rx_dv,
input phy_rx_er,
input phy_tx_clk,
output [3:0] phy_txd,
output phy_tx_en,
input phy_col, // nc
input phy_crs, // nc
output phy_reset_n,
output logic phy_ref_clk,
input logic phy_rx_clk,
input logic [3:0] phy_rxd,
input logic phy_rx_dv,
input logic phy_rx_er,
input logic phy_tx_clk,
output logic [3:0] phy_txd,
output logic phy_tx_en,
input logic phy_col, // nc
input logic phy_crs, // nc
output logic phy_reset_n,
inout [15:0] ddr3_dq,
inout [1:0] ddr3_dqs_n,
inout [1:0] ddr3_dqs_p,
output [13:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output [0:0] ddr3_ck_p,
output [0:0] ddr3_ck_n,
output [0:0] ddr3_cke,
output [0:0] ddr3_cs_n,
output [1:0] ddr3_dm,
output [0:0] ddr3_odt
inout logic [15:0] ddr3_dq,
inout logic [1:0] ddr3_dqs_n,
inout logic [1:0] ddr3_dqs_p,
output logic [13:0] ddr3_addr,
output logic [2:0] ddr3_ba,
output logic ddr3_ras_n,
output logic ddr3_cas_n,
output logic ddr3_we_n,
output logic ddr3_reset_n,
output logic [0:0] ddr3_ck_p,
output logic [0:0] ddr3_ck_n,
output logic [0:0] ddr3_cke,
output logic [0:0] ddr3_cs_n,
output logic [1:0] ddr3_dm,
output logic [0:0] ddr3_odt
);
// MMCM Signals
wire CPUCLK;
wire c0_ddr4_ui_clk_sync_rst;
wire bus_struct_reset;
wire peripheral_reset;
wire interconnect_aresetn;
wire peripheral_aresetn;
wire mb_reset;
logic CPUCLK;
logic c0_ddr4_ui_clk_sync_rst;
logic bus_struct_reset;
logic peripheral_reset;
logic interconnect_aresetn;
logic peripheral_aresetn;
logic mb_reset;
// AHB Signals from Wally
wire HCLKOpen;
wire HRESETnOpen;
wire [63:0] HRDATAEXT;
wire HREADYEXT;
wire HRESPEXT;
wire HSELEXT;
wire [55:0] HADDR;
wire [63:0] HWDATA;
wire [64/8-1:0] HWSTRB;
wire HWRITE;
wire [2:0] HSIZE;
wire [2:0] HBURST;
wire [1:0] HTRANS;
wire HREADY;
wire [3:0] HPROT;
wire HMASTLOCK;
logic HCLKOpen;
logic HRESETnOpen;
logic [63:0] HRDATAEXT;
logic HREADYEXT;
logic HRESPEXT;
logic HSELEXT;
logic [55:0] HADDR;
logic [63:0] HWDATA;
logic [64/8-1:0] HWSTRB;
logic HWRITE;
logic [2:0] HSIZE;
logic [2:0] HBURST;
logic [1:0] HTRANS;
logic HREADY;
logic [3:0] HPROT;
logic HMASTLOCK;
// GPIO Signals
wire [31:0] GPIOIN, GPIOOUT, GPIOEN;
logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
// AHB to AXI Bridge Signals
wire [3:0] m_axi_awid;
wire [7:0] m_axi_awlen;
wire [2:0] m_axi_awsize;
wire [1:0] m_axi_awburst;
wire [3:0] m_axi_awcache;
wire [31:0] m_axi_awaddr;
wire [2:0] m_axi_awprot;
wire m_axi_awvalid;
wire m_axi_awready;
wire m_axi_awlock;
wire [63:0] m_axi_wdata;
wire [7:0] m_axi_wstrb;
wire m_axi_wlast;
wire m_axi_wvalid;
wire m_axi_wready;
wire [3:0] m_axi_bid;
wire [1:0] m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_bready;
wire [3:0] m_axi_arid;
wire [7:0] m_axi_arlen;
wire [2:0] m_axi_arsize;
wire [1:0] m_axi_arburst;
wire [2:0] m_axi_arprot;
wire [3:0] m_axi_arcache;
wire m_axi_arvalid;
wire [31:0] m_axi_araddr;
wire m_axi_arlock;
wire m_axi_arready;
wire [3:0] m_axi_rid;
wire [63:0] m_axi_rdata;
wire [1:0] m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_rlast;
wire m_axi_rready;
logic [3:0] m_axi_awid;
logic [7:0] m_axi_awlen;
logic [2:0] m_axi_awsize;
logic [1:0] m_axi_awburst;
logic [3:0] m_axi_awcache;
logic [31:0] m_axi_awaddr;
logic [2:0] m_axi_awprot;
logic m_axi_awvalid;
logic m_axi_awready;
logic m_axi_awlock;
logic [63:0] m_axi_wdata;
logic [7:0] m_axi_wstrb;
logic m_axi_wlast;
logic m_axi_wvalid;
logic m_axi_wready;
logic [3:0] m_axi_bid;
logic [1:0] m_axi_bresp;
logic m_axi_bvalid;
logic m_axi_bready;
logic [3:0] m_axi_arid;
logic [7:0] m_axi_arlen;
logic [2:0] m_axi_arsize;
logic [1:0] m_axi_arburst;
logic [2:0] m_axi_arprot;
logic [3:0] m_axi_arcache;
logic m_axi_arvalid;
logic [31:0] m_axi_araddr;
logic m_axi_arlock;
logic m_axi_arready;
logic [3:0] m_axi_rid;
logic [63:0] m_axi_rdata;
logic [1:0] m_axi_rresp;
logic m_axi_rvalid;
logic m_axi_rlast;
logic m_axi_rready;
// AXI Signals going out of Clock Converter
wire [3:0] BUS_axi_arregion;
wire [3:0] BUS_axi_arqos;
wire [3:0] BUS_axi_awregion;
wire [3:0] BUS_axi_awqos;
wire [3:0] BUS_axi_awid;
wire [7:0] BUS_axi_awlen;
wire [2:0] BUS_axi_awsize;
wire [1:0] BUS_axi_awburst;
wire [3:0] BUS_axi_awcache;
wire [31:0] BUS_axi_awaddr;
wire [2:0] BUS_axi_awprot;
wire BUS_axi_awvalid;
wire BUS_axi_awready;
wire BUS_axi_awlock;
wire [63:0] BUS_axi_wdata;
wire [7:0] BUS_axi_wstrb;
wire BUS_axi_wlast;
wire BUS_axi_wvalid;
wire BUS_axi_wready;
wire [3:0] BUS_axi_bid;
wire [1:0] BUS_axi_bresp;
wire BUS_axi_bvalid;
wire BUS_axi_bready;
wire [3:0] BUS_axi_arid;
wire [7:0] BUS_axi_arlen;
wire [2:0] BUS_axi_arsize;
wire [1:0] BUS_axi_arburst;
wire [2:0] BUS_axi_arprot;
wire [3:0] BUS_axi_arcache;
wire BUS_axi_arvalid;
wire [31:0] BUS_axi_araddr;
wire BUS_axi_arlock;
wire BUS_axi_arready;
wire [3:0] BUS_axi_rid;
wire [63:0] BUS_axi_rdata;
wire [1:0] BUS_axi_rresp;
wire BUS_axi_rvalid;
wire BUS_axi_rlast;
wire BUS_axi_rready;
logic [3:0] BUS_axi_arregion;
logic [3:0] BUS_axi_arqos;
logic [3:0] BUS_axi_awregion;
logic [3:0] BUS_axi_awqos;
logic [3:0] BUS_axi_awid;
logic [7:0] BUS_axi_awlen;
logic [2:0] BUS_axi_awsize;
logic [1:0] BUS_axi_awburst;
logic [3:0] BUS_axi_awcache;
logic [31:0] BUS_axi_awaddr;
logic [2:0] BUS_axi_awprot;
logic BUS_axi_awvalid;
logic BUS_axi_awready;
logic BUS_axi_awlock;
logic [63:0] BUS_axi_wdata;
logic [7:0] BUS_axi_wstrb;
logic BUS_axi_wlast;
logic BUS_axi_wvalid;
logic BUS_axi_wready;
logic [3:0] BUS_axi_bid;
logic [1:0] BUS_axi_bresp;
logic BUS_axi_bvalid;
logic BUS_axi_bready;
logic [3:0] BUS_axi_arid;
logic [7:0] BUS_axi_arlen;
logic [2:0] BUS_axi_arsize;
logic [1:0] BUS_axi_arburst;
logic [2:0] BUS_axi_arprot;
logic [3:0] BUS_axi_arcache;
logic BUS_axi_arvalid;
logic [31:0] BUS_axi_araddr;
logic BUS_axi_arlock;
logic BUS_axi_arready;
logic [3:0] BUS_axi_rid;
logic [63:0] BUS_axi_rdata;
logic [1:0] BUS_axi_rresp;
logic BUS_axi_rvalid;
logic BUS_axi_rlast;
logic BUS_axi_rready;
wire BUSCLK;
wire sdio_reset_open;
logic BUSCLK;
logic sdio_reset_open;
wire c0_init_calib_complete;
wire dbg_clk;
wire [511 : 0] dbg_bus;
wire ui_clk_sync_rst;
logic c0_init_calib_complete;
logic dbg_clk;
logic [511 : 0] dbg_bus;
logic ui_clk_sync_rst;
wire CLK208;
wire clk167;
wire clk200;
logic CLK208;
logic clk167;
logic clk200;
wire app_sr_active;
wire app_ref_ack;
wire app_zq_ack;
wire mmcm_locked;
wire [11:0] device_temp;
wire mmcm1_locked;
logic app_sr_active;
logic app_ref_ack;
logic app_zq_ack;
logic mmcm_locked;
logic [11:0] device_temp;
logic mmcm1_locked;
(* mark_debug = "true" *) logic RVVIStall;