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Added spi debugger to build script.

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Rose Thompson 2024-09-05 12:04:14 -07:00
parent 261e503061
commit 510e3a268c
1 changed files with 1 additions and 0 deletions
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fpga/generator/wally.tcl
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@ -98,6 +98,7 @@ write_verilog -force -mode funcsim sim/syn-funcsim.v
if {$board=="ArtyA7"} { if {$board=="ArtyA7"} {
#source ../constraints/small-debug.xdc #source ../constraints/small-debug.xdc
#source ../constraints/small-debug-rvvi.xdc #source ../constraints/small-debug-rvvi.xdc
#source ../constraints/small-debug-spi.xdc
} else { } else {
#source ../constraints/vcu-small-debug.xdc #source ../constraints/vcu-small-debug.xdc
#source ../constraints/small-debug.xdc #source ../constraints/small-debug.xdc