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Merge pull request #424 from ross144/main

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Fixed issue #412 The root cause was DTLB miss leads to page fault exception with concurrent I$ miss.  The HPTW hits all entries in the D$ and quickly faults.  However the I$ is still waiting on the main memory. The trap then interrupts the atomimicity of the bus fetch and breaks the next several instructions.
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David Harris 2023-10-10 07:09:15 -07:00 • committed by GitHub
commit 519d7ce664
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src/privileged/trap.sv
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@ -87,7 +87,7 @@ module trap import cvw::*; #(parameter cvw_t P) (
BreakpointFaultM | EcallFaultM |
LoadAccessFaultM | StoreAmoAccessFaultM;
// coverage on
assign TrapM = ExceptionM | InterruptM;
assign TrapM = (ExceptionM & ~CommittedF) | InterruptM; // *** RT: review this additional ~CommittedF with DH and update priv chapter.
assign RetM = mretM | sretM;
///////////////////////////////////////////