Fix lots of spelling errors

fpga/rvvidaemon/rvvidaemon.c

@@ -169,7 +169,7 @@ int main(int argc, char **argv){
   if (ioctl(sockfd, SIOCGIFINDEX, &ifopts) < 0)
     perror("SIOCGIFINDEX");
   
-  /* Allow the socket to be reused - incase connection is closed prematurely */
+  /* Allow the socket to be reused - in case connection is closed prematurely */
   if (setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &sockopt, sizeof sockopt) == -1) {
     perror("setsockopt");
     close(sockfd);

fpga/src/fpgaTopArtyA7.sv

@@ -223,7 +223,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
   // the ddr3 mig7 requires 2 input clocks 
   // 1. sys clock which is 167 MHz = ddr3 clock / 4
   // 2. a second clock which is 200 MHz
-  // Wally requires a slower clock.  At this point I don't know what speed the atrix 7 will run so I'm initially targetting 25Mhz.
+  // Wally requires a slower clock.  At this point I don't know what speed the atrix 7 will run so I'm initially targeting 25Mhz.
   // the mig will output a clock at 1/4 the sys clock or 41Mhz which might work with wally so we may be able to simplify the logic a lot.
   mmcm mmcm(.clk_out1(clk167),
                      .clk_out2(clk200),
@@ -486,7 +486,7 @@ module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
     localparam [31:0] RVVI_INIT_TIME_OUT = 32'd100000000;
     localparam [31:0] RVVI_PACKET_DELAY = 32'd400;
     
-    // pipeline controlls
+    // pipeline controls
     logic                                             StallE, StallM, StallW, FlushE, FlushM, FlushW;
     // required
     logic [P.XLEN-1:0]                                PCM;

fpga/zsbl/gpt.c

@@ -51,7 +51,7 @@ int gpt_load_partitions() {
   BYTE lba2_buf[512];
   ret = disk_read(lba2_buf, (LBA_t)lba1->partition_entries_lba, 1);
 
-  // Load parition entries for the relevant boot partitions.
+  // Load partition entries for the relevant boot partitions.
   partition_entries_t *fdt = (partition_entries_t *)(lba2_buf);
   partition_entries_t *opensbi = (partition_entries_t *)(lba2_buf + 128);
   partition_entries_t *kernel = (partition_entries_t *)(lba2_buf + 256);

fpga/zsbl/sd.c

@@ -93,7 +93,7 @@ uint64_t sd_cmd(uint8_t cmd, uint32_t arg, uint8_t crc) {
   }
 
   // Make interrupt pending after response fifo receives the correct
-  // response length.  Probably unecessary so let's wait and see what
+  // response length.  Probably unnecessary so let's wait and see what
   // happens.
   // write_reg(SPI_RXMARK, response_len);