github-mirrors/cvw
1
0
Fork 0
mirror of https://github.com/openhwgroup/cvw.git synced 2025-06-27 17:01:20 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Fix lots of spelling errors

Browse source
This commit is contained in:
Jordan Carlin 2025-05-08 00:15:48 -07:00
parent f90a60348a
commit 5271234591
No known key found for this signature in database
180 changed files with 443 additions and 443 deletions
Download patch file Download diff file Expand all files Collapse all files

4
sim/questa/coverage-exclusions-rv64gc.do
View file

@ -197,7 +197,7 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$lin
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-tim"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-cachable"]
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-cacheable"]
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
set line [GetLineNum ${SRC}/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"]
@ -440,7 +440,7 @@ coverage exclude -scope /dut/core/hzu -linerange [GetLineNum ${SRC}/hazard/hazar
# Privileged
####################
# Instruction Misaligned never asserted because compresssed instructions are accepted
# Instruction Misaligned never asserted because compressed instructions are accepted
coverage exclude -scope /dut/core/priv/priv/trap -linerange [GetLineNum ${SRC}/privileged/trap.sv "assign ExceptionM"] -item e 1 -fecexprrow 2
# Attempting to access fflags, frm, fcsr with mstatus.FS = 0 traps, so checking for (STATUS_FS != 2'b00)

2
sim/questa/wally.do
View file

@ -75,7 +75,7 @@ set SVLib ""
set GUI 0
set accFlag ""
# Need to be able to pass arguments to vopt. Unforunately argv does not work because
# Need to be able to pass arguments to vopt. Unfortunately argv does not work because
# it takes on different values if vsim and the do file are called from the command line or
# if the do file is called from questa sim directly. This chunk of code uses the $n variables
# and compacts them into a single list for passing to vopt. Shift is used to move the arguments

2
sim/verilator/Makefile
View file

@ -22,7 +22,7 @@ TESTBENCH?=testbench
# constants
# assume WALLY variable is correctly configured in the shell environment
# INCLUDE_PATH are pathes that Verilator should search for files it needs
# INCLUDE_PATH are paths that Verilator should search for files it needs
INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
# SOURCES are source files
SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv