mirror of
https://github.com/openhwgroup/cvw.git
synced 2025-06-27 17:01:20 -04:00
Fix lots of spelling errors
This commit is contained in:
Jordan Carlin
parent
f90a60348a
commit
5271234591
180 changed files with 443 additions and 443 deletions
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@ -12,7 +12,7 @@ MEMFILES := $(addsuffix .memfile, $(ELFS))
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all: $(OBJDUMPS) $(MEMFILES)
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# Create dissassembly
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# Create disassembly
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%.elf.objdump: %.elf
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riscv64-unknown-elf-objdump -S -D $< > $@
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extractFunctionRadix.sh $@
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@ -24,7 +24,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -24,7 +24,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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@ -140,6 +140,6 @@ jump23:
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addi x31, x31, -1
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bne x31, x0, jump1
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finsihed:
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finished:
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j done
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@ -24,7 +24,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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@ -57,7 +57,7 @@ def write_repro_instrs():
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if i == 12:
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wl('sd zero, 0(t0)') # D$ write to set PCM = PCF + 8 for proper alignment (stallD will happen).
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elif i == 13:
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# the store in question happens here, at adresses 0x34, 0x74
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# the store in question happens here, at addresses 0x34, 0x74
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wl('sd zero, 0(t0)') # it should hit this time
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else:
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# can't be a NOP or anything else that is encoded as compressed.
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@ -73,7 +73,7 @@ if __name__ == "__main__":
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wl('#include "WALLY-init-lib.h"')
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wl('main:')
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# excercise all 4 D$ ways. If they're not all full, it uses the first empty.
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# exercise all 4 D$ ways. If they're not all full, it uses the first empty.
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# So we are sure all 4 ways are exercised.
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for i in range(dcache_num_ways):
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wl(comment=f"start way test #{i+1}")
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@ -81,6 +81,6 @@ if __name__ == "__main__":
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wl('.align 6') # start at i$ set boundary. 6 lsb bits are zero.
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wl(comment=f"i$ boundary, way test #{i+1}")
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write_repro_instrs()
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mem_addr += dcache_way_size_in_bytes # so that we excercise a new D$ way.
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mem_addr += dcache_way_size_in_bytes # so that we exercise a new D$ way.
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wl("j done")
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@ -24,7 +24,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -183,7 +183,7 @@ pagetable:
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.8byte 0x0000000020014C0F # for VA starting at 80200000 (misaligned megapage)
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.8byte 0x0000000020005001 # for VA starting at 80400000 (bad PBMT pages)
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.8byte 0x4000000020004C01 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
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.8byte 0x0000000020005401 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz)
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.8byte 0x0000000020005401 # for VA starting at 80800000 (testing rwx permissions with cbom/cboz)
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.8byte 0x0000000020005801 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000)
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.8byte 0x0000000020004C01
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.8byte 0x0000000020004C01
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@ -24,7 +24,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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@ -120,9 +120,9 @@ main:
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fcvt.s.l ft0, t0
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fcvt.s.lu ft0, t0
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// Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc
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// Tests verifying that half and quad floating point conversion instructions are not supported by rv64gc
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# fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124
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// idea: enable the Q extension for this to work properly? A: Q and halfs not supported in rv64gc
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// idea: enable the Q extension for this to work properly? A: Q and halves not supported in rv64gc
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# fcvt.h.w ft3, a0
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# fcvt.w.h a0, ft0
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# fcvt.q.w ft3, a0
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@ -25,7 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -25,7 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -24,7 +24,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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@ -97,7 +97,7 @@ main:
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csrw menvcfg, x1
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csrw senvcfg, x1
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li a0, 0
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ecall # swtich to user mode
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ecall # switch to user mode
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cbo.inval (x2)
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cbo.clean (x3)
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cbo.flush (x1)
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@ -24,7 +24,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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@ -27,7 +27,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -24,7 +24,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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@ -25,7 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -24,7 +24,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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@ -28,7 +28,7 @@
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -27,7 +27,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -43,7 +43,7 @@ main:
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li t5, 0 # j = 0, run nASID only once
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li t3, 32 //Max amount of Loops = 32
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li t4, 0x1000 //offset between addressses.
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li t4, 0x1000 //offset between addresses.
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li t1, 0x00008067 //load in jalr x0 x1 0 instruction to be stored
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setup:
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@ -25,7 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -25,7 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -24,7 +24,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -57,7 +57,7 @@ main:
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add t0, t0, t2 # go to the next page
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lw t1, 1(t0) # load a misaligned aligned uncached address should fault
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add t0, t0, t2 # go to the next page
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sw t1, 1(t0) # store to another misaligned uncached address should falt.
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sw t1, 1(t0) # store to another misaligned uncached address should fault.
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fence.I
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@ -26,7 +26,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -25,7 +25,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -24,7 +24,7 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// load code to initialize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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@ -365,7 +365,7 @@ SpecialPage:
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.8byte 0x0000000020014CCF # for VA starting at 80200000 (misaligned megapage)
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.8byte 0x0000000020005001 # for VA starting at 80400000 (bad PBMT pages page table at 0x80014000)
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.8byte 0x4000000020004C01 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
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.8byte 0x0000000020005401 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz . page table at 0x80015000)
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.8byte 0x0000000020005401 # for VA starting at 80800000 (testing rwx permissions with cbom/cboz . page table at 0x80015000)
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.8byte 0x0000000020004C01 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000. page table at 0x80013000)
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.8byte 0x0F00000020004CCF # for VA starting at 80C00000 (bad reserved field in bits 60:54)
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.8byte 0x000000002000000F # for VA starting at 80E00000 (megapage not dirty or accessed)
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@ -25,7 +25,7 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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// Cover IMMU vm64check block by jumping to illegal virtual addresses
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// Need a nonstandard trap handler to deal with returns from theses jumps
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// Need a nonstandard trap handler to deal with returns from these jumps
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// assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]);
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// assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
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// assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
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@ -42,7 +42,7 @@ The choices for `<test>` are as follows:
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cvtint - test integer conversion unit (fcvtint)
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cvtfp - test floating-point conversion unit (fcvtfp)
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cmp - test comparison unit's LT, LE, EQ opperations (fcmp)
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cmp - test comparison unit's LT, LE, EQ operations (fcmp)
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add - test addition
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fma - test fma
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mul - test mult with fma
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@ -1,4 +1,4 @@
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This folder holds the archtest and testfloat vectors necessary fo evaluating performance
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This folder holds the archtest and testfloat vectors necessary for evaluating performance
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of standalone intdiv vs combined IFdivsqrt
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to generate vectors, uncomment line 8 in create_all_vectors.sh
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@ -15,7 +15,7 @@ wally-sim-files: $(MEMFILES) $(ADDRFILES)
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# in the recipe.
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# because elf2hex requires a bit width we use findstring to figure out if the compiled directory
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# is XLEN=64 or 32. This is hacky and will likely break in the future.
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# the .addr is a separate target so make can split into more jobs and more parallism.
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# the .addr is a separate target so make can split into more jobs and more parallelism.
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%.elf.memfile: BITWIDTH ?= $(if $(findstring rv64,$*),64,32)
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%.elf.memfile: %.elf
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riscv64-unknown-elf-elf2hex --bit-width $(BITWIDTH) --input $< --output $@
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@ -38,7 +38,7 @@ class spike(pluginTemplate):
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# Path to the directory where this python file is located. Collect it from the config.ini
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self.pluginpath=os.path.abspath(config['pluginpath'])
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# Collect the paths to the riscv-config absed ISA and platform yaml files. One can choose
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# Collect the paths to the riscv-config based ISA and platform yaml files. One can choose
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# to hardcode these here itself instead of picking it from the config.ini file.
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self.isa_spec = os.path.abspath(config['ispec'])
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self.platform_spec = os.path.abspath(config['pspec'])
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@ -154,7 +154,7 @@ class spike(pluginTemplate):
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# function earlier
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make.makeCommand = 'make -j' + self.num_jobs
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# we will iterate over each entry in the testList. Each entry node will be refered to by the
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# we will iterate over each entry in the testList. Each entry node will be referred to by the
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# variable testname.
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for testname in testList:
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@ -271,7 +271,7 @@
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#define MPP_SMODE (1<<MPP_LSB)
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//define sizes
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#define actual_tramp_sz ((XLEN + 3* NUM_SPECD_INTCAUSES + 5) * 4) // 5 is added ops before common entry pt
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#define tramp_sz ((actual_tramp_sz+4) & -8) // round up to keep aligment for sv area alloc
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#define tramp_sz ((actual_tramp_sz+4) & -8) // round up to keep alignment for sv area alloc
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#define ptr_sv_sz (16*8)
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#define reg_sv_sz ( 8*REGWIDTH)
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#define sv_area_sz (tramp_sz + ptr_sv_sz + reg_sv_sz) // force dblword alignment
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@ -354,7 +354,7 @@
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.set absimm, ((immx^(-BIT(immx,XLEN-1)))&MASK) /* cvt to posnum to simplify code */ ;\
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.set cry, (BIT(immx, IMMSGN)) ;\
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.set imm12, (SEXT_IMM(immx)) ;\
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/***************** used in code that gnerates bitmasks */ ;\
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/***************** used in code that generates bitmasks */ ;\
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.set even, (1-BIT(imm, 0)) /* imm has at least 1 trailing zero */ ;\
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.set cryh, (BIT(immx, IMMSGN+32)) ;\
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/******** loop finding rising/falling edge fm LSB-MSB given even operand ****/ ;\
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@ -409,7 +409,7 @@
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.elseif ((immx==imme)&&((absimmsh>>IMMSGN)==0))/* fits 12b after shift? */ ;\
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li reg, imm12sh /* <= 12bit, will be simple li */ ;\
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slli reg, reg, edge1 /* add trailing zeros */ ;\
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.elseif ((immx==imme)&&(((absimmsh>>WDSGN)+crysh)==0)) /* fits 32 <<shft? */ ;\
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.elseif ((immx==imme)&&(((absimmsh>>WDSGN)+crysh)==0)) /* fits 32 <<shift?*/ ;\
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lui reg, ((immxsh>>IMMSZ)+crysh)&LIMMMSK /* <=32b, use lui/addi */ ;\
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.if ((imm12sh&IMMMSK)!=0) /* but skip this if low bits ==0 */ ;\
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addi reg, reg, imm12sh ;\
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@ -1082,9 +1082,9 @@ rvtest_\__MODE__\()prolog_done:
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/**********************************************************************/
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/**** This is the entry point for all x-modetraps, vectored or not.****/
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/**** xtvec should either point here, or trampoline code does and ****/
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/**** trampoline code was copied to whereever xtvec pointed to. ****/
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/**** trampoline code was copied to wherever xtvec pointed to. ****/
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/**** At entry, xscratch will contain a pointer to a scratch area. ****/
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/**** This is an array of branches at 4B intevals that spreads out ****/
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/**** This is an array of branches at 4B intervals that spreads out ****/
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/**** to an array of 12B xhandler stubs for specd int causes, and ****/
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/**** to a return for anything above that (which causes a mismatch)****/
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/**********************************************************************/
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@ -1171,7 +1171,7 @@ spcl_\__MODE__\()2mmode_test:
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slli T3, T5, 1 // remove MSB, cause<<1
|
||||
addi T3, T3, -(IRQ_M_TIMER)<<1 // is cause (w/o MSB) an extint or larger? ( (cause<<1) > (8<<1) )?
|
||||
bgez T3, \__MODE__\()trap_sig_sv // yes, keep std length
|
||||
li T2, 3*REGWIDTH // no, its a timer or swint, overrride preinc to 3*regsz
|
||||
li T2, 3*REGWIDTH // no, its a timer or swint, override preinc to 3*regsz
|
||||
j \__MODE__\()trap_sig_sv
|
||||
|
||||
/**********************************************************************/
|
||||
|
|
@ -1635,7 +1635,7 @@ excpt_\__MODE__\()hndlr_tbl: // handler code should only touch T2..T6
|
|||
|
||||
\__MODE__\()clr_Mext_int: // inT11 default to just return after saving IntID in T3
|
||||
RVMODEL_CLR_MEXT_INT
|
||||
SREG T3, 3*REGWIDTH(T1) // save 4rd sig value, (intID)
|
||||
SREG T3, 3*REGWIDTH(T1) // save 4th sig value, (intID)
|
||||
j resto_\__MODE__\()rtn
|
||||
|
||||
//------------- SMode----------------
|
||||
|
|
@ -1649,7 +1649,7 @@ excpt_\__MODE__\()hndlr_tbl: // handler code should only touch T2..T6
|
|||
|
||||
\__MODE__\()clr_Sext_int: // int 9 default to just return after saving IntID in T3
|
||||
RVMODEL_CLR_SEXT_INT
|
||||
SREG T3, 3*REGWIDTH(T1) // save 4rd sig value, (intID)
|
||||
SREG T3, 3*REGWIDTH(T1) // save 4th sig value, (intID)
|
||||
j resto_\__MODE__\()rtn
|
||||
|
||||
//------------- VSmode----------------
|
||||
|
|
@ -1663,7 +1663,7 @@ excpt_\__MODE__\()hndlr_tbl: // handler code should only touch T2..T6
|
|||
|
||||
\__MODE__\()clr_Vext_int: // int 8 default to just return after saving IntID in T3
|
||||
RVMODEL_CLR_VEXT_INT
|
||||
SREG T3, 3*REGWIDTH(T1) // save 4rd sig value, (intID)
|
||||
SREG T3, 3*REGWIDTH(T1) // save 4th sig value, (intID)
|
||||
j resto_\__MODE__\()rtn
|
||||
|
||||
.ifc \__MODE__ , M
|
||||
|
|
@ -1791,7 +1791,7 @@ rvtest_\__MODE__\()end:
|
|||
/*******************************************************************************/
|
||||
/**** This macro defines per/mode save areas for mmode for each mode ****/
|
||||
/**** note that it is the code area, not the data area, and ****/
|
||||
/**** must be mulitple of 8B, so multiple instantiations stay aligned ****/
|
||||
/**** must be multiple of 8B, so multiple instantiations stay aligned ****/
|
||||
/**** This is preceded by the current signature pointer, (@Mtrpreg_sv -64? ****/
|
||||
/*******************************************************************************/
|
||||
.macro RVTEST_TRAP_SAVEAREA __MODE__
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
Arguments:
|
||||
_PAR: Register containing Physical Address
|
||||
_PR: Register containing Permissions for Leaf PTE.
|
||||
(Note: No-leaf PTE (if-any) has only valid permssion (pte.v) set)
|
||||
(Note: No-leaf PTE (if-any) has only valid permission (pte.v) set)
|
||||
_TR0, _TR1, _TR2: Temporary registers used and modified by function
|
||||
VA: Virtual address
|
||||
level: Level at which PTE would be setup
|
||||
|
|
|
|||
|
|
@ -270,9 +270,9 @@
|
|||
|
||||
00000022 #clear 1 frame from rx fifo
|
||||
|
||||
00000000 # read recieve ip
|
||||
00000000 # read receive ip
|
||||
|
||||
00000002 #read recieve ip
|
||||
00000002 #read receive ip
|
||||
|
||||
00000000 #read mip
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
0007ec03 # value to indicate successful vectoring on m soft interrupt
|
||||
80000003 # mcause value from m time interrupt
|
||||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire.
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 # Note here that we attempt to cause an interrupt after zeroing status.mie, but it shouldn't fire.
|
||||
0000000b # mcause for ecall from terminating tests in M mode
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
0007ec01 # value to indicate successful vectoring on s soft interrupt
|
||||
80000001 # scause value from s soft interrupt
|
||||
00000000 # stval for ssoft interrupt (0x0)
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire.
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0 # Note here that we attempt to cause an interrupt after zeroing status.mie, but it shouldn't fire.
|
||||
00000009 # mcause for ecall from terminating tests in S mode
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
|
|
|
|||
|
|
@ -8,13 +8,13 @@ FFFFFFFF # stimecmp readback
|
|||
FFFFFFFF # mtval of faulting instruction (0x11111111)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000003 # mcause from Breakpoint
|
||||
80000168 # mtval of breakpoint instruction adress
|
||||
80000168 # mtval of breakpoint instruction address
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000004 # mcause from load address misaligned
|
||||
80000171 # mtval of misaligned address
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000005 # mcause from load access
|
||||
00000000 # mtval of accessed adress (0x0)
|
||||
00000000 # mtval of accessed address (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000006 # mcause from store misaligned
|
||||
80000189 # mtval of address with misaligned store instr
|
||||
|
|
@ -64,13 +64,13 @@ FFFFFFFF # mtval of faulting instruction (0x11111111)
|
|||
FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000003 # mcause from Breakpoint
|
||||
80000168 # mtval of breakpoint instruction adress
|
||||
80000168 # mtval of breakpoint instruction address
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000004 # mcause from load address misaligned
|
||||
80000171 # mtval of misaligned address
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000005 # mcause from load access
|
||||
00000000 # mtval of accessed adress (0x0)
|
||||
00000000 # mtval of accessed address (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000006 # mcause from store misaligned
|
||||
80000189 # mtval of address with misaligned store instr
|
||||
|
|
|
|||
|
|
@ -9,13 +9,13 @@
|
|||
FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000003 # scause from Breakpoint
|
||||
80000168 # stval of breakpoint instruction adress
|
||||
80000168 # stval of breakpoint instruction address
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000004 # scause from load address misaligned
|
||||
80000171 # stval of misaligned address
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000005 # scause from load access
|
||||
00000000 # stval of accessed adress (0x0)
|
||||
00000000 # stval of accessed address (0x0)
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000006 # scause from store misaligned
|
||||
80000189 # stval of address with misaligned store instr
|
||||
|
|
@ -60,13 +60,13 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
|||
FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000003 # scause from Breakpoint
|
||||
80000168 # stval of breakpoint instruction adress
|
||||
80000168 # stval of breakpoint instruction address
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000004 # scause from load address misaligned
|
||||
80000171 # stval of misaligned address
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000005 # scause from load access
|
||||
00000000 # stval of accessed adress (0x0)
|
||||
00000000 # stval of accessed address (0x0)
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000006 # scause from store misaligned
|
||||
80000189 # stval of address with misaligned store instr
|
||||
|
|
|
|||
|
|
@ -9,13 +9,13 @@
|
|||
FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000003 # scause from Breakpoint
|
||||
80000168 # stval of breakpoint instruction adress
|
||||
80000168 # stval of breakpoint instruction address
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000004 # scause from load address misaligned
|
||||
80000171 # stval of misaligned address
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000005 # scause from load access
|
||||
00000000 # stval of accessed adress (0x0)
|
||||
00000000 # stval of accessed address (0x0)
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000006 # scause from store misaligned
|
||||
80000189 # stval of address with misaligned store instr
|
||||
|
|
@ -57,13 +57,13 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
|||
FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000003 # scause from Breakpoint
|
||||
80000168 # stval of breakpoint instruction adress
|
||||
80000168 # stval of breakpoint instruction address
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000004 # scause from load address misaligned
|
||||
80000171 # stval of misaligned address
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000005 # scause from load access
|
||||
00000000 # stval of accessed adress (0x0)
|
||||
00000000 # stval of accessed address (0x0)
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000006 # scause from store misaligned
|
||||
80000189 # stval of address with misaligned store instr
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ RVTEST_CODE_BEGIN
|
|||
|
||||
.endm
|
||||
|
||||
// Code to trigger traps goes here so we have consistent mtvals for instruction adresses
|
||||
// Code to trigger traps goes here so we have consistent mtvals for instruction addresses
|
||||
// Even if more tests are added.
|
||||
.macro CAUSE_TRAP_TRIGGERS
|
||||
j end_trap_triggers
|
||||
|
|
@ -81,10 +81,10 @@ cause_instr_addr_misaligned:
|
|||
ret
|
||||
|
||||
cause_instr_access:
|
||||
sw ra, -4(sp) // push the return adress ontot the stack
|
||||
sw ra, -4(sp) // push the return address ontot the stack
|
||||
addi sp, sp, -4
|
||||
jalr zero // cause instruction access trap (address zero is an address with no memory)
|
||||
lw ra, 0(sp) // pop return adress back from the stack
|
||||
lw ra, 0(sp) // pop return address back from the stack
|
||||
addi sp, sp, 4
|
||||
ret
|
||||
|
||||
|
|
@ -270,7 +270,7 @@ end_trap_triggers:
|
|||
.if (\MODE\() == m)
|
||||
csrrw tp, \MODE\()tvec, ra // tp reserved for "default" trap handler address that needs to be restored before halting this test.
|
||||
.else
|
||||
csrw \MODE\()tvec, ra // we only neet save the machine trap handler and this if statement ensures it isn't overwritten
|
||||
csrw \MODE\()tvec, ra // we only need save the machine trap handler and this if statement ensures it isn't overwritten
|
||||
.endif
|
||||
|
||||
li a0, 0
|
||||
|
|
@ -307,8 +307,8 @@ end_trap_triggers:
|
|||
// 0x0 : defaults to next instruction on the same page the trap was called on.
|
||||
//
|
||||
// a2 (x12):
|
||||
// Pagetype of the current address VPN before changing privilge mode
|
||||
// Used so that we can know how many bits of the adress are the offset.
|
||||
// Pagetype of the current address VPN before changing privilege mode
|
||||
// Used so that we can know how many bits of the address are the offset.
|
||||
// Ignored if a1 == 0x0
|
||||
// 0: Kilopage
|
||||
// 1: Megapage
|
||||
|
|
@ -318,7 +318,7 @@ end_trap_triggers:
|
|||
|
||||
.align 6
|
||||
trap_handler_\MODE\():
|
||||
j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
|
||||
j trap_unvectored_\MODE\() // for the unvectored implementation: jump past this table of addresses into the actual handler
|
||||
// ASSUMES that a cause value of 0 for an interrupt is unimplemented
|
||||
// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
|
||||
// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
|
||||
|
|
@ -336,10 +336,10 @@ trap_handler_\MODE\():
|
|||
// 12 through >=16 are reserved or designated for platform use
|
||||
|
||||
trap_unvectored_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
// NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests
|
||||
|
||||
trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there
|
||||
trap_stack_saved_\MODE\(): // jump here after handling vectored interrupt since we already switch sp and scratch there
|
||||
// save registers on stack before using
|
||||
sw ra, -4(sp)
|
||||
sw t0, -8(sp)
|
||||
|
|
@ -505,37 +505,37 @@ breakpt_\MODE\():
|
|||
// note: does not mess up any registers, saves and restores them to the stack instead.
|
||||
|
||||
s_soft_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
sw t0, -4(sp) // put t0 on the scratch stack before messing with it
|
||||
li t0, 0x7EC01 // write 0x7ec01 (for "VEC"tored and 01 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
m_soft_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
sw t0, -4(sp) // put t0 on the scratch stack before messing with it
|
||||
li t0, 0x7EC03 // write 0x7ec03 (for "VEC"tored and 03 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
s_time_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
sw t0, -4(sp) // put t0 on the scratch stack before messing with it
|
||||
li t0, 0x7EC05 // write 0x7ec05 (for "VEC"tored and 05 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
m_time_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
sw t0, -4(sp) // put t0 on the scratch stack before messing with it
|
||||
li t0, 0x7EC07 // write 0x7ec07 (for "VEC"tored and 07 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
s_ext_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
sw t0, -4(sp) // put t0 on the scratch stack before messing with it
|
||||
li t0, 0x7EC09 // write 0x7ec09 (for "VEC"tored and 08 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
m_ext_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
sw t0, -4(sp) // put t0 on the scratch stack before messing with it
|
||||
li t0, 0x7EC0B // write 0x7ec0B (for "VEC"tored and 0B for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
|
@ -668,11 +668,11 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
|
|||
// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of t2 modified by exectuion code (usually 0x111)
|
||||
// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of t2 modified by execution code (usually 0x111)
|
||||
// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_baremetal : satp.MODE = bare metal : None : None
|
||||
// goto_sv32 : satp.MODE = sv32 : None : None
|
||||
// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_m_mode : go to machine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR
|
||||
|
|
@ -823,7 +823,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
|
|||
// 0x2, then
|
||||
// 0x11 *** consider changing to something more meaningful
|
||||
// Fault outputs:
|
||||
// 0xBAD *** consider changing this one as well. in general, do we need the branching if it hould cause an illegal instruction fault?
|
||||
// 0xBAD *** consider changing this one as well. in general, do we need the branching if it should cause an illegal instruction fault?
|
||||
csrr t4, \CSR
|
||||
csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR
|
||||
csrr t5, \CSR
|
||||
|
|
@ -840,7 +840,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
|
|||
|
||||
.macro EXECUTE_AT_ADDRESS ADDR
|
||||
// Execute the code already written to ADDR, returning the value in t2.
|
||||
// *** Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR
|
||||
// *** Note: this test itself doesn't write the code to ADDR because it might be called at a point where we dont have write access to ADDR
|
||||
// Assumes the code modifies t2, usually to become 0x111.
|
||||
// Sample code: 0x11100393 (li t2, 0x111), 0x00008067 (ret)
|
||||
// Success outputs:
|
||||
|
|
@ -939,13 +939,13 @@ test_loop:
|
|||
// read32_test : Read 32 bits from address : 0xd, 0xbad : readvalue in hex
|
||||
// read16_test : Read 16 bits from address : 0xd, 0xbad : readvalue in hex
|
||||
// read08_test : Read 8 bits from address : 0xd, 0xbad : readvalue in hex
|
||||
// executable_test : test executable on virtual page : 0xc, 0xbad : value of t2 modified by exectuion code (usually 0x111)
|
||||
// executable_test : test executable on virtual page : 0xc, 0xbad : value of t2 modified by execution code (usually 0x111)
|
||||
// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_baremetal : satp.MODE = bare metal : None : None
|
||||
// goto_sv39 : satp.MODE = sv39 : None : None
|
||||
// goto_sv48 : satp.MODE = sv48 : None : None
|
||||
// write_mxr_sum : write sstatus.[19:18] = MXR, SUM bits : None : None
|
||||
// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_m_mode : go to machine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// write_pmpcfg_x : Write one of the pmpcfg csr's : mstatuses?, 0xD : readback of pmpcfg value
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ INIT_TESTS
|
|||
|
||||
TRAP_HANDLER m
|
||||
|
||||
# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode.
|
||||
# Test 5.2.3.6: Test that all the machine mode CSR's are inaccessible for reads and writes in S mode.
|
||||
|
||||
GOTO_S_MODE 0x0, 0x0
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ INIT_TESTS
|
|||
|
||||
TRAP_HANDLER m
|
||||
|
||||
# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode.
|
||||
# Test 5.2.3.6: Test that all the machine mode CSR's are inaccessible for reads and writes in R mode.
|
||||
|
||||
GOTO_U_MODE 0x0, 0x0
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ INIT_TESTS
|
|||
|
||||
TRAP_HANDLER m
|
||||
|
||||
// Test 5.3.2.4: testing that accesses to sub-word memory acceses not on a word boundary go
|
||||
// Test 5.3.2.4: testing that accesses to sub-word memory accesses not on a word boundary go
|
||||
// correctly with the relevant status bit indicating endianness for each mode.
|
||||
// do this by going to each mode with and testing loads with the big endian bit on and off work correctly
|
||||
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ INIT_TESTS
|
|||
TRAP_HANDLER m
|
||||
// Test 5.3.2.2: Machine ISA register test
|
||||
|
||||
// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs.
|
||||
// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unknown value CSRs.
|
||||
csrr x30, misa // should not cause a fault in machine mode. *** not writing to output because MISA is different for different configs.
|
||||
li x7, 0x111 // success value for read of nonzero misa
|
||||
bnez x30, misa_nonzero
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ test_cases:
|
|||
|
||||
# =========== test 11.3.1.1 Page Table Translation ===========
|
||||
|
||||
# test 11.3.1.1.1 write page tables / entries to phyiscal memory
|
||||
# test 11.3.1.1.1 write page tables / entries to physical memory
|
||||
# sv32 Page table (See Figure 12.12***):
|
||||
# Level 1 page table, situated at 0x8000D000
|
||||
.4byte 0x8000D000, 0x20004C01, write32_test # points to level 0 page table A
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ test_cases:
|
|||
|
||||
# =========== test 11.3.1.1 Page Table Translation ===========
|
||||
|
||||
# test 11.3.1.1.1 write page tables / entries to phyiscal memory
|
||||
# test 11.3.1.1.1 write page tables / entries to physical memory
|
||||
# sv32 Page table (See Figure 12.12***):
|
||||
# Level 1 page table, situated at 0x8000D000
|
||||
.4byte 0x8000D000, 0x20004C01, write32_test # points to level 0 page table A
|
||||
|
|
@ -180,7 +180,7 @@ test_cases:
|
|||
.4byte 0x3020, 0xBEEF0770, read32_test # Read success when A=0 and SVADU is enabled
|
||||
|
||||
# test 11.3.1.3.7(b) Dirty flag == 0
|
||||
.4byte 0x4658, 0xBEEF0AA0, write32_test # write successs when D=0 and SVADU is enabled
|
||||
.4byte 0x4658, 0xBEEF0AA0, write32_test # write success when D=0 and SVADU is enabled
|
||||
.4byte 0x4658, 0xBEEF0AA0, read32_test # read success when D=0
|
||||
|
||||
# =========== test 11.3.1.4 SATP Register ===========
|
||||
|
|
|
|||
|
|
@ -693,7 +693,7 @@ Intr03BEEF13:
|
|||
li t1, 0b00010000
|
||||
1: bne t1,a0,1b
|
||||
li a0, 0
|
||||
# ========== Received Data Available Intrrupt (ERBFI) & Loop Mode ==========
|
||||
# ========== Received Data Available Interrupt (ERBFI) & Loop Mode ==========
|
||||
# Clear SCR
|
||||
sb x0, 7(t0)
|
||||
Intr03BEEF14:
|
||||
|
|
|
|||
|
|
@ -696,7 +696,7 @@ Intr03BEEF13:
|
|||
li t1, 0b00010000
|
||||
1: bne t1,a0,1b
|
||||
li a0, 0
|
||||
# ========== Received Data Available Intrrupt (ERBFI) & Loop Mode ==========
|
||||
# ========== Received Data Available Interrupt (ERBFI) & Loop Mode ==========
|
||||
# Clear SCR
|
||||
sb x0, 7(t0)
|
||||
Intr03BEEF14:
|
||||
|
|
|
|||
|
|
@ -34,8 +34,8 @@ csrw mtvec, t4 // set the new trap handler to do the pre behavior first.
|
|||
|
||||
GOTO_S_MODE // go to S mode to attempt to turn on virtual memory
|
||||
|
||||
la ra, post_satp // load the address after the failing adress into ra so it doesn't get confused
|
||||
GOTO_SV32 0x0, 0x0 // attempt to turn on virtual memory with satp pointing to an invlaid address. Should cause invalid instruction exception
|
||||
la ra, post_satp // load the address after the failing address into ra so it doesn't get confused
|
||||
GOTO_SV32 0x0, 0x0 // attempt to turn on virtual memory with satp pointing to an invalid address. Should cause invalid instruction exception
|
||||
|
||||
post_satp:
|
||||
j test_end
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@ WRITE_READ_CSR sie, 0x0 // force zeroing out mie CSR.
|
|||
// note that none of these interrupts should be caught or handled.
|
||||
|
||||
jal cause_s_time_interrupt // write this from M mode to attempt to make s time interrupt pending
|
||||
GOTO_S_MODE // this would cause S mode interrupt to fire, but it shouldn't since SIE is zeored out.
|
||||
GOTO_S_MODE // this would cause S mode interrupt to fire, but it shouldn't since SIE is zeroed out.
|
||||
jal cause_s_soft_interrupt
|
||||
# li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
|
||||
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
|
||||
|
|
|
|||
|
|
@ -258,7 +258,7 @@ test_cases:
|
|||
|
||||
# Test cs-sck delay of 0 with sck phase = 0 (implicit half cycle delay)
|
||||
|
||||
.4byte cs_mode, 0x00000000, write32_test # reset cs_mode to auto, all cs and sck mode settings should be defualt
|
||||
.4byte cs_mode, 0x00000000, write32_test # reset cs_mode to auto, all cs and sck mode settings should be default
|
||||
.4byte delay0, 0x00010000, write32_test # set cs-sck delay to 0
|
||||
.4byte tx_data, 0x00000020, write32_test # place 8'h11 into tx_data
|
||||
.4byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
|
||||
|
|
@ -635,23 +635,23 @@ SETUP_PLIC
|
|||
.4byte tx_mark, 0x00000001, write32_test # set transmit watermark to 1 (any entry turns mark off)
|
||||
.4byte sck_div, 0x00000100, write32_test # lower SPI clock rate so read32_tests trigger at correct times
|
||||
#.4byte ie, 0x00000000, write32_test # enable transmit interrupt
|
||||
.4byte ip, 0x00000001, read32_test # tx watermark interupt should be pending
|
||||
.4byte ip, 0x00000001, read32_test # tx watermark interrupt should be pending
|
||||
.4byte 0x0, 0x00000000, readmip_test
|
||||
.4byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo
|
||||
.4byte ip, 0x00000000, read32_test # tx watermark interupt should be off 125
|
||||
.4byte ip, 0x00000000, read32_test # tx watermark interrupt should be off 125
|
||||
.4byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end
|
||||
|
||||
# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark)
|
||||
# test receive watermark interrupt (triggers when entries in rx FIFO > rx watermark)
|
||||
|
||||
.4byte tx_mark, 0x00000000, write32_test # set tx_mark to 0
|
||||
.4byte rx_data, 0x00000022, read32_test # clear one entry from rx FIFO
|
||||
.4byte rx_mark, 0x00000003, write32_test # set recieve watermark to 3
|
||||
.4byte rx_mark, 0x00000003, write32_test # set receive watermark to 3
|
||||
#.4byte ie, 0x0000002, write32_test # enable receive interrupts
|
||||
.4byte ip, 0x00000000, read32_test # rx interrupts should be low (rx FIFO has 3 entries)
|
||||
.4byte rx_mark, 0x00000002, write32_test # set recieve watermark to 2
|
||||
.4byte ip, 0x00000002, read32_test # recieve interrupt should be high
|
||||
.4byte rx_mark, 0x00000002, write32_test # set receive watermark to 2
|
||||
.4byte ip, 0x00000002, read32_test # receive interrupt should be high
|
||||
.4byte 0x0, 0x00000000, readmip_test
|
||||
.4byte rx_data, 0x00000033, read32_test # clear one more entry from recieve FIFO (2 entries)
|
||||
.4byte rx_data, 0x00000033, read32_test # clear one more entry from receive FIFO (2 entries)
|
||||
.4byte ip, 0x00000000, read32_test # receive interrupt should be low
|
||||
.4byte rx_data, 0x00000044, read32_test
|
||||
.4byte rx_data, 0x00000055, read32_test # clear rx fifo
|
||||
|
|
@ -659,25 +659,25 @@ SETUP_PLIC
|
|||
|
||||
.4byte tx_mark, 0x00000001, write32_test # set transmit watermark to 0
|
||||
.4byte ie, 0x00000001, write32_test # enable transmit interrupt
|
||||
.4byte ip, 0x00000001, read32_test # tx watermark interupt should be pending
|
||||
.4byte ip, 0x00000001, read32_test # tx watermark interrupt should be pending
|
||||
.4byte 0x0, 0x00000800, readmip_test
|
||||
.4byte ie, 0x00000000, write32_test # disable tx intr
|
||||
.4byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo
|
||||
.4byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end
|
||||
|
||||
# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark)
|
||||
# test receive watermark interrupt (triggers when entries in rx FIFO > rx watermark)
|
||||
|
||||
.4byte tx_mark, 0x00000000, write32_test
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts
|
||||
.4byte rx_data, 0x00000022, read32_test # clear one entry from rx FIFO
|
||||
.4byte rx_mark, 0x00000003, write32_test # set recieve watermark to 3
|
||||
.4byte rx_mark, 0x00000003, write32_test # set receive watermark to 3
|
||||
.4byte ie, 0x0000002, write32_test # enable receive interrupts
|
||||
.4byte ip, 0x00000000, read32_test # rx interrupts should be low (rx FIFO has 3 entries)
|
||||
.4byte 0x0, 0x00000000, readmip_test
|
||||
.4byte rx_mark, 0x00000002, write32_test # set recieve watermark to 2
|
||||
.4byte ip, 0x00000002, read32_test # recieve interrupt should be high
|
||||
.4byte rx_mark, 0x00000002, write32_test # set receive watermark to 2
|
||||
.4byte ip, 0x00000002, read32_test # receive interrupt should be high
|
||||
.4byte 0x0, 0x00000800, readmip_test
|
||||
.4byte rx_data, 0x00000033, read32_test # clear one more entry from recieve FIFO (2 entries)
|
||||
.4byte rx_data, 0x00000033, read32_test # clear one more entry from receive FIFO (2 entries)
|
||||
.4byte 0x0, 0x00000000, claim_m_plic_interrupts
|
||||
.4byte ip, 0x00000000, read32_test # receive interrupt should be low
|
||||
.4byte 0x0, 0x00000000, readmip_test
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ INIT_TESTS
|
|||
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
|
||||
|
||||
TRAP_HANDLER m, EXT_SIGNATURE=1 // necessary so we can go to S mode
|
||||
TRAP_HANDLER s, EXT_SIGNATURE=1 // neccessary to handle s mode interrupts.
|
||||
TRAP_HANDLER s, EXT_SIGNATURE=1 // necessary to handle s mode interrupts.
|
||||
|
||||
li x28, 0x2
|
||||
csrs sstatus, x28 // set sstatus.SIE bit to 1
|
||||
|
|
|
|||
|
|
@ -68,7 +68,7 @@ li a3, 0x40
|
|||
jal cause_m_ext_interrupt
|
||||
|
||||
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
|
||||
// We can tell which one becuase the different trap handler modes write different bits of the status register
|
||||
// We can tell which one because the different trap handler modes write different bits of the status register
|
||||
// to the output when EXT_SIGNATURE is on.
|
||||
|
||||
GOTO_M_MODE // so we can write the delegate registers
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@ jal cause_store_addr_misaligned
|
|||
jal cause_store_acc
|
||||
jal cause_ecall
|
||||
|
||||
// some interrupts excluded becaus writing SIP/MIP is illegal from U mode
|
||||
// some interrupts excluded because writing SIP/MIP is illegal from U mode
|
||||
jal cause_m_soft_interrupt
|
||||
jal cause_m_time_interrupt
|
||||
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
|
||||
|
|
@ -65,7 +65,7 @@ li a3, 0x40
|
|||
jal cause_m_ext_interrupt
|
||||
|
||||
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
|
||||
// We can tell which one becuase the different trap handler modes write different bits of the status register
|
||||
// We can tell which one because the different trap handler modes write different bits of the status register
|
||||
// to the output when EXT_SIGNATURE is on.
|
||||
|
||||
GOTO_M_MODE // so we can write the delegate registers
|
||||
|
|
|
|||
|
|
@ -87,7 +87,7 @@ TEST_STACK_AND_DATA
|
|||
|
||||
// in your isa
|
||||
// first claim the plic's uart interrupt by reading the claim register corresponding to 10 on context 0.
|
||||
// then you'll read all entires in the fifo.
|
||||
// then you'll read all entries in the fifo.
|
||||
// then you'll write the completed plic register to 10 on context 0.
|
||||
// claim and completed have the same address.
|
||||
// then you'll return by mret.
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ ffffffff
|
|||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000002 # read 32 bits success in PLIC (confriming 32 bit write)
|
||||
00000002 # read 32 bits success in PLIC (confirming 32 bit write)
|
||||
00000000
|
||||
00000007 # write 16 bits with access fault in PLIC
|
||||
00000000
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@
|
|||
00000000
|
||||
00000bad
|
||||
00000000
|
||||
00000111 # execute sucess when X=1
|
||||
00000111 # execute success when X=1
|
||||
00000000
|
||||
00000009 # ecall from terminating tests in S mode
|
||||
00000000
|
||||
|
|
|
|||
|
|
@ -270,9 +270,9 @@
|
|||
00000000
|
||||
00000022 #clear 1 frame from rx fifo
|
||||
00000000
|
||||
00000000 # read recieve ip
|
||||
00000000 # read receive ip
|
||||
00000000
|
||||
00000002 #read recieve ip
|
||||
00000002 #read receive ip
|
||||
00000000
|
||||
00000000 #read mip
|
||||
00000000
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire.
|
||||
00000000 # Note here that we attempt to cause an interrupt after zeroing status.mie, but it shouldn't fire.
|
||||
0000000b # mcause for ecall from terminating tests in M mode
|
||||
00000000
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
00000000 # stval for ssoft interrupt (0x0)
|
||||
00000000
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire.
|
||||
00000000 # Note here that we attempt to cause an interrupt after zeroing status.mie, but it shouldn't fire.
|
||||
00000009 # mcause for ecall from terminating tests in S mode
|
||||
00000000
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF)
|
|||
00000000
|
||||
00000003 # mcause from Breakpoint
|
||||
00000000
|
||||
80000458 # mtval of breakpoint instruction adress (0x80000458)
|
||||
80000458 # mtval of breakpoint instruction address (0x80000458)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -31,7 +31,7 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF)
|
|||
00000000
|
||||
00000005 # mcause from load access
|
||||
00000000
|
||||
00000000 # mtval of accessed adress (0x0)
|
||||
00000000 # mtval of accessed address (0x0)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -131,7 +131,7 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF)
|
|||
00000000
|
||||
00000003 # mcause from Breakpoint
|
||||
00000000
|
||||
80000458 # mtval of breakpoint instruction adress (0x80000458)
|
||||
80000458 # mtval of breakpoint instruction address (0x80000458)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -143,7 +143,7 @@ FFFFFFFF # mtval of faulting instruction (0xFFFFFFFF)
|
|||
00000000
|
||||
00000005 # mcause from load access
|
||||
00000000
|
||||
00000000 # mtval of accessed adress (0x0)
|
||||
00000000 # mtval of accessed address (0x0)
|
||||
00000000
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
|||
00000000
|
||||
00000003 # scause from Breakpoint
|
||||
00000000
|
||||
80000458 # stval of breakpoint instruction adress (0x80000400)
|
||||
80000458 # stval of breakpoint instruction address (0x80000400)
|
||||
00000000
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -32,7 +32,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
|||
00000000
|
||||
00000005 # scause from load access
|
||||
00000000
|
||||
00000000 # stval of accessed adress (0x0)
|
||||
00000000 # stval of accessed address (0x0)
|
||||
00000000
|
||||
00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -122,7 +122,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
|||
00000000
|
||||
00000003 # scause from Breakpoint
|
||||
00000000
|
||||
80000458 # stval of breakpoint instruction adress (0x80000400)
|
||||
80000458 # stval of breakpoint instruction address (0x80000400)
|
||||
00000000
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
|
|
@ -134,7 +134,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
|||
00000000
|
||||
00000005 # scause from load access
|
||||
00000000
|
||||
00000000 # stval of accessed adress (0x0)
|
||||
00000000 # stval of accessed address (0x0)
|
||||
00000000
|
||||
00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
|||
00000000
|
||||
00000003 # scause from Breakpoint
|
||||
00000000
|
||||
80000458 # stval of breakpoint instruction adress (0x80000400)
|
||||
80000458 # stval of breakpoint instruction address (0x80000400)
|
||||
00000000
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -32,7 +32,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
|||
00000000
|
||||
00000005 # scause from load access
|
||||
00000000
|
||||
00000000 # stval of accessed adress (0x0)
|
||||
00000000 # stval of accessed address (0x0)
|
||||
00000000
|
||||
00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
|
||||
00000000
|
||||
|
|
@ -116,7 +116,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
|||
00000000
|
||||
00000003 # scause from Breakpoint
|
||||
00000000
|
||||
80000458 # stval of breakpoint instruction adress (0x80000400)
|
||||
80000458 # stval of breakpoint instruction address (0x80000400)
|
||||
00000000
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
|
|
@ -128,7 +128,7 @@ FFFFFFFF # stval of faulting instruction (0xFFFFFFFF)
|
|||
00000000
|
||||
00000005 # scause from load access
|
||||
00000000
|
||||
00000000 # stval of accessed adress (0x0)
|
||||
00000000 # stval of accessed address (0x0)
|
||||
00000000
|
||||
00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
|
||||
00000000
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ RVTEST_CODE_BEGIN
|
|||
|
||||
.endm
|
||||
|
||||
// Code to trigger traps goes here so we have consistent mtvals for instruction adresses
|
||||
// Code to trigger traps goes here so we have consistent mtvals for instruction addresses
|
||||
// Even if more tests are added.
|
||||
.macro CAUSE_TRAP_TRIGGERS
|
||||
j end_trap_triggers
|
||||
|
|
@ -82,10 +82,10 @@ cause_instr_addr_misaligned:
|
|||
ret
|
||||
|
||||
cause_instr_access:
|
||||
sd ra, -8(sp) // push the return adress onto the stack
|
||||
sd ra, -8(sp) // push the return address onto the stack
|
||||
addi sp, sp, -8
|
||||
jalr zero // cause instruction access trap (address zero is an address with no memory)
|
||||
ld ra, 0(sp) // pop return adress back from the stack
|
||||
ld ra, 0(sp) // pop return address back from the stack
|
||||
addi sp, sp, 8
|
||||
ret
|
||||
|
||||
|
|
@ -266,7 +266,7 @@ end_trap_triggers:
|
|||
.if (\MODE\() == m)
|
||||
csrrw tp, \MODE\()tvec, ra // tp reserved for "default" trap handler address that needs to be restored before halting this test.
|
||||
.else
|
||||
csrw \MODE\()tvec, ra // we only neet save the machine trap handler and this if statement ensures it isn't overwritten
|
||||
csrw \MODE\()tvec, ra // we only need save the machine trap handler and this if statement ensures it isn't overwritten
|
||||
.endif
|
||||
|
||||
li a0, 0
|
||||
|
|
@ -303,8 +303,8 @@ end_trap_triggers:
|
|||
// 0x0 : defaults to next instruction on the same page the trap was called on.
|
||||
//
|
||||
// a2 (x12):
|
||||
// Pagetype of the current address VPN before changing privilge mode
|
||||
// Used so that we can know how many bits of the adress are the offset.
|
||||
// Pagetype of the current address VPN before changing privilege mode
|
||||
// Used so that we can know how many bits of the address are the offset.
|
||||
// Ignored if a1 == 0x0
|
||||
// 0: Kilopage
|
||||
// 1: Megapage
|
||||
|
|
@ -315,7 +315,7 @@ end_trap_triggers:
|
|||
|
||||
.align 6
|
||||
trap_handler_\MODE\():
|
||||
j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
|
||||
j trap_unvectored_\MODE\() // for the unvectored implementation: jump past this table of addresses into the actual handler
|
||||
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
|
||||
// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
|
||||
// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
|
||||
|
|
@ -333,10 +333,10 @@ trap_handler_\MODE\():
|
|||
// 12 through >=16 are reserved or designated for platform use
|
||||
|
||||
trap_unvectored_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
// *** NOTE: this means that nested traps will be screwed up but they shouldn't happen in any of these tests
|
||||
|
||||
trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since we already switch sp and scratch there
|
||||
trap_stack_saved_\MODE\(): // jump here after handling vectored interrupt since we already switch sp and scratch there
|
||||
// save registers on stack before using
|
||||
sd ra, -8(sp)
|
||||
sd t0, -16(sp)
|
||||
|
|
@ -502,37 +502,37 @@ breakpt_\MODE\():
|
|||
// note: does not mess up any registers, saves and restores them to the stack instead.
|
||||
|
||||
s_soft_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
sd t0, -8(sp) // put t0 on the scratch stack before messing with it
|
||||
li t0, 0x7EC01 // write 0x7ec01 (for "VEC"tored and 01 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
m_soft_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
sd t0, -8(sp) // put t0 on the scratch stack before messing with it
|
||||
li t0, 0x7EC03 // write 0x7ec03 (for "VEC"tored and 03 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
s_time_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
sd t0, -8(sp) // put t0 on the scratch stack before messing with it
|
||||
li t0, 0x7EC05 // write 0x7ec05 (for "VEC"tored and 05 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
m_time_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
sd t0, -8(sp) // put t0 on the scratch stack before messing with it
|
||||
li t0, 0x7EC07 // write 0x7ec07 (for "VEC"tored and 07 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
s_ext_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
sd t0, -8(sp) // put t0 on the scratch stack before messing with it
|
||||
li t0, 0x7EC09 // write 0x7ec09 (for "VEC"tored and 08 for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
||||
m_ext_vector_\MODE\():
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap hanler without messing up sp's value or the stack itself.
|
||||
csrrw sp, \MODE\()scratch, sp // swap sp and scratch so we can use the scratch stack in the trap handler without messing up sp's value or the stack itself.
|
||||
sd t0, -8(sp) // put t0 on the scratch stack before messing with it
|
||||
li t0, 0x7EC0B // write 0x7ec0B (for "VEC"tored and 0B for the interrupt code)
|
||||
j vectored_int_end_\MODE\()
|
||||
|
|
@ -665,12 +665,12 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
|
|||
// read32_test : Read 32 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// read16_test : Read 16 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// read08_test : Read 8 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex
|
||||
// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of t2 modified by exectuion code (usually 0x111)
|
||||
// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of t2 modified by execution code (usually 0x111)
|
||||
// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_baremetal : satp.MODE = bare metal : None : None
|
||||
// goto_sv39 : satp.MODE = sv39 : None : None
|
||||
// goto_sv48 : satp.MODE = sv48 : None : None
|
||||
// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_m_mode : go to machine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR
|
||||
|
|
@ -864,7 +864,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
|
|||
|
||||
.macro EXECUTE_AT_ADDRESS ADDR
|
||||
// Execute the code already written to ADDR, returning the value in t2.
|
||||
// Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR
|
||||
// Note: this test itself doesn't write the code to ADDR because it might be called at a point where we dont have write access to ADDR
|
||||
// Assumes the code modifies t2, usually to become 0x111.
|
||||
// Sample code: 0x11100393 (li t2, 0x111), 0x00008067 (ret)
|
||||
// Success outputs:
|
||||
|
|
@ -965,13 +965,13 @@ test_loop:
|
|||
// read32_test : Read 32 bitsfrom address : 0xd, 0xbad : readvalue in hex
|
||||
// read16_test : Read 16 bitsfrom address : 0xd, 0xbad : readvalue in hex
|
||||
// read08_test : Read 8 bitsfrom address : 0xd, 0xbad : readvalue in hex
|
||||
// executable_test : test executable on virtual page : 0xc, 0xbad : value of t2 modified by exectuion code (usually 0x111)
|
||||
// executable_test : test executable on virtual page : 0xc, 0xbad : value of t2 modified by execution code (usually 0x111)
|
||||
// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_baremetal : satp.MODE = bare metal : None : None
|
||||
// goto_sv39 : satp.MODE = sv39 : None : None
|
||||
// goto_sv48 : satp.MODE = sv48 : None : None
|
||||
// write_mxr_sum : write sstatus.[19:18] = MXR, SUM bits : None : None
|
||||
// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_m_mode : go to machine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8
|
||||
// write_pmpcfg_x : Write one of the pmpcfg csr's : mstatuses?, 0xD : readback of pmpcfg value
|
||||
|
|
|
|||
|
|
@ -30,10 +30,10 @@ INIT_TESTS
|
|||
|
||||
TRAP_HANDLER m
|
||||
|
||||
# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode.
|
||||
# Test 5.2.3.6: Test that all the machine mode CSR's are inaccessible for reads and writes in S mode.
|
||||
|
||||
# *** several of these appear not to be implemented in the assembler?
|
||||
# I get "assembler messages: error: unkown CSR" with many of them.
|
||||
# I get "assembler messages: error: unknown CSR" with many of them.
|
||||
|
||||
GOTO_S_MODE 0x0, 0x0
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ INIT_TESTS
|
|||
|
||||
TRAP_HANDLER m
|
||||
|
||||
# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode.
|
||||
# Test 5.2.3.6: Test that all the machine mode CSR's are inaccessible for reads and writes in R mode.
|
||||
|
||||
GOTO_U_MODE 0x0, 0x0
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ INIT_TESTS
|
|||
|
||||
TRAP_HANDLER m
|
||||
|
||||
// Test 5.3.2.4: testing that accesses to sub-word memory acceses not on a word boundary go
|
||||
// Test 5.3.2.4: testing that accesses to sub-word memory accesses not on a word boundary go
|
||||
// correctly with the relevant status bit indicating endianness for each mode.
|
||||
// do this by going to each mode with and testing loads with the big endian bit on and off work correctly
|
||||
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ TRAP_HANDLER m
|
|||
|
||||
// Test 5.3.2.2: Machine ISA register test
|
||||
|
||||
// Misa is a specific case so I don't want to add a whole test case for reading nonzero but unkown value CSRs.
|
||||
// Misa is a specific case so I don't want to add a whole test case for reading nonzero but unknown value CSRs.
|
||||
csrr x30, misa // should not cause a fault in machine mode. not writing to output because MISA is different for different configs.
|
||||
li x7, 0x111 // success value for read of nonzero misa
|
||||
bnez x30, misa_nonzero
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ test_cases:
|
|||
|
||||
# =========== test 11.3.1.1 Page Table Translation ===========
|
||||
|
||||
# test 11.3.1.1.1 write page tables / entries to phyiscal memory
|
||||
# test 11.3.1.1.1 write page tables / entries to physical memory
|
||||
# sv39 page table (See Figure 12.12***):
|
||||
# Level 2 page table, situated at 0x8000D000
|
||||
.8byte 0x000000008000D000, 0x0000000020004C01, write64_test# points to level 1 page table A
|
||||
|
|
@ -92,7 +92,7 @@ test_cases:
|
|||
|
||||
# test 11.3.1.1.2 write values to Paddrs in each page
|
||||
# each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments.
|
||||
# when a test is supposed to fault, nothing is written into where it'll be reading/executing since it shuold fault before getting there.
|
||||
# when a test is supposed to fault, nothing is written into where it'll be reading/executing since it should fault before getting there.
|
||||
.8byte 0x80200AB0, 0x0000DEADBEEF0000, write64_test# 11.3.1.1.4 and 11.3.1.4.1
|
||||
.8byte 0x800FFAB8, 0x0880DEADBEEF0055, write64_test# 11.3.1.1.4
|
||||
.8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test# 11.3.1.3.2
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ test_cases:
|
|||
|
||||
# =========== test 11.3.1.1 Page Table Translation ===========
|
||||
|
||||
# test 11.3.1.1.1 write page tables / entries to phyiscal memory
|
||||
# test 11.3.1.1.1 write page tables / entries to physical memory
|
||||
# sv39 page table (See Figure 12.12***):
|
||||
# Level 2 page table, situated at 0x8000D000
|
||||
.8byte 0x000000008000D000, 0x0000000020004C01, write64_test# points to level 1 page table A
|
||||
|
|
@ -113,7 +113,7 @@ test_cases:
|
|||
|
||||
# test 11.3.1.1.2 write values to Paddrs in each page
|
||||
# each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments.
|
||||
# when a test is supposed to fault, nothing is written into where it'll be reading/executing since it shuold fault before getting there.
|
||||
# when a test is supposed to fault, nothing is written into where it'll be reading/executing since it should fault before getting there.
|
||||
.8byte 0x80200AB0, 0x0000DEADBEEF0000, write64_test # 11.3.1.1.4 and 11.3.1.4.1
|
||||
.8byte 0x800FFAB8, 0x0880DEADBEEF0055, write64_test # 11.3.1.1.4
|
||||
.8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ test_cases:
|
|||
|
||||
# =========== test 11.3.1.1 Page Table Translation ===========
|
||||
|
||||
# test 11.3.1.1.1 write page tables / entries to phyiscal memory
|
||||
# test 11.3.1.1.1 write page tables / entries to physical memory
|
||||
# sv48 page table (See Figure 12.12***):
|
||||
# Level 3 page table, situated at 0x8000D000
|
||||
.8byte 0x000000008000D000, 0x0000000020004C01, write64_test # points to level 2 page table A
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ test_cases:
|
|||
|
||||
# =========== test 11.3.1.1 Page Table Translation ===========
|
||||
|
||||
# test 11.3.1.1.1 write page tables / entries to phyiscal memory
|
||||
# test 11.3.1.1.1 write page tables / entries to physical memory
|
||||
# sv48 page table (See Figure 12.12***):
|
||||
# Level 3 page table, situated at 0x8000D000
|
||||
.8byte 0x000000008000D000, 0x0000000020004C01, write64_test # points to level 2 page table A
|
||||
|
|
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|||
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|
@ -693,7 +693,7 @@ Intr03BEEF13:
|
|||
li t1, 0b00010000
|
||||
1: bne t1,a0,1b
|
||||
li a0, 0
|
||||
# ========== Received Data Available Intrrupt (ERBFI) & Loop Mode ==========
|
||||
# ========== Received Data Available Interrupt (ERBFI) & Loop Mode ==========
|
||||
# Clear SCR
|
||||
sb x0, 7(t0)
|
||||
Intr03BEEF14:
|
||||
|
|
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|||
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|
@ -34,8 +34,8 @@ csrw mtvec, t4 // set the new trap handler to do the pre behavior first.
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|||
|
||||
GOTO_S_MODE // go to S mode to attempt to turn on virtual memory
|
||||
|
||||
la ra, post_satp // load the address after the failing adress into ra so it doesn't get confused
|
||||
GOTO_SV39 0x0, 0x0 // attempt to turn on virtual memory with satp pointing to an invlaid address. Should cause invalid instruction exception
|
||||
la ra, post_satp // load the address after the failing address into ra so it doesn't get confused
|
||||
GOTO_SV39 0x0, 0x0 // attempt to turn on virtual memory with satp pointing to an invalid address. Should cause invalid instruction exception
|
||||
|
||||
post_satp:
|
||||
j test_end
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ WRITE_READ_CSR sie, 0x0 // force zeroing out mie CSR.
|
|||
// note that none of these interrupts should be caught or handled.
|
||||
|
||||
jal cause_s_time_interrupt // write this from M mode to attempt to make s time interrupt pending
|
||||
GOTO_S_MODE // this would cause S mode interrupt to fire, but it shouldn't since SIE is zeored out.
|
||||
GOTO_S_MODE // this would cause S mode interrupt to fire, but it shouldn't since SIE is zeroed out.
|
||||
jal cause_s_soft_interrupt
|
||||
li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
|
||||
// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
|
||||
|
|
|
|||
|
|
@ -262,7 +262,7 @@ test_cases:
|
|||
|
||||
# Test cs-sck delay of 0 with sck phase = 0 (implicit half cycle delay)
|
||||
|
||||
.8byte cs_mode, 0x00000000, write32_test # reset cs_mode to auto, all cs and sck mode settings should be defualt
|
||||
.8byte cs_mode, 0x00000000, write32_test # reset cs_mode to auto, all cs and sck mode settings should be default
|
||||
.8byte delay0, 0x00010000, write32_test # set cs-sck delay to 0
|
||||
.8byte tx_data, 0x00000020, write32_test # place 8'h11 into tx_data
|
||||
.8byte 0x0, 0x00000000, spi_data_wait # wait for transmission to end
|
||||
|
|
@ -646,23 +646,23 @@ SETUP_PLIC
|
|||
.8byte sck_div, 0x00000100, write32_test # lower SPI clock rate so reads are done at correct time when ICACHE not supported
|
||||
.8byte tx_mark, 0x00000001, write32_test # set transmit watermark to 1 (any entry turns mark off)
|
||||
#.8byte ie, 0x00000000, write32_test # enable transmit interrupt
|
||||
.8byte ip, 0x00000001, read32_test # tx watermark interupt should be pending
|
||||
.8byte ip, 0x00000001, read32_test # tx watermark interrupt should be pending
|
||||
.8byte 0x0, 0x00000000, readmip_test
|
||||
.8byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo
|
||||
.8byte ip, 0x00000000, read32_test # tx watermark interupt should be off 125
|
||||
.8byte ip, 0x00000000, read32_test # tx watermark interrupt should be off 125
|
||||
.8byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end
|
||||
|
||||
# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark)
|
||||
# test receive watermark interrupt (triggers when entries in rx FIFO > rx watermark)
|
||||
|
||||
.8byte tx_mark, 0x00000000, write32_test # set tx_mark to 0
|
||||
.8byte rx_data, 0x00000022, read32_test # clear one entry from rx FIFO
|
||||
.8byte rx_mark, 0x00000003, write32_test # set recieve watermark to 3
|
||||
.8byte rx_mark, 0x00000003, write32_test # set receive watermark to 3
|
||||
#.8byte ie, 0x0000002, write32_test # enable receive interrupts
|
||||
.8byte ip, 0x00000000, read32_test # rx interrupts should be low (rx FIFO has 3 entries)
|
||||
.8byte rx_mark, 0x00000002, write32_test # set recieve watermark to 2
|
||||
.8byte ip, 0x00000002, read32_test # recieve interrupt should be high
|
||||
.8byte rx_mark, 0x00000002, write32_test # set receive watermark to 2
|
||||
.8byte ip, 0x00000002, read32_test # receive interrupt should be high
|
||||
.8byte 0x0, 0x00000000, readmip_test
|
||||
.8byte rx_data, 0x00000033, read32_test # clear one more entry from recieve FIFO (2 entries)
|
||||
.8byte rx_data, 0x00000033, read32_test # clear one more entry from receive FIFO (2 entries)
|
||||
.8byte ip, 0x00000000, read32_test # receive interrupt should be low
|
||||
.8byte rx_data, 0x00000044, read32_test
|
||||
.8byte rx_data, 0x00000055, read32_test # clear rx fifo
|
||||
|
|
@ -670,25 +670,25 @@ SETUP_PLIC
|
|||
|
||||
.8byte tx_mark, 0x00000001, write32_test # set transmit watermark to 0
|
||||
.8byte ie, 0x00000001, write32_test # enable transmit interrupt
|
||||
.8byte ip, 0x00000001, read32_test # tx watermark interupt should be pending
|
||||
.8byte ip, 0x00000001, read32_test # tx watermark interrupt should be pending
|
||||
.8byte 0x0, 0x00000800, readmip_test
|
||||
.8byte ie, 0x00000000, write32_test # disable tx intr
|
||||
.8byte tx_data, 0x55443322, spi_burst_send # place 4 entries in transmit fifo
|
||||
.8byte 0x0, 0x00000003, spi_data_wait # wait for transmission to end
|
||||
|
||||
# test recieve watermark interrupt (triggers when entries in rx FIFO > rx watermark)
|
||||
# test receive watermark interrupt (triggers when entries in rx FIFO > rx watermark)
|
||||
|
||||
.8byte tx_mark, 0x00000000, write32_test
|
||||
.8byte 0x0, 0x00000000, claim_m_plic_interrupts
|
||||
.8byte rx_data, 0x00000022, read32_test # clear one entry from rx FIFO
|
||||
.8byte rx_mark, 0x00000003, write32_test # set recieve watermark to 3
|
||||
.8byte rx_mark, 0x00000003, write32_test # set receive watermark to 3
|
||||
.8byte ie, 0x0000002, write32_test # enable receive interrupts
|
||||
.8byte ip, 0x00000000, read32_test # rx interrupts should be low (rx FIFO has 3 entries)
|
||||
.8byte 0x0, 0x00000000, readmip_test
|
||||
.8byte rx_mark, 0x00000002, write32_test # set recieve watermark to 2
|
||||
.8byte ip, 0x00000002, read32_test # recieve interrupt should be high
|
||||
.8byte rx_mark, 0x00000002, write32_test # set receive watermark to 2
|
||||
.8byte ip, 0x00000002, read32_test # receive interrupt should be high
|
||||
.8byte 0x0, 0x00000800, readmip_test
|
||||
.8byte rx_data, 0x00000033, read32_test # clear one more entry from recieve FIFO (2 entries)
|
||||
.8byte rx_data, 0x00000033, read32_test # clear one more entry from receive FIFO (2 entries)
|
||||
.8byte 0x0, 0x00000000, claim_m_plic_interrupts
|
||||
.8byte ip, 0x00000000, read32_test # receive interrupt should be low
|
||||
.8byte 0x0, 0x00000000, readmip_test
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ INIT_TESTS
|
|||
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
|
||||
|
||||
TRAP_HANDLER m, EXT_SIGNATURE=1 // necessary so we can go to S mode
|
||||
TRAP_HANDLER s, EXT_SIGNATURE=1 // neccessary to handle s mode interrupts.
|
||||
TRAP_HANDLER s, EXT_SIGNATURE=1 // necessary to handle s mode interrupts.
|
||||
|
||||
li x28, 0x2
|
||||
csrs sstatus, x28 // set sstatus.SIE bit to 1
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ li a3, 0x40
|
|||
jal cause_m_ext_interrupt
|
||||
|
||||
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
|
||||
// We can tell which one becuase the different trap handler modes write different bits of the status register
|
||||
// We can tell which one because the different trap handler modes write different bits of the status register
|
||||
// to the output when EXT_SIGNATURE is on.
|
||||
|
||||
GOTO_M_MODE // so we can write the delegate registers
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ jal cause_store_addr_misaligned
|
|||
jal cause_store_acc
|
||||
jal cause_ecall
|
||||
|
||||
// some interrupts excluded becaus writing SIP/MIP is illegal from U mode
|
||||
// some interrupts excluded because writing SIP/MIP is illegal from U mode
|
||||
jal cause_m_soft_interrupt
|
||||
jal cause_m_time_interrupt
|
||||
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
|
||||
|
|
@ -64,7 +64,7 @@ li a3, 0x40
|
|||
jal cause_m_ext_interrupt
|
||||
|
||||
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
|
||||
// We can tell which one becuase the different trap handler modes write different bits of the status register
|
||||
// We can tell which one because the different trap handler modes write different bits of the status register
|
||||
// to the output when EXT_SIGNATURE is on.
|
||||
|
||||
GOTO_M_MODE // so we can write the delegate registers
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue