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https://github.com/openhwgroup/cvw.git
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Merge pull request #1411 from rosethompson/main
Fixes Misalgined Instruction Page Fault
This commit is contained in:
David Harris
GitHub
commit
56e6749eec
8 changed files with 180 additions and 11 deletions
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@ -70,7 +70,7 @@ module ebufsmarb (
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case (CurrState)
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IDLE: if (both) NextState = ARBITRATE;
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else NextState = IDLE;
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ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq)) NextState = IDLE;
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ARBITRATE: if (HREADY & FinalBeatD & ~both) NextState = IDLE;
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else NextState = ARBITRATE;
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default: NextState = IDLE;
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endcase
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@ -80,7 +80,7 @@ module ebufsmarb (
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// Controller 0 (IFU)
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assign IFUSave = CurrState == IDLE & both;
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assign IFURestore = CurrState == ARBITRATE;
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assign IFUDisable = CurrState == ARBITRATE;
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assign IFUDisable = IFURestore;
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assign IFUSelect = (NextState == ARBITRATE) ? 1'b0 : IFUReq;
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// Controller 1 (LSU)
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// When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
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@ -89,7 +89,8 @@ module ebufsmarb (
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// This is necessary because the pipeline is stalled for the entire duration of both transactions,
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// and the LSU memory request will still be active.
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flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqDelay);
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assign LSUDisable = (CurrState == ARBITRATE) ? 1'b0 : (IFUReqDelay & ~(HREADY & FinalBeatD));
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//assign LSUDisable = (CurrState != ARBITRATE) & (IFUReqDelay & ~(HREADY & FinalBeatD));
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assign LSUDisable = (CurrState != ARBITRATE) & IFUReqDelay;
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assign LSUSelect = (NextState == ARBITRATE) ? 1'b1: LSUReq;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@ -64,6 +64,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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output logic [31:0] InstrM, // The decoded instruction in Memory stage
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output logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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output logic [P.XLEN-1:0] PCM, // Memory stage instruction address
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output logic [P.XLEN-1:0] PCSpillM, // Memory stage instruction address
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// branch predictor
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output logic [3:0] IClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
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output logic BPDirWrongM, // Prediction direction is wrong
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@ -149,13 +150,23 @@ module ifu import cvw::*; #(parameter cvw_t P) (
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/////////////////////////////////////////////////////////////////////////////////////////////
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if(P.ZCA_SUPPORTED) begin : Spill
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logic [P.XLEN-1:0] PCSpillD, PCSpillE;
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logic [P.XLEN-1:0] PCIncrM;
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logic SelSpillF, SelSpillD, SelSpillE, SelSpillM;
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spill #(P) spill(.clk, .reset, .StallF, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .CacheableF,
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.IFUCacheBusStallF, .ITLBMissOrUpdateAF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
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.IFUCacheBusStallF, .ITLBMissOrUpdateAF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .SelSpillF, .PostSpillInstrRawF, .CompressedF);
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flopenr #(1) SpillDReg(clk, reset, ~StallD, SelSpillF, SelSpillD);
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flopenr #(1) SpillEReg(clk, reset, ~StallE, SelSpillD, SelSpillE);
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flopenr #(1) SpillMReg(clk, reset, ~StallM, SelSpillE, SelSpillM);
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assign PCIncrM = PCM + 'd2;
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mux2 #(P.XLEN) pcspillmmux(PCM, PCIncrM, SelSpillM, PCSpillM);
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end else begin : NoSpill
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assign PCSpillNextF = PCNextF;
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assign PCSpillF = PCF;
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assign PostSpillInstrRawF = InstrRawF;
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assign {SelSpillNextF, CompressedF} = '0;
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assign PCSpillM = PCM;
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end
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////////////////////////////////////////////////////////////////////////////////////////////////
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@ -44,6 +44,7 @@ module spill import cvw::*; #(parameter cvw_t P) (
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output logic [P.XLEN-1:0] PCSpillNextF, // The next PCF for one of the two memory addresses of the spill
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output logic [P.XLEN-1:0] PCSpillF, // PCF for one of the two memory addresses of the spill
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output logic SelSpillNextF, // During the transition between the two spill operations, the IFU should stall the pipeline
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output logic SelSpillF, // Select incremented PC on a spill
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output logic [31:0] PostSpillInstrRawF,// The final 32 bit instruction after merging the two spilled fetches into 1 instruction
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output logic CompressedF); // The fetched instruction is compressed
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@ -54,7 +55,6 @@ module spill import cvw::*; #(parameter cvw_t P) (
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logic [P.XLEN-1:0] PCPlus2NextF, PCPlus2F;
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logic TakeSpillF;
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logic SpillF;
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logic SelSpillF;
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logic SpillSaveF;
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logic [15:0] InstrFirstHalfF;
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logic EarlyCompressedF;
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@ -36,6 +36,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
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input logic [31:0] InstrM, // current instruction
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input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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input logic [P.XLEN-1:0] PCM, // program counter, next PC going to trap/return logic
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input logic [P.XLEN-1:0] PCSpillM, // program counter, next PC going to trap/return logic aligned after an instruction spill
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input logic [P.XLEN-1:0] SrcAM, IEUAdrxTvalM, // SrcA and memory address from IEU
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input logic CSRReadM, CSRWriteM, // read or write CSR
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input logic TrapM, // trap is occurring
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@ -140,7 +141,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
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always_comb
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if (InterruptM) NextFaultMtvalM = '0;
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else case (CauseM)
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12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint
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12, 1, 3: NextFaultMtvalM = PCSpillM; // Instruction page/access faults, breakpoint
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2: NextFaultMtvalM = {{(P.XLEN-32){1'b0}}, InstrOrigM}; // Illegal instruction fault
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0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrxTvalM; // Instruction misaligned, Load/Store Misaligned/page/access faults
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default: NextFaultMtvalM = '0; // Ecall, interrupts
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@ -39,6 +39,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL
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input logic [P.XLEN-1:0] IEUAdrxTvalM, // address from IEU
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input logic [P.XLEN-1:0] PCM, // program counter
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input logic [P.XLEN-1:0] PCSpillM, // program counter
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// control signals
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input logic InstrValidM, // Current instruction is valid (not flushed)
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input logic CommittedM, CommittedF, // current instruction is using bus; don't interrupt
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@ -133,7 +134,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
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// Control and Status Registers
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csr #(P) csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW,
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.InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrxTvalM,
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.InstrM, .InstrOrigM, .PCM, .PCSpillM, .SrcAM, .IEUAdrxTvalM,
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.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
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.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
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.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
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@ -62,7 +62,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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logic [31:0] InstrD;
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logic [31:0] InstrM, InstrOrigM;
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logic [P.XLEN-1:0] PCSpillF, PCE, PCLinkE;
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logic [P.XLEN-1:0] PCM;
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logic [P.XLEN-1:0] PCM, PCSpillM;
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logic [P.XLEN-1:0] CSRReadValW, MDUResultW;
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logic [P.XLEN-1:0] EPCM, TrapVectorM;
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logic [1:0] MemRWE;
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@ -184,7 +184,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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.PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPWrongE, .BPWrongM,
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// Mem
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.CommittedF, .EPCM, .TrapVectorM, .RetM, .TrapM, .InvalidateICacheM, .CSRWriteFenceM,
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.InstrD, .InstrM, .InstrOrigM, .PCM, .IClassM, .BPDirWrongM,
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.InstrD, .InstrM, .InstrOrigM, .PCM, .PCSpillM, .IClassM, .BPDirWrongM,
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.BTAWrongM, .RASPredPCWrongM, .IClassWrongM,
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// Faults out
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.IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM,
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@ -289,7 +289,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
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privileged #(P) priv(
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.clk, .reset,
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.FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
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.CSRReadM, .CSRWriteM, .SrcAM, .PCM,
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.CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCSpillM,
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.InstrM, .InstrOrigM, .CSRReadValW, .EPCM, .TrapVectorM,
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.RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF,
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.InstrValidM, .CommittedM, .CommittedF,
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155
tests/coverage/WALLY-init-lib-misalignedSpill.h
Normal file
155
tests/coverage/WALLY-init-lib-misalignedSpill.h
Normal file
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@ -0,0 +1,155 @@
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///////////////////////////////////////////
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// WALLY-init-lib.h
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//
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// Written: David_Harris@hmc.edu 21 March 2023
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//
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// Purpose: Initialize stack, handle interrupts, terminate test case
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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// The PMP tests are sensitive to the exact addresses in this code, so unfortunately
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// modifying anything breaks those tests.
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.section .text.init
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.global rvtest_entry_point
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rvtest_entry_point:
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la sp, topofstack # Initialize stack pointer (not used)
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# Set up interrupts
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la t0, trap_handler
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csrw mtvec, t0 # Initialize MTVEC to trap_handler
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csrw mideleg, zero # Don't delegate interrupts
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csrw medeleg, zero # Don't delegate exceptions
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# li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
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# li t1, 0x02004000 # MTIMECMP in CLINT
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# sd t0, 0(t1)
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li t0, 0x80
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# li t0, 0x00
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csrw mie, t0 # Enable machine timer interrupt
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la t0, topoftrapstack
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csrw mscratch, t0 # MSCRATCH holds trap stack pointer
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csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable
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# set up PMP so user and supervisor mode can access full address space
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csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX
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li t0, 0xFFFFFFFF
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csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
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j main # Call main function in user test program
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done:
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li a0, 4 # argument to finish program
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ecall # system call to finish program
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j self_loop # wait forever (not taken)
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.align 4 # trap handlers must be aligned to multiple of 4
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trap_handler:
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# Load trap handler stack pointer tp
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csrrw tp, mscratch, tp # swap MSCRATCH and tp
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sd t0, 0(tp) # Save t0 and t1 on the stack
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sd t1, -8(tp)
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csrr t0, mcause # Check the cause
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csrr t1, mtval # And the trap value
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bgez t0, exception # if msb is clear, it is an exception
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interrupt: # must be a timer interrupt
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li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
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li t1, 0x02004000 # MTIMECMP in CLIN
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sd t0, 0(t1)
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csrw stimecmp, t0 # sets stimecmp to big number so it doesnt interrupt
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li t0, 32
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csrc sip, t0 # clears stimer interrupt
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j trap_return # clean up and return
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exception:
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csrr t0, mcause
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li t1, 0xC # is it an instruction page fault
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li a0, 3 # set a0 to 3 to ecall looks like a program terminate
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beq t0, t1, ecall # terminate program for instruction page fault
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li t1, 8 # is it an ecall trap?
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andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
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bne t0, t1, trap_return # ignore other exceptions
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ecall:
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li t0, 4
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beq a0, t0, write_tohost # call 4: terminate program
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bltu a0, t0, changeprivilege # calls 0-3: change privilege level
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j trap_return # ignore other ecalls
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changeprivilege:
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li t0, 0x00001800 # mask off mstatus.MPP in bits 11-12
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csrc mstatus, t0
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andi a0, a0, 0x003 # only keep bottom two bits of argument
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slli a0, a0, 11 # move into mstatus.MPP position
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csrs mstatus, a0 # set mstatus.MPP with desired privilege
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trap_return: # return from trap handler
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csrr t0, mepc # get address of instruction that caused exception
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li t1, 0x20000
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csrs mstatus, t1 # set mprv bit to fetch instruction with permission of code that trapped
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lh t0, 0(t0) # get instruction that caused exception
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csrc mstatus, t1 # clear mprv bit to restore normal operation
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li t1, 3
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and t0, t0, t1 # mask off upper bits
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beq t0, t1, instr32 # if lower 2 bits are 11, instruction is uncompresssed
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li t0, 2 # increment PC by 2 for compressed instruction
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j updateepc
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instr32:
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li t0, 4
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updateepc:
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csrr t1, mepc # add 2 or 4 (from t0) to MEPC to determine return Address
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add t1, t1, t0
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csrw mepc, t1
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ld t1, -8(tp) # restore t1 and t0
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ld t0, 0(tp)
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csrrw tp, mscratch, tp # restore tp
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mret # return from trap
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write_tohost:
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la t1, tohost
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li t0, 1 # 1 for success, 3 for failure
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sd t0, 0(t1) # send success code
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self_loop:
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j self_loop # wait
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.section .tohost
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tohost: # write to HTIF
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.dword 0
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fromhost:
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.dword 0
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.EQU XLEN,64
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begin_signature:
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.fill 6*(XLEN/32),4,0xdeadbeef #
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end_signature:
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# Initialize stack with room for 512 bytes
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.bss
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.space 512
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topofstack:
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# And another stack for the trap handler
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.bss
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.space 512
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topoftrapstack:
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.align 4
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.section .text.main
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@ -26,7 +26,7 @@
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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#include "WALLY-init-lib-misalignedSpill.h"
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# run-elf.bash find this in project description
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main:
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