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Fixed the icache and dcache overlogging issue.

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This commit is contained in:
Ross Thompson 2023-07-14 15:47:05 -05:00
parent 141c1b9dfb
commit 59022099c7
1 changed files with 2 additions and 0 deletions
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2
testbench/common/loggers.sv
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@ -138,6 +138,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn &
dut.core.ifu.immu.immu.pmachecker.Cacheable &
~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage &
dut.core.ifu.bus.icache.icache.cachefsm.CacheEn &
~reset;
flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD;
@ -190,6 +191,7 @@ module loggers import cvw::*; #(parameter cvw_t P,
assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn &
(AccessTypeString != "NULL");
initial begin